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path: root/drivers/clk
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2019-08-24Merge tag 'u-boot-rockchip-20190823' of ↵Tom Rini1-0/+12
https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - remove rk3288 fennec board - remove SPL raw image support for Rockchip SoCs - add common misc_init_r() for ethaddr from cpuid - enable USB HOST support for rk3328 - unify code for finding a valid gpt in part driver
2019-08-23rockchip: clk: rk3328: add clk_enable ops for HCLK_HOST0Kever Yang1-0/+12
Required to successfully probe the ehci generic driver Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-08-22clk: imx: add i.MX8MM clk driverPeng Fan2-0/+417
Add i.MX8MM clk driver support. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-08-22clk: imx: add i.MX8M composite clk supportPeng Fan1-0/+170
Import i.MX8M composite clk from Linux Kernel 5.3.0-rc2 Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-08-22clk: imx: add pll14xx driverPeng Fan2-0/+406
Add pll14xx driver for i.MX8MM usage, modifed from Linux Kernel 5.3.0-rc1 Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-08-22clk: imx: expose CCF entry for allPeng Fan2-2/+16
Expose CCF entry, then we could avoid expand the SoC support list Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-08-22sandbox: clk: add clk enable/disable test codePeng Fan1-0/+15
Since we added clk enable_count and prograte clk child enabling operation to clk parent, so add a new function sandbox_clk_enable_count to get enable_count for test usage. And add test code to get the enable_count after we enable/disable the device clk. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-08-22clk: prograte clk enable/disable to parentPeng Fan1-6/+71
On i.MX8MM, thinking such as clk path OSC->PLL->PLL GATE->CCM ROOT->CCGR GATE->Device Only enabling CCGR GATE is not enough, we also need to enable PLL GATE to make sure the clk path work. So when enabling CCGR GATE, we could prograte to enabling PLL GATE to make life easier. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-08-22clk: introduce enable_countPeng Fan2-0/+2
As what Linux Kernel 5.3.0 provides when enable/disable clk, there is an enable_count in clk_core_disable/enable. Introduce enable_count to track the clk enable/disable count when clk_enable/disable for CCF. And Initialize enable_count to 0 when register the clk. And clk tree dump with enable_count will be supported, it will be easy for us to check the clk status with enable_count Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-08-12clk: add support for clk_is_match()Sekhar Nori1-0/+13
Add support for clk_is_match() which is required to know if two clock pointers point to the same exact physical clock. Also add a unit test for the new API. Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2019-08-09clk: renesas: Add R8A77980 V3H clock tablesMarek Vasut3-0/+262
Import R8A77980 V3H clock tables from Linux 5.2.7 , commit 5697a9d3d55f. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-08-07clk: MediaTek: add hifsys entry for MT7623 SoC.Ryder Lee3-23/+51
This adds high speed interface subsystem - hifsys (i.e. PCIe and USB) for MT7623 SoC and enables its reset controller. The control block is shared with ethsys and accordingly rename the related defines. Tested-by: Frank Wunderlich <frank-w@public-files.de> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
2019-08-02Merge https://gitlab.denx.de/u-boot/custodians/u-boot-clkTom Rini12-14/+681
- Port more CCF code to work with i.MX8 devices.
2019-07-31clk: meson: remove duplicate logicHeinrich Schuchardt1-4/+1
First thing we check in meson_clk_set_rate_by_id() is current_rate == rate. There is not need to check it again. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-07-31clk: sandbox: add composite clkPeng Fan1-0/+80
Add composite clk to sandbox driver Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-31clk: gate: support sandboxPeng Fan1-0/+11
Introduce io_gate_val for sandbox clk gate test usage Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-31clk: add composite clk supportPeng Fan3-0/+175
Import clk composite clk support from Linux Kernel 5.1-rc5 Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-31dm: clk: ignore default settings when node not validPeng Fan1-0/+3
When the device not binded with a node, we need ignore the parents and rate settings. Cc: Simon Glass <sjg@chromium.org> Cc: Jagan Teki <jagan@amarulasolutions.com> Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Cc: Neil Armstrong <narmstrong@baylibre.com> Cc: Andreas Dannenberg <dannenberg@ti.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-31clk: imx: gate2 add set ratePeng Fan1-0/+11
Add set rate for imx clk-gate2 Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-31clk: imx: import clk heplersPeng Fan1-0/+81
Import some clk helpers from Linux Kernel for i.MX8MM usage Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-31clk: fixed_rate: export clk_fixed_ratePeng Fan1-7/+1
Export the structure for others to use. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-31clk: divider set rate supporrtPeng Fan1-0/+88
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-31clk: add clk-gate supportPeng Fan2-1/+149
Import clk-gate support from Linux Kernel 5.1-rc5 Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-31clk: mux: add set parent supportPeng Fan1-2/+68
Add set parent support for clk mux Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-31clk: use clk_dev_bindedPeng Fan2-4/+6
Preparing to support composite clk. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-31clk: introduce clk_dev_bindedPeng Fan1-0/+8
When support Clock Common Framework, U-Boot use dev for clk tree information, there is no clk->parent. When support composite clk, it contains mux/gate/divider, but the mux/gate/divider is not binded with device. So we could not use dev_get_uclass_priv to get the correct clk_mux/gate/divider. So add clk_dev_binded to let choose the correct method. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-29Merge tag 'u-boot-rockchip-20190729' of ↵Tom Rini1-0/+3
https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - Clean up and migrate to use common rockchip spl board file - Clean up and migrate to use common rockchip board file - Increase rk3288 CONFIG_SYS_BOOTM_LEN to 16MB
2019-07-29rockchip: rk3188: init CPU freq in clock driverKever Yang1-0/+3
Init CPU frquency in clock driver instead of in SPL board file, this will help for use common board file later. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-27Merge tag 'u-boot-imx-20190719' of ↵Tom Rini17-6/+1280
https://gitlab.denx.de/u-boot/custodians/u-boot-imx u-boot-imx-20190719 - CCF for i.MX6 - nandbcb command to write SPL into NAND - Switch to DM (i.MX28) - Boards: Toradex, engicam, DH - Fixes for i.MX8 - Fixes for i.MX7ULP Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/561147504
2019-07-24clk: initialize clk->data when using default xlateSekhar Nori1-0/+2
Right now when using clk_of_xlate_default(), clk->data remains un-initialized because clk_get_bulk() does not initialize memory on allocation of clock structure. This can cause problems when data is used to match if two clocks pointers are exactly the same underlying clocks, for example. Fix it by initializing clk->data to 0. Suggested-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2019-07-23Merge tag 'u-boot-stm32-20190723' of ↵Tom Rini1-0/+9
https://gitlab.denx.de/u-boot/custodians/u-boot-stm - add rtc driver for stm32mp1 - add remoteproc driver for stm32mp1 - use kernel qspi compatible string for stm32
2019-07-22clk: stm32mp1: Add RTC clock entryPatrick Delaunay1-0/+9
Add RTCAPB and RTC clock support. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-07-21Merge tag 'rockchip-for-v2019.07' of ↵Tom Rini1-37/+51
https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - rk3399 lpddr4 support - rk3399-rock960 board support improvement - Eliminate pyelftools dependency by make_fit_atf.py - clean up rockchip dts to use -u-boot.dtsi - use ARM arch/generic timer instead of rk_timer - clean up Kconfig options for board support
2019-07-21clk: rockchip: rk3399: Set 400MHz ddr clockJagan Teki1-0/+4
Add support for setting 400MHz ddr clock. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-21clk: rockchip: rk3399: Set 50MHz ddr clockJagan Teki1-0/+4
Add support for setting 50MHz ddr clock. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19clk: sandbox: Add sandbox test code for Common Clock Framework [CCF]Lukasz Majewski3-1/+195
This patch provides code to implement the CCF clock tree in sandbox. It uses all the introduced primitives; some generic ones are reused, some sandbox specific were developed. In that way (after introducing the real CCF tree in sandbox) the recently added to clk-uclass.c: clk_get_by_id() and clk_get_parent_rate() are tested in their natural work environment. Usage (sandbox_defconfig and sandbox_flattree_defconfig): ./u-boot --fdt arch/sandbox/dts/test.dtb --command "ut dm clk_ccf" Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-07-19clk: sandbox: Adjust clk-mux.c to emulate reading divider value from HWLukasz Majewski1-1/+9
The generic mux clock code for CCF requires reading the clock multiplexer value from HW registers. As sandbox by design has readl() as no-op it was necessary to provide this value in the other way. The new field in the mux structure (accessible only when sandbox is run) has been introduced for this purpose. Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-07-19clk: sandbox: Adjust clk-divider to emulate reading its value from HWLukasz Majewski1-1/+9
The generic divider clock code for CCF requires reading the divider value from HW registers. As sandbox by design has readl() as no-op it was necessary to provide this value in the other way. The new field in the divider structure (accessible only when sandbox is run) has been introduced for this purpose. Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-07-19dm: clk: Extend clk_get_parent_rate() to support CLK_GET_RATE_NOCACHE flagLukasz Majewski1-2/+2
If the CLK_GET_RATE_NOCACHE flag is set - the clk_get_parent_rate() provides recalculated clock value without considering the cache setting. This may be necessary for some clocks tightly coupled with power domains (i.e. imx8), and prevents from reading invalid cached values. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-07-19clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12)Lukasz Majewski13-0/+1005
This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-07-19dm: clk: Define clk_get_by_id() for clk operationsLukasz Majewski1-0/+22
This commit adds the clk_get_by_id() function, which is responsible for getting the udevice with matching clk->id. Such approach allows re-usage of inherit DM list relationship for the same class (UCLASS_CLK). As a result - we don't need any other external list - it is just enough to look for UCLASS_CLK related udevices. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-07-19dm: clk: Define clk_get_parent_rate() for clk operationsLukasz Majewski1-0/+22
This commit adds the clk_get_parent_rate() function, which is responsible for getting the rate of parent clock. Unfortunately, u-boot's DM support for getting parent is different (the parent relationship is in udevice) than the one in Common Clock Framework [CCF] in Linux. To alleviate this problem - the clk_get_parent_rate() function has been introduced to clk-uclass.c. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-07-19dm: clk: Define clk_get_parent() for clk operationsLukasz Majewski1-0/+16
This commit adds the clk_get_parent() function, which is responsible for getting the parent's struct clock pointer. U-Boot's DM support for getting parent is different (the parent relationship is in udevice) than the one in Common Clock Framework [CCF] in Linux. To obtain the pointer to struct clk of parent the pdev->uclass_priv field is read via dev_get_clk_ptr() wrapper. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-07-19clk: Provide struct clk for fixed rate clock (clk_fixed_rate.c)Lukasz Majewski1-0/+5
Up till now the fixed rate clock ('osc') has been added to UCLASS_CLK without declaring struct clk. As a result it was only accessible by iterating the udevice's uclass list. This is a problem for clock code, which operates on pointers to struct clk (like clk_get_rate()), not udevices. After this change struct clk is accessible from udevice and udevice from struct clk. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-07-19clk: Remove clock ID check in .get_rate() of clk_fixed_*Lukasz Majewski2-6/+0
This check requires the struct clk passed to .get_rate() to be always cleared out as any clock with valid ID causes -EINVAL return value. The return code of fixed clocks shall always be returned. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-07-19clk: sifive: Drop GEMGXL clock driverAnup Patel3-69/+0
The GEMGXL clock driver is now directly part of Cadence MACB ethernet driver in upstream Linux kernel. There is no separate GEMGXL clock driver in upstream Linux kernel hence we drop GEMGXL clock driver from U-Boot as well. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-19clk: sifive: Sync-up main driver with upstream LinuxAnup Patel1-36/+60
The DT bindings of SiFive clock driver in upstream Linux has changes. As-per latest DT bindings, the clock driver takes two parent clocks and compatible string has also changed. This patch sync-up SiFive clock driver implementation as-per upstream Linux so that we now use latest DT bindings. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-19clk: sifive: Sync-up DT bindings header with upstream LinuxAnup Patel1-1/+1
The location and license header of DT bindings header for SiFive clock driver has changed in upstream Linux hence this patch. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-19clk: sifive: Sync-up WRPLL library with upstream LinuxAnup Patel2-108/+83
Now that SiFive clock driver is merged in upstream Linux, we sync-up WRPLL library used by SiFive clock driver with upstream Linux sources. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-19clk: sifive: Factor-out PLL library as separate moduleAnup Patel9-110/+11
To match SiFive clock driver with latest Linux, we factor-out PLL library as separate module under drivers/clk/analogbits. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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