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path: root/drivers/clk
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2019-08-24Merge tag 'u-boot-rockchip-20190823' of https://gitlab.denx.de/u-boot/custodi...Tom Rini1-0/+12
2019-08-23rockchip: clk: rk3328: add clk_enable ops for HCLK_HOST0Kever Yang1-0/+12
2019-08-22clk: imx: add i.MX8MM clk driverPeng Fan2-0/+417
2019-08-22clk: imx: add i.MX8M composite clk supportPeng Fan1-0/+170
2019-08-22clk: imx: add pll14xx driverPeng Fan2-0/+406
2019-08-22clk: imx: expose CCF entry for allPeng Fan2-2/+16
2019-08-22sandbox: clk: add clk enable/disable test codePeng Fan1-0/+15
2019-08-22clk: prograte clk enable/disable to parentPeng Fan1-6/+71
2019-08-22clk: introduce enable_countPeng Fan2-0/+2
2019-08-12clk: add support for clk_is_match()Sekhar Nori1-0/+13
2019-08-09clk: renesas: Add R8A77980 V3H clock tablesMarek Vasut3-0/+262
2019-08-07clk: MediaTek: add hifsys entry for MT7623 SoC.Ryder Lee3-23/+51
2019-08-02Merge https://gitlab.denx.de/u-boot/custodians/u-boot-clkTom Rini12-14/+681
2019-07-31clk: meson: remove duplicate logicHeinrich Schuchardt1-4/+1
2019-07-31clk: sandbox: add composite clkPeng Fan1-0/+80
2019-07-31clk: gate: support sandboxPeng Fan1-0/+11
2019-07-31clk: add composite clk supportPeng Fan3-0/+175
2019-07-31dm: clk: ignore default settings when node not validPeng Fan1-0/+3
2019-07-31clk: imx: gate2 add set ratePeng Fan1-0/+11
2019-07-31clk: imx: import clk heplersPeng Fan1-0/+81
2019-07-31clk: fixed_rate: export clk_fixed_ratePeng Fan1-7/+1
2019-07-31clk: divider set rate supporrtPeng Fan1-0/+88
2019-07-31clk: add clk-gate supportPeng Fan2-1/+149
2019-07-31clk: mux: add set parent supportPeng Fan1-2/+68
2019-07-31clk: use clk_dev_bindedPeng Fan2-4/+6
2019-07-31clk: introduce clk_dev_bindedPeng Fan1-0/+8
2019-07-29Merge tag 'u-boot-rockchip-20190729' of https://gitlab.denx.de/u-boot/custodi...Tom Rini1-0/+3
2019-07-29rockchip: rk3188: init CPU freq in clock driverKever Yang1-0/+3
2019-07-27Merge tag 'u-boot-imx-20190719' of https://gitlab.denx.de/u-boot/custodians/u...Tom Rini17-6/+1280
2019-07-24clk: initialize clk->data when using default xlateSekhar Nori1-0/+2
2019-07-23Merge tag 'u-boot-stm32-20190723' of https://gitlab.denx.de/u-boot/custodians...Tom Rini1-0/+9
2019-07-22clk: stm32mp1: Add RTC clock entryPatrick Delaunay1-0/+9
2019-07-21Merge tag 'rockchip-for-v2019.07' of https://gitlab.denx.de/u-boot/custodians...Tom Rini1-37/+51
2019-07-21clk: rockchip: rk3399: Set 400MHz ddr clockJagan Teki1-0/+4
2019-07-21clk: rockchip: rk3399: Set 50MHz ddr clockJagan Teki1-0/+4
2019-07-19clk: sandbox: Add sandbox test code for Common Clock Framework [CCF]Lukasz Majewski3-1/+195
2019-07-19clk: sandbox: Adjust clk-mux.c to emulate reading divider value from HWLukasz Majewski1-1/+9
2019-07-19clk: sandbox: Adjust clk-divider to emulate reading its value from HWLukasz Majewski1-1/+9
2019-07-19dm: clk: Extend clk_get_parent_rate() to support CLK_GET_RATE_NOCACHE flagLukasz Majewski1-2/+2
2019-07-19clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12)Lukasz Majewski13-0/+1005
2019-07-19dm: clk: Define clk_get_by_id() for clk operationsLukasz Majewski1-0/+22
2019-07-19dm: clk: Define clk_get_parent_rate() for clk operationsLukasz Majewski1-0/+22
2019-07-19dm: clk: Define clk_get_parent() for clk operationsLukasz Majewski1-0/+16
2019-07-19clk: Provide struct clk for fixed rate clock (clk_fixed_rate.c)Lukasz Majewski1-0/+5
2019-07-19clk: Remove clock ID check in .get_rate() of clk_fixed_*Lukasz Majewski2-6/+0
2019-07-19clk: sifive: Drop GEMGXL clock driverAnup Patel3-69/+0
2019-07-19clk: sifive: Sync-up main driver with upstream LinuxAnup Patel1-36/+60
2019-07-19clk: sifive: Sync-up DT bindings header with upstream LinuxAnup Patel1-1/+1
2019-07-19clk: sifive: Sync-up WRPLL library with upstream LinuxAnup Patel2-108/+83
2019-07-19clk: sifive: Factor-out PLL library as separate moduleAnup Patel9-110/+11
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