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path: root/drivers/clk/renesas
AgeCommit message (Expand)AuthorFilesLines
2022-01-13treewide: invaild -> invalidSean Anderson2-2/+2
2021-06-24clk: renesas: Add R8A779A0 clock tablesHai Pham7-0/+338
2021-06-24clk: renesas: Handle R8A779A0 V3U clock types in Gen3 clock codeMarek Vasut2-0/+33
2021-05-21clk: renesas: Deduplicate gen3_clk_get_rate64() PLL handlingMarek Vasut1-43/+43
2021-05-21clk: renesas: Add register pointers into struct cpg_mssr_infoHai Pham3-45/+65
2021-05-21clk: renesas: Introduce enum clk_reg_layoutHai Pham1-0/+6
2021-05-21clk: renesas: Pass struct cpg_mssr_info to renesas_clk_endisable()Hai Pham4-6/+8
2021-05-21clk: renesas: Make reset controller modemr register offset configurableMarek Vasut20-5/+21
2021-05-21clk: renesas: Add support for RPCD2 clockHai Pham2-5/+17
2021-05-21clk: renesas: Fix Realtime Module Stop Control Register offsetsHai Pham1-1/+1
2021-05-21clk: renesas: Fix incorrect return RPC clk_get_rateHai Pham1-1/+1
2021-05-21clk: renesas: Reinstate RPC clock on R-Car D3/E3Marek Vasut2-0/+18
2021-05-21clk: renesas: Synchronize R-Car Gen3 tables with Linux 5.12Marek Vasut7-163/+212
2021-05-21clk: renesas: Synchronize R-Car Gen2 tables with Linux 5.12Marek Vasut5-9/+6
2021-05-21clk: renesas: Synchronize RZ/G2 tables with Linux 5.12Marek Vasut3-5/+26
2021-04-25clk: renesas: Synchronize Gen2 MSTP teardown tablesMarek Vasut3-6/+6
2021-04-25clk: renesas: Only ever access documented bits in clock driver teardownMarek Vasut7-81/+81
2021-02-02common: Drop asm/global_data.h from common headerSimon Glass2-0/+2
2020-12-13dm: treewide: Rename auto_alloc_size members to be shorterSimon Glass15-15/+15
2020-10-20clk: renesas: Import R8A774C0 clock tables from Linux 5.9Lad Prabhakar3-0/+315
2020-10-20clk: renesas: Add R8A774E1 clock tablesBiju Das3-0/+365
2020-10-20clk: renesas: Add R8A774B1 clock tablesBiju Das3-0/+343
2020-10-20clk: renesas: r8a774a1-cpg-mssr: Add R8A774A1 RPC clockBiju Das1-0/+4
2020-07-27Merge tag 'dm-pull-20jul20-take2a' of https://gitlab.denx.de/u-boot/custodian...Tom Rini2-2/+2
2020-07-25treewide: convert (void *)devfdt_get_addr() to dev_read_addr_ptr()Masahiro Yamada2-2/+2
2020-07-25clk: renesas: Add R8A774A1 clock tablesAdam Ford4-0/+349
2020-07-24Revert "Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm"Tom Rini2-2/+2
2020-07-20treewide: convert (void *)devfdt_get_addr() to dev_read_addr_ptr()Masahiro Yamada2-2/+2
2020-05-18common: Drop linux/bitops.h from common headerSimon Glass14-0/+14
2020-05-18common: Drop log.h from common headerSimon Glass3-0/+3
2020-03-30clk: renesas: Switch to fdtdec_get_addr_size_auto_noparent() on Gen2Marek Vasut1-1/+2
2019-08-09clk: renesas: Add R8A77980 V3H clock tablesMarek Vasut3-0/+262
2019-04-09clk: renesas: Synchronize Gen3 tables with Linux 5.0Marek Vasut8-130/+215
2019-04-09clk: renesas: Synchronize Gen2 tables with Linux 5.0Marek Vasut4-16/+14
2019-04-09clk: renesas: Add R8A77965 clock tablesMarek Vasut4-19/+346
2019-03-25clk: renesas: Add support for setting MMCIF clock divider on Gen2Marek Vasut1-0/+42
2019-03-25clk: renesas: Fix swapped div and mul in debug output on Gen2Marek Vasut1-1/+1
2019-03-25clk: renesas: Fix SDH clock divider decoding on Gen2Marek Vasut1-5/+9
2019-02-25clk: rmobile: Drop def_bool per SoCMarek Vasut1-10/+0
2018-12-03clk: renesas: Allow reconfiguring SDHI clock on Gen3Marek Vasut1-7/+3
2018-06-14clk: rmobile: Add R8A77995 RPC clockMarek Vasut1-0/+5
2018-06-14clk: rmobile: Add R8A77990 RPC clockMarek Vasut1-0/+5
2018-06-02Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini5-32/+386
2018-06-01clk: renesas: Add R8A77990 E3 clock tablesMarek Vasut3-0/+311
2018-06-01clk: renesas: Add PE clock handlingMarek Vasut2-6/+40
2018-06-01clk: renesas: Add PLL1 and PLL3 dividersMarek Vasut1-4/+8
2018-06-01clk: renesas: Pass clock rate around as 64bit number internallyMarek Vasut1-25/+31
2018-06-01clk: renesas: Fix swapped arguments in debug messageMarek Vasut1-1/+1
2018-05-07SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini9-18/+9
2018-05-02clk: renesas: Drop USB extal from the R8A7792 clock driverMarek Vasut1-2/+0