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2024-09-10riscv: show registers in crash dumps by defaultHeinrich Schuchardt1-0/+1
2024-09-10riscv: allow to enable SHOW_REGS in main U-Boot onlyHeinrich Schuchardt2-4/+15
2024-09-10riscv: CONFIG_SPL_FRAMEPOINTER must depend on CONFIG_SPLHeinrich Schuchardt1-0/+1
2024-09-10riscv: define find_{first,next}_zero_bit in asm/bitops.hMaxim Kochetkov1-0/+40
2024-07-22Revert "riscv: dts: jh7110: Enable PLL node in SPL"Leo Yu-Chi Liang1-4/+0
2024-07-22riscv: semihosting: correct alignmentHeinrich Schuchardt1-1/+1
2024-07-22riscv: add RISC-V fields to bdinfo commandHeinrich Schuchardt2-0/+19
2024-06-04Merge tag 'v2024.07-rc4' into nextTom Rini3-8/+2
2024-05-30andes: Use UCCTLCOMMAND instead of MCCTLCOMMANDLeo Yu-Chi Liang2-4/+2
2024-05-30riscv: remove cache enablement in start.SLeo Yu-Chi Liang1-4/+0
2024-05-20Restore patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"Tom Rini1-1/+2
2024-05-19Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""Tom Rini1-2/+1
2024-05-14andes: Unify naming policy for Andes related sourceLeo Yu-Chi Liang6-10/+10
2024-05-14riscv: simplify backtrace reportHeinrich Schuchardt1-11/+5
2024-05-14board: starfive: function to read eMMC sizeHeinrich Schuchardt1-0/+7
2024-05-06global: Make <asm/global_data.h> include <asm/u-boot.h>Tom Rini1-1/+2
2024-05-02board: starfive: Rename spl_soc_init() to spl_dram_init()Lukas Funke2-2/+2
2024-05-02board: sifive: Rename spl_soc_init() to spl_dram_init()Lukas Funke4-4/+4
2024-05-02riscv: dts: sophgo: Add spi nor flash controller nodeKongyang Liu2-0/+30
2024-05-02riscv: dts: sophgo: Add ethernet nodeKongyang Liu2-0/+28
2024-05-01cmd: sbi: add Supervisor Software Events extensionHeinrich Schuchardt1-0/+1
2024-05-01riscv: andesv5: Set default cache line size to 64-bytesYu Chien Peter Lin1-0/+1
2024-04-18Revert "Merge patch series "pxe: Allow extlinux booting without CMDLINE enabl...Tom Rini1-1/+1
2024-04-10Merge patch series "pxe: Allow extlinux booting without CMDLINE enabled"Tom Rini1-1/+1
2024-04-10treewide: Make arch-specific bootm code depend on BOOTMSimon Glass1-1/+1
2024-04-10Merge tag 'xilinx-for-v2024.07-rc1' of https://source.denx.de/u-boot/custodia...Tom Rini1-0/+3
2024-04-09eeprom: starfive: function get_product_id_from_eeprom()Heinrich Schuchardt1-0/+9
2024-04-09riscv: starfive: MMC card detectHeinrich Schuchardt1-1/+1
2024-04-09riscv: Move virtio scan to board_late_init()Łukasz Stelmach1-0/+1
2024-04-09riscv: support extension probing using riscv, isa-extensionsConor Dooley1-21/+35
2024-04-09riscv: don't read riscv, isa in the riscv cpu's get_desc()Conor Dooley1-5/+7
2024-04-09riscv: dts: sophgo: Add clk node and sdhci nodeKongyang Liu3-0/+34
2024-04-09riscv: cache: Implement dcache for cv1800bKongyang Liu2-0/+46
2024-04-09riscv: cpu: cv1800b: Add support for cv1800b SoCKongyang Liu5-0/+49
2024-04-09riscv: add backtrace supportBen Dooks4-0/+60
2024-03-19Merge tag 'u-boot-socfpga-next-20240319' of https://source.denx.de/u-boot/cus...Tom Rini4-8/+22
2024-03-13Kconfig: move CONFIG_32/64BIT to arch/KconfigDan Carpenter1-6/+0
2024-03-12riscv: dts: jh7110: Enable PLL node in SPLBo Gan1-0/+4
2024-03-12riscv: cpu: improve multi-letter extension detection in supports_extension()Conor Dooley1-6/+16
2024-03-12riscv: dts: jh7110: fix indentationLeon M. Busch-George1-1/+1
2024-03-12riscv: sifive: fu740: reduce DDR speed from 1866MT/s to 1600MT/sThomas Perrot1-1/+1
2024-03-01riscv: mbv: Enable SPL and binmanMichal Simek1-0/+3
2024-02-28efi_loader: set IMAGE_DLLCHARACTERISTICS_NX_COMPATHeinrich Schuchardt1-0/+4
2024-01-31riscv: dts: starfive: add regulator deviceNam Cao1-0/+5
2024-01-31riscv: dts: jh7110: add power management unit controller nodeNam Cao1-0/+6
2024-01-31riscv: sophgo: milkv_duo: initial support addedKongyang Liu1-0/+4
2024-01-31riscv: dts: sophgo: add basic device tree for Milk-V Duo boardKongyang Liu4-0/+249
2024-01-31riscv: Support building with Clangkleines Filmröllchen1-1/+1
2024-01-31cmd: sbi: add support for Debug Trigger ExtensionHeinrich Schuchardt1-0/+1
2024-01-31board: sifive: spl: Initialized the PWM setting in the SPL stageVincent Chen1-0/+15