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path: root/arch/riscv/cpu/cpu.c
AgeCommit message (Expand)AuthorFilesLines
2024-04-09riscv: support extension probing using riscv, isa-extensionsConor Dooley1-21/+35
2024-04-09riscv: don't read riscv, isa in the riscv cpu's get_desc()Conor Dooley1-5/+7
2024-03-12riscv: cpu: improve multi-letter extension detection in supports_extension()Conor Dooley1-6/+16
2023-12-21riscv: Add a reset_cpu() functionSimon Glass1-0/+13
2023-10-24riscv: Remove common.h usageTom Rini1-1/+0
2023-09-06riscv: Correct event usage for riscv_cpu_probe/setupTom Rini1-5/+1
2023-09-06riscv: Rework riscv_cpu_probe for current event macrosTom Rini1-2/+2
2023-09-04Merge tag 'v2023.10-rc4' into nextTom Rini1-8/+3
2023-08-31event: Convert existing spy records to simpleSimon Glass1-2/+2
2023-08-22riscv: cpu: make riscv_cpu_probe to EVT_DM_POST_INIT_R callbackChanho Park1-8/+3
2023-05-11dm: Emit the arch_cpu_init_dm() even only before relocationSimon Glass1-1/+1
2023-02-01riscv: cpu: check U-Mode before counteren writeNikita Shubin1-8/+8
2022-11-15riscv: Fix detecting FPU support in standard extensionYu Chien Peter Lin1-3/+11
2022-09-26riscv: Introduce AVAILABLE_HARTSRick Chen1-0/+2
2022-09-26spl: introduce SPL_XIP to configNikita Shubin1-1/+1
2022-03-10event: Convert arch_cpu_init_dm() to use eventsSimon Glass1-1/+4
2021-10-18riscv: Remove OF_PRIOR_STAGE from RISC-V boardsIlias Apalodimas1-3/+0
2021-10-07sysreset: provide SBI based sysreset driverHeinrich Schuchardt1-1/+12
2021-05-24treewide: Convert macro and uses of __section(foo) to __section("foo")Marek BehĂșn1-2/+2
2021-05-05riscv: cpu: Add callback to init each coreGreen Wan1-0/+11
2020-09-30riscv: Clear pending IPIs on initializationSean Anderson1-0/+20
2020-07-24riscv: Make SiFive HiFive Unleashed board boot againBin Meng1-1/+1
2020-07-01riscv: Add option to support RISC-V privileged spec 1.9Sean Anderson1-0/+9
2020-07-01riscv: Clean up IPI initialization codeSean Anderson1-0/+6
2020-05-18common: Drop linux/bitops.h from common headerSimon Glass1-0/+1
2020-05-18common: Drop init.h from common headerSimon Glass1-0/+1
2019-08-26riscv: add run mode configuration for SPLLukas Auer1-3/+3
2019-08-15riscv: Access CSRs using CSR numbersBin Meng1-5/+4
2019-05-09riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE is ena...Rick Chen1-0/+2
2019-05-09riscv: Introduce CONFIG_XIP to support booting from flashRick Chen1-0/+2
2019-04-08riscv: add support for multi-hart systemsLukas Auer1-1/+8
2018-12-18riscv: Do some basic architecture level cpu initializationBin Meng1-1/+26
2018-12-18riscv: Update supports_extension() to use desc from cpu driverBin Meng1-0/+26
2018-12-18riscv: Remove non-DM version of print_cpuinfo()Bin Meng1-37/+0
2018-12-18riscv: Probe cpus during bootBin Meng1-0/+26
2018-11-26riscv: save hart ID and device tree passed by prior boot stageLukas Auer1-0/+6
2018-10-03riscv: Add a helper routine to print CPU informationBin Meng1-0/+49