summaryrefslogtreecommitdiff
path: root/include
diff options
context:
space:
mode:
Diffstat (limited to 'include')
-rw-r--r--include/configs/bk4r1.h33
-rw-r--r--include/configs/colibri_imx7.h2
-rw-r--r--include/configs/ge_bx50v3.h7
-rw-r--r--include/configs/mx6ullevk.h180
-rw-r--r--include/configs/pcm052.h78
-rw-r--r--include/configs/tbs2910.h4
-rw-r--r--include/configs/wandboard.h26
-rw-r--r--include/dt-bindings/clock/imx6ul-clock.h253
-rw-r--r--include/fsl_wdog.h1
-rw-r--r--include/image.h1
-rw-r--r--include/power/rn5t567_pmic.h113
11 files changed, 644 insertions, 54 deletions
diff --git a/include/configs/bk4r1.h b/include/configs/bk4r1.h
new file mode 100644
index 0000000000..5861eeb178
--- /dev/null
+++ b/include/configs/bk4r1.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2016 3ADEV <http://3adev.com>
+ * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
+ *
+ * Configuration settings for the phytec PCM-052 SoM-based BK4R1.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* Define the BK4r1-specific env commands */
+#define PCM052_EXTRA_ENV_SETTINGS \
+ "set_gpio103=mw 0x400ff0c4 0x0080; mw 0x4004819C 0x000011bf\0" \
+ "set_gpio122=mw 0x400481e8 0x0282; mw 0x400ff0c4 0x04000000\0"
+
+/* BK4r1 boot command sets GPIO103/PTC30 to force USB hub out of reset*/
+#define PCM052_BOOTCOMMAND "run set_gpio103; sf probe; "
+
+/* BK4r1 net init sets GPIO122/PTE17 to enable Ethernet */
+#define PCM052_NET_INIT "run set_gpio122; "
+
+/* add NOR to MTD env */
+#define MTDIDS_DEFAULT "nand0=NAND,nor0=NOR"
+#define MTDPARTS_DEFAULT "mtdparts=NAND:640k(bootloader)"\
+ ",128k(env1)"\
+ ",128k(env2)"\
+ ",128k(dtb)"\
+ ",6144k(kernel)"\
+ ",-(root);"\
+ "NOR:-(nor)"
+
+/* now include standard PCM052 config */
+
+#include "configs/pcm052.h"
diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h
index 16ae952f37..55d8fcf4d4 100644
--- a/include/configs/colibri_imx7.h
+++ b/include/configs/colibri_imx7.h
@@ -59,9 +59,7 @@
#undef CONFIG_BOOTM_RTEMS
/* I2C configs */
-#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_IPADDR 192.168.10.2
diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h
index 52f096eec1..c77fef6f24 100644
--- a/include/configs/ge_bx50v3.h
+++ b/include/configs/ge_bx50v3.h
@@ -15,6 +15,7 @@
#include <asm/arch/imx-regs.h>
#include <asm/imx-common/gpio.h>
+#define BX50V3_BOOTARGS_EXTRA
#if defined(CONFIG_TARGET_GE_B450V3)
#define CONFIG_BOARD_NAME "General Electric B450v3"
#define CONFIG_DEFAULT_FDT_FILE "/boot/imx6q-b450v3.dtb"
@@ -24,6 +25,9 @@
#elif defined(CONFIG_TARGET_GE_B850V3)
#define CONFIG_BOARD_NAME "General Electric B850v3"
#define CONFIG_DEFAULT_FDT_FILE "/boot/imx6q-b850v3.dtb"
+#undef BX50V3_BOOTARGS_EXTRA
+#define BX50V3_BOOTARGS_EXTRA "video=DP-1:1024x768@60 " \
+ "video=HDMI-A-1:1024x768@60 "
#else
#define CONFIG_BOARD_NAME "General Electric BA16 Generic"
#define CONFIG_DEFAULT_FDT_FILE "/boot/imx6q-ba16.dtb"
@@ -166,7 +170,8 @@
"echo 'U-Boot upgraded. Please reset'; " \
"fi\0" \
"setargs=setenv bootargs console=${console},${baudrate} " \
- "root=/dev/${rootdev} rw rootwait cma=128M\0" \
+ "root=/dev/${rootdev} rw rootwait cma=128M " \
+ BX50V3_BOOTARGS_EXTRA "\0" \
"loadbootscript=" \
"ext2load ${dev} ${devnum}:${partnum} ${loadaddr} ${script};\0" \
"bootscript=echo Running bootscript from ${dev}:${devnum}:${partnum};" \
diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h
new file mode 100644
index 0000000000..ccce9546b7
--- /dev/null
+++ b/include/configs/mx6ullevk.h
@@ -0,0 +1,180 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX6UL 14x14 EVK board.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __MX6ULLEVK_CONFIG_H
+#define __MX6ULLEVK_CONFIG_H
+
+
+#include <asm/arch/imx-regs.h>
+#include <linux/sizes.h>
+#include "mx6_common.h"
+#include <asm/imx-common/gpio.h>
+
+#ifdef CONFIG_SECURE_BOOT
+#ifndef CONFIG_CSF_SIZE
+#define CONFIG_CSF_SIZE 0x4000
+#endif
+#endif
+
+#define PHYS_SDRAM_SIZE SZ_512M
+
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_MXC_GPIO
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE UART1_BASE
+
+/* MMC Configs */
+#ifdef CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
+
+/* NAND pin conflicts with usdhc2 */
+#ifdef CONFIG_SYS_USE_NAND
+#define CONFIG_SYS_FSL_USDHC_NUM 1
+#else
+#define CONFIG_SYS_FSL_USDHC_NUM 2
+#endif
+#endif
+
+/* I2C configs */
+#ifdef CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_SPEED 100000
+#endif
+
+#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "script=boot.scr\0" \
+ "image=zImage\0" \
+ "console=ttymxc0\0" \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0" \
+ "fdt_file=imx6ull-14x14-evk.dtb\0" \
+ "fdt_addr=0x83000000\0" \
+ "boot_fdt=try\0" \
+ "ip_dyn=yes\0" \
+ "videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \
+ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+ "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+ "mmcautodetect=yes\0" \
+ "mmcargs=setenv bootargs console=${console},${baudrate} " \
+ "root=${mmcroot}\0" \
+ "loadbootscript=" \
+ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source\0" \
+ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if run loadfdt; then " \
+ "bootz ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootz; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootz; " \
+ "fi;\0" \
+ "netargs=setenv bootargs console=${console},${baudrate} " \
+ "root=/dev/nfs " \
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+ "netboot=echo Booting from net ...; " \
+ "run netargs; " \
+ "if test ${ip_dyn} = yes; then " \
+ "setenv get_cmd dhcp; " \
+ "else " \
+ "setenv get_cmd tftp; " \
+ "fi; " \
+ "${get_cmd} ${image}; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+ "bootz ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootz; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootz; " \
+ "fi;\0" \
+
+#define CONFIG_BOOTCOMMAND \
+ "mmc dev ${mmcdev};" \
+ "mmc dev ${mmcdev}; if mmc rescan; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loadimage; then " \
+ "run mmcboot; " \
+ "else run netboot; " \
+ "fi; " \
+ "fi; " \
+ "else run netboot; fi"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x8000000)
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_STACKSIZE SZ_128K
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
+#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
+#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
+
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_SIZE SZ_8K
+#define CONFIG_ENV_OFFSET (12 * SZ_64K)
+
+#define CONFIG_CMD_BMODE
+
+#define CONFIG_IMX_THERMAL
+
+#define CONFIG_IOMUX_LPSR
+
+#define CONFIG_SOFT_SPI
+
+#endif
diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h
index a70c9887e7..0372e4376b 100644
--- a/include/configs/pcm052.h
+++ b/include/configs/pcm052.h
@@ -52,15 +52,20 @@
#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_PARTITIONS
#define CONFIG_MTD_DEVICE
+
+#ifndef MTDIDS_DEFAULT
#define MTDIDS_DEFAULT "nand0=NAND"
-#define MTDPARTS_DEFAULT "mtdparts=NAND:256k(spare)"\
- ",384k(bootloader)"\
+#endif
+
+#ifndef MTDPARTS_DEFAULT
+#define MTDPARTS_DEFAULT "mtdparts=NAND:640k(bootloader)"\
",128k(env1)"\
",128k(env2)"\
",128k(dtb)"\
",6144k(kernel)"\
- ",65536k(ramdisk)"\
- ",450944k(root)"
+ ",-(root)"
+#endif
+
#endif
#define CONFIG_MMC
@@ -87,7 +92,6 @@
/* QSPI Configs*/
#ifdef CONFIG_FSL_QSPI
-#define CONFIG_SPI_FLASH
#define FSL_QSPI_FLASH_SIZE (1 << 24)
#define FSL_QSPI_FLASH_NUM 2
#define CONFIG_SYS_FSL_QSPI_LE
@@ -117,16 +121,38 @@
#define CONFIG_SYS_TEXT_BASE 0x3f408000
#define CONFIG_BOARD_SIZE_LIMIT 524288
-#define CONFIG_BOOTCOMMAND "run bootcmd_sd"
+/* if no target-specific extra environment settings were defined by the
+ target, define an empty one */
+#ifndef PCM052_EXTRA_ENV_SETTINGS
+#define PCM052_EXTRA_ENV_SETTINGS
+#endif
+
+/* if no target-specific boot command was defined by the target,
+ define an empty one */
+#ifndef PCM052_BOOTCOMMAND
+#define PCM052_BOOTCOMMAND
+#endif
+
+/* if no target-specific extra environment settings were defined by the
+ target, define an empty one */
+#ifndef PCM052_NET_INIT
+#define PCM052_NET_INIT
+#endif
+
+/* boot command, including the target-defined one if any */
+#define CONFIG_BOOTCOMMAND PCM052_BOOTCOMMAND "run bootcmd_nand"
+
+/* Extra env settings (including the target-defined ones if any) */
#define CONFIG_EXTRA_ENV_SETTINGS \
+ PCM052_EXTRA_ENV_SETTINGS \
+ "autoload=no\0" \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
- "blimg_file=u-boot.imx\0" \
- "blsec_addr=0x81000000\0" \
- "blimg_addr=0x81000400\0" \
+ "blimg_file=u-boot.vyb\0" \
+ "blimg_addr=0x81000000\0" \
"kernel_file=zImage\0" \
"kernel_addr=0x82000000\0" \
- "fdt_file=vf610-pcm052.dtb\0" \
+ "fdt_file=zImage.dtb\0" \
"fdt_addr=0x81000000\0" \
"ram_file=uRamdisk\0" \
"ram_addr=0x83000000\0" \
@@ -137,14 +163,15 @@
"tftptimeout=1000\0" \
"tftptimeoutcountmax=1000000\0" \
"mtdparts=" MTDPARTS_DEFAULT "\0" \
- "bootargs_base=setenv bootargs rw mem=256M " \
+ "bootargs_base=setenv bootargs rw " \
+ " mem=" __stringify(CONFIG_PCM052_DDR_SIZE) "M " \
"console=ttyLP1,115200n8\0" \
"bootargs_sd=setenv bootargs ${bootargs} " \
"root=/dev/mmcblk0p2 rootwait\0" \
"bootargs_net=setenv bootargs ${bootargs} root=/dev/nfs ip=dhcp " \
"nfsroot=${serverip}:${nfs_root},v3,tcp\0" \
"bootargs_nand=setenv bootargs ${bootargs} " \
- "ubi.mtd=6 rootfstype=ubifs root=ubi0:rootfs\0" \
+ "ubi.mtd=5 rootfstype=ubifs root=ubi0:rootfs\0" \
"bootargs_ram=setenv bootargs ${bootargs} " \
"root=/dev/ram rw initrd=${ram_addr}\0" \
"bootargs_mtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
@@ -163,14 +190,14 @@
"bootcmd_ram=run bootargs_base bootargs_ram bootargs_mtd; " \
"nand read ${fdt_addr} dtb; " \
"nand read ${kernel_addr} kernel; " \
- "nand read ${ram_addr} ramdisk; " \
+ "nand read ${ram_addr} root; " \
"bootz ${kernel_addr} ${ram_addr} ${fdt_addr}\0" \
- "update_bootloader_from_tftp=mtdparts default; " \
- "nand read ${blsec_addr} bootloader; " \
- "mw.b ${blimg_addr} 0xff 0x5FC00; " \
- "if tftp ${blimg_addr} ${tftpdir}${blimg_file}; then " \
+ "update_bootloader_from_tftp=" PCM052_NET_INIT \
+ "if tftp ${blimg_addr} "\
+ "${tftpdir}${blimg_file}; then " \
+ "mtdparts default; " \
"nand erase.part bootloader; " \
- "nand write ${blsec_addr} bootloader ${filesize}; fi\0" \
+ "nand write ${blimg_addr} bootloader ${filesize}; fi\0" \
"update_kernel_from_sd=if fatload mmc 0:2 ${kernel_addr} " \
"${kernel_file}; " \
"then mtdparts default; " \
@@ -179,7 +206,8 @@
"if fatload mmc 0:2 ${fdt_addr} ${fdt_file}; then " \
"nand erase.part dtb; " \
"nand write ${fdt_addr} dtb ${filesize}; fi\0" \
- "update_kernel_from_tftp=if tftp ${fdt_addr} ${tftpdir}${fdt_file}; " \
+ "update_kernel_from_tftp=" PCM052_NET_INIT \
+ "if tftp ${fdt_addr} ${tftpdir}${fdt_file}; " \
"then setenv fdtsize ${filesize}; " \
"if tftp ${kernel_addr} ${tftpdir}${kernel_file}; then " \
"mtdparts default; " \
@@ -187,16 +215,18 @@
"nand write ${fdt_addr} dtb ${fdtsize}; " \
"nand erase.part kernel; " \
"nand write ${kernel_addr} kernel ${filesize}; fi; fi\0" \
- "update_rootfs_from_tftp=if tftp ${sys_addr} ${tftpdir}${filesys}; " \
+ "update_rootfs_from_tftp=" PCM052_NET_INIT \
+ "if tftp ${sys_addr} ${tftpdir}${filesys}; " \
"then mtdparts default; " \
"nand erase.part root; " \
"ubi part root; " \
"ubi create rootfs; " \
"ubi write ${sys_addr} rootfs ${filesize}; fi\0" \
- "update_ramdisk_from_tftp=if tftp ${ram_addr} ${tftpdir}${ram_file}; " \
+ "update_ramdisk_from_tftp=" PCM052_NET_INIT \
+ "if tftp ${ram_addr} ${tftpdir}${ram_file}; " \
"then mtdparts default; " \
- "nand erase.part ramdisk; " \
- "nand write ${ram_addr} ramdisk ${filesize}; fi\0"
+ "nand erase.part root; " \
+ "nand write ${ram_addr} root ${filesize}; fi\0"
/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP /* undef to save memory */
@@ -222,7 +252,7 @@
/* Physical memory map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM (0x80000000)
-#define PHYS_SDRAM_SIZE (256 * 1024 * 1024)
+#define PHYS_SDRAM_SIZE (CONFIG_PCM052_DDR_SIZE * 1024 * 1024)
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h
index 85501bca0f..d8773362a9 100644
--- a/include/configs/tbs2910.h
+++ b/include/configs/tbs2910.h
@@ -39,7 +39,7 @@
#define CONFIG_SYS_MEMTEST_END \
(CONFIG_SYS_MEMTEST_START + 500 * 1024 * 1024)
-#define CONFIG_SYS_BOOTMAPSZ 0x6C000000
+#define CONFIG_SYS_BOOTMAPSZ 0x10000000
/* Serial console */
#define CONFIG_MXC_UART
@@ -56,9 +56,11 @@
/* *** Command definition *** */
#define CONFIG_CMD_BMODE
+#define CONFIG_CMD_PART
/* Filesystems / image support */
#define CONFIG_EFI_PARTITION
+#define CONFIG_PARTITION_UUIDS
/* MMC */
#define CONFIG_SYS_FSL_USDHC_NUM 3
diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h
index 69d0fd5c88..999ee6de97 100644
--- a/include/configs/wandboard.h
+++ b/include/configs/wandboard.h
@@ -116,32 +116,6 @@
"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
"fi; " \
"fi\0" \
- "videoargs=" \
- "setenv nextcon 0; " \
- "if hdmidet; then " \
- "setenv bootargs ${bootargs} " \
- "video=mxcfb${nextcon}:dev=hdmi,1280x720M@60," \
- "if=RGB24; " \
- "setenv fbmen fbmem=28M; " \
- "setexpr nextcon ${nextcon} + 1; " \
- "else " \
- "echo - no HDMI monitor;" \
- "fi; " \
- "i2c dev 1; " \
- "if i2c probe 0x10; then " \
- "setenv bootargs ${bootargs} " \
- "video=mxcfb${nextcon}:dev=lcd,800x480@60," \
- "if=RGB666,bpp=32; " \
- "if test 0 -eq ${nextcon}; then " \
- "setenv fbmem fbmem=10M; " \
- "else " \
- "setenv fbmem ${fbmem},10M; " \
- "fi; " \
- "setexpr nextcon ${nextcon} + 1; " \
- "else " \
- "echo '- no FWBADAPT-7WVGA-LCD-F07A-0102 display';" \
- "fi; " \
- "setenv bootargs ${bootargs} ${fbmem}\0" \
"findfdt="\
"if test $board_name = C1 && test $board_rev = MX6Q ; then " \
"setenv fdtfile imx6q-wandboard.dtb; fi; " \
diff --git a/include/dt-bindings/clock/imx6ul-clock.h b/include/dt-bindings/clock/imx6ul-clock.h
new file mode 100644
index 0000000000..18de070932
--- /dev/null
+++ b/include/dt-bindings/clock/imx6ul-clock.h
@@ -0,0 +1,253 @@
+/*
+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX6UL_H
+#define __DT_BINDINGS_CLOCK_IMX6UL_H
+
+#define IMX6UL_CLK_DUMMY 0
+#define IMX6UL_CLK_CKIL 1
+#define IMX6UL_CLK_CKIH 2
+#define IMX6UL_CLK_OSC 3
+#define IMX6UL_PLL1_BYPASS_SRC 4
+#define IMX6UL_PLL2_BYPASS_SRC 5
+#define IMX6UL_PLL3_BYPASS_SRC 6
+#define IMX6UL_PLL4_BYPASS_SRC 7
+#define IMX6UL_PLL5_BYPASS_SRC 8
+#define IMX6UL_PLL6_BYPASS_SRC 9
+#define IMX6UL_PLL7_BYPASS_SRC 10
+#define IMX6UL_CLK_PLL1 11
+#define IMX6UL_CLK_PLL2 12
+#define IMX6UL_CLK_PLL3 13
+#define IMX6UL_CLK_PLL4 14
+#define IMX6UL_CLK_PLL5 15
+#define IMX6UL_CLK_PLL6 16
+#define IMX6UL_CLK_PLL7 17
+#define IMX6UL_PLL1_BYPASS 18
+#define IMX6UL_PLL2_BYPASS 19
+#define IMX6UL_PLL3_BYPASS 20
+#define IMX6UL_PLL4_BYPASS 21
+#define IMX6UL_PLL5_BYPASS 22
+#define IMX6UL_PLL6_BYPASS 23
+#define IMX6UL_PLL7_BYPASS 24
+#define IMX6UL_CLK_PLL1_SYS 25
+#define IMX6UL_CLK_PLL2_BUS 26
+#define IMX6UL_CLK_PLL3_USB_OTG 27
+#define IMX6UL_CLK_PLL4_AUDIO 28
+#define IMX6UL_CLK_PLL5_VIDEO 29
+#define IMX6UL_CLK_PLL6_ENET 30
+#define IMX6UL_CLK_PLL7_USB_HOST 31
+#define IMX6UL_CLK_USBPHY1 32
+#define IMX6UL_CLK_USBPHY2 33
+#define IMX6UL_CLK_USBPHY1_GATE 34
+#define IMX6UL_CLK_USBPHY2_GATE 35
+#define IMX6UL_CLK_PLL2_PFD0 36
+#define IMX6UL_CLK_PLL2_PFD1 37
+#define IMX6UL_CLK_PLL2_PFD2 38
+#define IMX6UL_CLK_PLL2_PFD3 39
+#define IMX6UL_CLK_PLL3_PFD0 40
+#define IMX6UL_CLK_PLL3_PFD1 41
+#define IMX6UL_CLK_PLL3_PFD2 42
+#define IMX6UL_CLK_PLL3_PFD3 43
+#define IMX6UL_CLK_ENET_REF 44
+#define IMX6UL_CLK_ENET2_REF 45
+#define IMX6UL_CLK_ENET2_REF_125M 46
+#define IMX6UL_CLK_ENET_PTP_REF 47
+#define IMX6UL_CLK_ENET_PTP 48
+#define IMX6UL_CLK_PLL4_POST_DIV 49
+#define IMX6UL_CLK_PLL4_AUDIO_DIV 50
+#define IMX6UL_CLK_PLL5_POST_DIV 51
+#define IMX6UL_CLK_PLL5_VIDEO_DIV 52
+#define IMX6UL_CLK_PLL2_198M 53
+#define IMX6UL_CLK_PLL3_80M 54
+#define IMX6UL_CLK_PLL3_60M 55
+#define IMX6UL_CLK_STEP 56
+#define IMX6UL_CLK_PLL1_SW 57
+#define IMX6UL_CLK_AXI_ALT_SEL 58
+#define IMX6UL_CLK_AXI_SEL 59
+#define IMX6UL_CLK_PERIPH_PRE 60
+#define IMX6UL_CLK_PERIPH2_PRE 61
+#define IMX6UL_CLK_PERIPH_CLK2_SEL 62
+#define IMX6UL_CLK_PERIPH2_CLK2_SEL 63
+#define IMX6UL_CLK_USDHC1_SEL 64
+#define IMX6UL_CLK_USDHC2_SEL 65
+#define IMX6UL_CLK_BCH_SEL 66
+#define IMX6UL_CLK_GPMI_SEL 67
+#define IMX6UL_CLK_EIM_SLOW_SEL 68
+#define IMX6UL_CLK_SPDIF_SEL 69
+#define IMX6UL_CLK_SAI1_SEL 70
+#define IMX6UL_CLK_SAI2_SEL 71
+#define IMX6UL_CLK_SAI3_SEL 72
+#define IMX6UL_CLK_LCDIF_PRE_SEL 73
+#define IMX6UL_CLK_SIM_PRE_SEL 74
+#define IMX6UL_CLK_LDB_DI0_SEL 75
+#define IMX6UL_CLK_LDB_DI1_SEL 76
+#define IMX6UL_CLK_ENFC_SEL 77
+#define IMX6UL_CLK_CAN_SEL 78
+#define IMX6UL_CLK_ECSPI_SEL 79
+#define IMX6UL_CLK_UART_SEL 80
+#define IMX6UL_CLK_QSPI1_SEL 81
+#define IMX6UL_CLK_PERCLK_SEL 82
+#define IMX6UL_CLK_LCDIF_SEL 83
+#define IMX6UL_CLK_SIM_SEL 84
+#define IMX6UL_CLK_PERIPH 85
+#define IMX6UL_CLK_PERIPH2 86
+#define IMX6UL_CLK_LDB_DI0_DIV_3_5 87
+#define IMX6UL_CLK_LDB_DI0_DIV_7 88
+#define IMX6UL_CLK_LDB_DI1_DIV_3_5 89
+#define IMX6UL_CLK_LDB_DI1_DIV_7 90
+#define IMX6UL_CLK_LDB_DI0_DIV_SEL 91
+#define IMX6UL_CLK_LDB_DI1_DIV_SEL 92
+#define IMX6UL_CLK_ARM 93
+#define IMX6UL_CLK_PERIPH_CLK2 94
+#define IMX6UL_CLK_PERIPH2_CLK2 95
+#define IMX6UL_CLK_AHB 96
+#define IMX6UL_CLK_MMDC_PODF 97
+#define IMX6UL_CLK_AXI_PODF 98
+#define IMX6UL_CLK_PERCLK 99
+#define IMX6UL_CLK_IPG 100
+#define IMX6UL_CLK_USDHC1_PODF 101
+#define IMX6UL_CLK_USDHC2_PODF 102
+#define IMX6UL_CLK_BCH_PODF 103
+#define IMX6UL_CLK_GPMI_PODF 104
+#define IMX6UL_CLK_EIM_SLOW_PODF 105
+#define IMX6UL_CLK_SPDIF_PRED 106
+#define IMX6UL_CLK_SPDIF_PODF 107
+#define IMX6UL_CLK_SAI1_PRED 108
+#define IMX6UL_CLK_SAI1_PODF 109
+#define IMX6UL_CLK_SAI2_PRED 110
+#define IMX6UL_CLK_SAI2_PODF 111
+#define IMX6UL_CLK_SAI3_PRED 112
+#define IMX6UL_CLK_SAI3_PODF 113
+#define IMX6UL_CLK_LCDIF_PRED 114
+#define IMX6UL_CLK_LCDIF_PODF 115
+#define IMX6UL_CLK_SIM_PODF 116
+#define IMX6UL_CLK_QSPI1_PDOF 117
+#define IMX6UL_CLK_ENFC_PRED 118
+#define IMX6UL_CLK_ENFC_PODF 119
+#define IMX6UL_CLK_CAN_PODF 120
+#define IMX6UL_CLK_ECSPI_PODF 121
+#define IMX6UL_CLK_UART_PODF 122
+#define IMX6UL_CLK_ADC1 123
+#define IMX6UL_CLK_ADC2 124
+#define IMX6UL_CLK_AIPSTZ1 125
+#define IMX6UL_CLK_AIPSTZ2 126
+#define IMX6UL_CLK_AIPSTZ3 127
+#define IMX6UL_CLK_APBHDMA 128
+#define IMX6UL_CLK_ASRC_IPG 129
+#define IMX6UL_CLK_ASRC_MEM 130
+#define IMX6UL_CLK_GPMI_BCH_APB 131
+#define IMX6UL_CLK_GPMI_BCH 132
+#define IMX6UL_CLK_GPMI_IO 133
+#define IMX6UL_CLK_GPMI_APB 134
+#define IMX6UL_CLK_CAAM_MEM 135
+#define IMX6UL_CLK_CAAM_ACLK 136
+#define IMX6UL_CLK_CAAM_IPG 137
+#define IMX6UL_CLK_CSI 138
+#define IMX6UL_CLK_ECSPI1 139
+#define IMX6UL_CLK_ECSPI2 140
+#define IMX6UL_CLK_ECSPI3 141
+#define IMX6UL_CLK_ECSPI4 142
+#define IMX6UL_CLK_EIM 143
+#define IMX6UL_CLK_ENET 144
+#define IMX6UL_CLK_ENET_AHB 145
+#define IMX6UL_CLK_EPIT1 146
+#define IMX6UL_CLK_EPIT2 147
+#define IMX6UL_CLK_CAN1_IPG 148
+#define IMX6UL_CLK_CAN1_SERIAL 149
+#define IMX6UL_CLK_CAN2_IPG 150
+#define IMX6UL_CLK_CAN2_SERIAL 151
+#define IMX6UL_CLK_GPT1_BUS 152
+#define IMX6UL_CLK_GPT1_SERIAL 153
+#define IMX6UL_CLK_GPT2_BUS 154
+#define IMX6UL_CLK_GPT2_SERIAL 155
+#define IMX6UL_CLK_I2C1 156
+#define IMX6UL_CLK_I2C2 157
+#define IMX6UL_CLK_I2C3 158
+#define IMX6UL_CLK_I2C4 159
+#define IMX6UL_CLK_IOMUXC 160
+#define IMX6UL_CLK_LCDIF_APB 161
+#define IMX6UL_CLK_LCDIF_PIX 162
+#define IMX6UL_CLK_MMDC_P0_FAST 163
+#define IMX6UL_CLK_MMDC_P0_IPG 164
+#define IMX6UL_CLK_OCOTP 165
+#define IMX6UL_CLK_OCRAM 166
+#define IMX6UL_CLK_PWM1 167
+#define IMX6UL_CLK_PWM2 168
+#define IMX6UL_CLK_PWM3 169
+#define IMX6UL_CLK_PWM4 170
+#define IMX6UL_CLK_PWM5 171
+#define IMX6UL_CLK_PWM6 172
+#define IMX6UL_CLK_PWM7 173
+#define IMX6UL_CLK_PWM8 174
+#define IMX6UL_CLK_PXP 175
+#define IMX6UL_CLK_QSPI 176
+#define IMX6UL_CLK_ROM 177
+#define IMX6UL_CLK_SAI1 178
+#define IMX6UL_CLK_SAI1_IPG 179
+#define IMX6UL_CLK_SAI2 180
+#define IMX6UL_CLK_SAI2_IPG 181
+#define IMX6UL_CLK_SAI3 182
+#define IMX6UL_CLK_SAI3_IPG 183
+#define IMX6UL_CLK_SDMA 184
+#define IMX6UL_CLK_SIM 185
+#define IMX6UL_CLK_SIM_S 186
+#define IMX6UL_CLK_SPBA 187
+#define IMX6UL_CLK_SPDIF 188
+#define IMX6UL_CLK_UART1_IPG 189
+#define IMX6UL_CLK_UART1_SERIAL 190
+#define IMX6UL_CLK_UART2_IPG 191
+#define IMX6UL_CLK_UART2_SERIAL 192
+#define IMX6UL_CLK_UART3_IPG 193
+#define IMX6UL_CLK_UART3_SERIAL 194
+#define IMX6UL_CLK_UART4_IPG 195
+#define IMX6UL_CLK_UART4_SERIAL 196
+#define IMX6UL_CLK_UART5_IPG 197
+#define IMX6UL_CLK_UART5_SERIAL 198
+#define IMX6UL_CLK_UART6_IPG 199
+#define IMX6UL_CLK_UART6_SERIAL 200
+#define IMX6UL_CLK_UART7_IPG 201
+#define IMX6UL_CLK_UART7_SERIAL 202
+#define IMX6UL_CLK_UART8_IPG 203
+#define IMX6UL_CLK_UART8_SERIAL 204
+#define IMX6UL_CLK_USBOH3 205
+#define IMX6UL_CLK_USDHC1 206
+#define IMX6UL_CLK_USDHC2 207
+#define IMX6UL_CLK_WDOG1 208
+#define IMX6UL_CLK_WDOG2 209
+#define IMX6UL_CLK_WDOG3 210
+#define IMX6UL_CLK_LDB_DI0 211
+#define IMX6UL_CLK_AXI 212
+#define IMX6UL_CLK_SPDIF_GCLK 213
+#define IMX6UL_CLK_GPT_3M 214
+#define IMX6UL_CLK_SIM2 215
+#define IMX6UL_CLK_SIM1 216
+#define IMX6UL_CLK_IPP_DI0 217
+#define IMX6UL_CLK_IPP_DI1 218
+#define IMX6UL_CA7_SECONDARY_SEL 219
+#define IMX6UL_CLK_PER_BCH 220
+#define IMX6UL_CLK_CSI_SEL 221
+#define IMX6UL_CLK_CSI_PODF 222
+#define IMX6UL_CLK_PLL3_120M 223
+/* For i.MX6ULL */
+#define IMX6UL_CLK_ESAI_SEL 224
+#define IMX6UL_CLK_ESAI_PRED 225
+#define IMX6UL_CLK_ESAI_PODF 226
+#define IMX6UL_CLK_ESAI_EXTAL 227
+#define IMX6UL_CLK_ESAI_MEM 228
+#define IMX6UL_CLK_ESAI_IPG 229
+#define IMX6UL_CLK_DCP_CLK 230
+#define IMX6UL_CLK_EPDC_PRE_SEL 231
+#define IMX6UL_CLK_EPDC_SEL 232
+#define IMX6UL_CLK_EPDC_PODF 233
+#define IMX6UL_CLK_EPDC_ACLK 234
+#define IMX6UL_CLK_EPDC_PIX 235
+
+#define IMX6UL_CLK_END 236
+
+#endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */
diff --git a/include/fsl_wdog.h b/include/fsl_wdog.h
index f698d4d64e..683c3f3bac 100644
--- a/include/fsl_wdog.h
+++ b/include/fsl_wdog.h
@@ -15,5 +15,6 @@ struct watchdog_regs {
#define WCR_WDE 0x04
#define WCR_WDT 0x08
#define WCR_SRS 0x10
+#define WCR_WDA 0x20
#define SET_WCR_WT(x) (x << 8)
#define WCR_WT_MSK SET_WCR_WT(0xFF)
diff --git a/include/image.h b/include/image.h
index 64da722649..2b1296c86c 100644
--- a/include/image.h
+++ b/include/image.h
@@ -278,6 +278,7 @@ enum {
IH_TYPE_ZYNQIMAGE, /* Xilinx Zynq Boot Image */
IH_TYPE_ZYNQMPIMAGE, /* Xilinx ZynqMP Boot Image */
IH_TYPE_FPGA, /* FPGA Image */
+ IH_TYPE_VYBRIDIMAGE, /* VYBRID .vyb Image */
IH_TYPE_COUNT, /* Number of image types */
};
diff --git a/include/power/rn5t567_pmic.h b/include/power/rn5t567_pmic.h
new file mode 100644
index 0000000000..9ce601f2ad
--- /dev/null
+++ b/include/power/rn5t567_pmic.h
@@ -0,0 +1,113 @@
+/*
+ * Copyright (C) 2016 Toradex AG
+ * Stefan Agner <stefan.agner@toradex.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __RN5T567_PMIC_H_
+#define __RN5T567_PMIC_H_
+
+/* RN5T567 registers */
+enum {
+ RN5T567_LSIVER = 0x00,
+ RN5T567_OTPVER = 0x01,
+ RN5T567_IODAC = 0x02,
+ RN5T567_VINDAC = 0x03,
+ RN5T567_OUT32KEN = 0x05,
+
+ RN5T567_CPUCNT = 0x06,
+
+ RN5T567_PSWR = 0x07,
+ RN5T567_PONHIS = 0x09,
+ RN5T567_POFFHIS = 0x0A,
+ RN5T567_WATCHDOG = 0x0B,
+ RN5T567_WATCHDOGCNT = 0x0C,
+ RN5T567_PWRFUNC = 0x0D,
+ RN5T567_SLPCNT = 0x0E,
+ RN5T567_REPCNT = 0x0F,
+ RN5T567_PWRONTIMSET = 0x10,
+ RN5T567_NOETIMSETCNT = 0x11,
+ RN5T567_PWRIREN = 0x12,
+ RN5T567_PWRIRQ = 0x13,
+ RN5T567_PWRMON = 0x14,
+ RN5T567_PWRIRSEL = 0x15,
+
+ RN5T567_DC1_SLOT = 0x16,
+ RN5T567_DC2_SLOT = 0x17,
+ RN5T567_DC3_SLOT = 0x18,
+ RN5T567_DC4_SLOT = 0x19,
+
+ RN5T567_LDO1_SLOT = 0x1B,
+ RN5T567_LDO2_SLOT = 0x1C,
+ RN5T567_LDO3_SLOT = 0x1D,
+ RN5T567_LDO4_SLOT = 0x1E,
+ RN5T567_LDO5_SLOT = 0x1F,
+
+ RN5T567_PSO0_SLOT = 0x25,
+ RN5T567_PSO1_SLOT = 0x26,
+ RN5T567_PSO2_SLOT = 0x27,
+ RN5T567_PSO3_SLOT = 0x28,
+
+ RN5T567_LDORTC1_SLOT = 0x2A,
+
+ RN5T567_DC1CTL = 0x2C,
+ RN5T567_DC1CTL2 = 0x2D,
+ RN5T567_DC2CTL = 0x2E,
+ RN5T567_DC2CTL2 = 0x2F,
+ RN5T567_DC3CTL = 0x30,
+ RN5T567_DC3CTL2 = 0x31,
+ RN5T567_DC4CTL = 0x32,
+ RN5T567_DC4CTL2 = 0x33,
+
+ RN5T567_DC1DAC = 0x36,
+ RN5T567_DC2DAC = 0x37,
+ RN5T567_DC3DAC = 0x38,
+ RN5T567_DC4DAC = 0x39,
+
+ RN5T567_DC1DAC_SLP = 0x3B,
+ RN5T567_DC2DAC_SLP = 0x3C,
+ RN5T567_DC3DAC_SLP = 0x3D,
+ RN5T567_DC4DAC_SLP = 0x3E,
+
+ RN5T567_DCIREN = 0x40,
+ RN5T567_DCIRQ = 0x41,
+ RN5T567_DCIRMON = 0x42,
+
+ RN5T567_LDOEN1 = 0x44,
+ RN5T567_LDOEN2 = 0x45,
+ RN5T567_LDODIS1 = 0x46,
+
+ RN5T567_LDO1DAC = 0x4C,
+ RN5T567_LDO2DAC = 0x4D,
+ RN5T567_LDO3DAC = 0x4E,
+ RN5T567_LDO4DAC = 0x4F,
+ RN5T567_LDO5DAC = 0x50,
+
+ RN5T567_LDORTC1DAC = 0x56,
+ RN5T567_LDORTC2DAC = 0x57,
+
+ RN5T567_LDO1DAC_SLP = 0x58,
+ RN5T567_LDO2DAC_SLP = 0x59,
+ RN5T567_LDO3DAC_SLP = 0x5A,
+ RN5T567_LDO4DAC_SLP = 0x5B,
+ RN5T567_LDO5DAC_SLP = 0x5C,
+
+ RN5T567_IOSEL = 0x90,
+ RN5T567_IOOUT = 0x91,
+ RN5T567_GPEDGE1 = 0x92,
+ RN5T567_EN_GPIR = 0x94,
+ RN5T567_IR_GPR = 0x95,
+ RN5T567_IR_GPF = 0x96,
+ RN5T567_MON_IOIN = 0x97,
+ RN5T567_GPLED_FUNC = 0x98,
+ RN5T567_INTPOL = 0x9C,
+ RN5T567_INTEN = 0x9D,
+ RN5T567_INTMON = 0x9E,
+
+ RN5T567_PREVINDAC = 0xB0,
+ RN5T567_OVTEMP = 0xBC,
+
+ RN5T567_NUM_OF_REGS = 0xBF,
+};
+
+#endif
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-24 07:52:20 +0000