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-rw-r--r--board/bosch/shc/Kconfig87
-rw-r--r--board/bosch/shc/MAINTAINERS11
-rw-r--r--board/bosch/shc/Makefile10
-rw-r--r--board/bosch/shc/README114
-rw-r--r--board/bosch/shc/board.c648
-rw-r--r--board/bosch/shc/board.h187
-rw-r--r--board/bosch/shc/mux.c261
7 files changed, 1318 insertions, 0 deletions
diff --git a/board/bosch/shc/Kconfig b/board/bosch/shc/Kconfig
new file mode 100644
index 0000000000..c71af11c1c
--- /dev/null
+++ b/board/bosch/shc/Kconfig
@@ -0,0 +1,87 @@
+if TARGET_AM335X_SHC
+
+config SYS_BOARD
+ default "shc"
+
+config SYS_VENDOR
+ default "bosch"
+
+config SYS_SOC
+ default "am33xx"
+
+config SYS_CONFIG_NAME
+ default "am335x_shc"
+
+choice
+ prompt "enable different boot versions for the shc board"
+ default EMMC
+ help
+ Select the boot version of the shc board.
+
+config SHC_EMMC
+ bool "enable eMMC"
+ help
+ enable here the eMMC functionality on the bosch shc board.
+
+config SHC_ICT
+ bool "enable ICT"
+ help
+ enable here the ICT functionality on the bosch shc board
+
+config SHC_NETBOOT
+ bool "enable NETBOOT"
+ help
+ enable here the NETBOOT functionality on the bosch shc board
+
+config SHC_SDBOOT
+ bool "enable SDBOOT"
+ help
+ enable here the SDBOOT functionality on the bosch shc board
+
+endchoice
+
+choice
+ prompt "enable different board versions for the shc board"
+ default C3_SAMPLE
+ help
+ Select the board version of the shc board.
+
+config B_SAMPLE
+ bool "B Sample board version"
+ help
+ activate, if you want to build for the B sample version
+ of the bosch shc board
+
+config B2_SAMPLE
+ bool "B2 Sample board version"
+ help
+ activate, if you want to build for the B2 sample version
+ of the bosch shc board
+
+config C_SAMPLE
+ bool "C Sample board version"
+ help
+ activate, if you want to build for the C sample version
+ of the bosch shc board
+
+config C2_SAMPLE
+ bool "C2 Sample board version"
+ help
+ activate, if you want to build for the C2 sample version
+ of the bosch shc board
+
+config C3_SAMPLE
+ bool "C3 Sample board version"
+ help
+ activate, if you want to build for the C3 sample version
+ of the bosch shc board
+
+config SERIES
+ bool "Series board version"
+ help
+ activate, if you want to build for the Series version
+ of the bosch shc board
+
+endchoice
+
+endif
diff --git a/board/bosch/shc/MAINTAINERS b/board/bosch/shc/MAINTAINERS
new file mode 100644
index 0000000000..ae3c0355c0
--- /dev/null
+++ b/board/bosch/shc/MAINTAINERS
@@ -0,0 +1,11 @@
+SHC BOARD
+M: Heiko Schocher <hs@denx.de>
+S: Maintained
+F: board/bosch/shc
+F: include/configs/am335x_shc.h
+F: configs/am335x_shc_defconfig
+F: configs/am335x_shc_ict_defconfig
+F: configs/am335x_shc_netboot_defconfig
+F: configs/am335x_shc_prompt_defconfig
+F: configs/am335x_shc_sdboot_defconfig
+F: configs/am335x_shc_sdboot_prompt_defconfig
diff --git a/board/bosch/shc/Makefile b/board/bosch/shc/Makefile
new file mode 100644
index 0000000000..4fec2bff29
--- /dev/null
+++ b/board/bosch/shc/Makefile
@@ -0,0 +1,10 @@
+#
+# Makefile
+#
+# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := mux.o
+obj-y += board.o
diff --git a/board/bosch/shc/README b/board/bosch/shc/README
new file mode 100644
index 0000000000..2f206e0d55
--- /dev/null
+++ b/board/bosch/shc/README
@@ -0,0 +1,114 @@
+Summary
+=======
+
+This document covers various features of the 'am335x_shc' build.
+
+Hardware
+========
+
+AM335X based board:
+
+I2C: ready
+DRAM: 512 MiB
+Enabling the D-Cache
+MMC: OMAP SD/MMC: 0 @ 26 MHz, OMAP SD/MMC: 1 @ 26 MHz
+Net: cpsw
+
+Following boot options are possible:
+
+2 Jumpers:
+
+Jumper 1 Jumper 2 Bootmode
+off off eMMC boot
+on off SD boot
+off on Net boot
+
+Compiling
+=========
+
+$ make am335x_shc_defconfig
+ HOSTCC scripts/basic/fixdep
+ HOSTCC scripts/kconfig/conf.o
+ SHIPPED scripts/kconfig/zconf.tab.c
+ SHIPPED scripts/kconfig/zconf.lex.c
+ SHIPPED scripts/kconfig/zconf.hash.c
+ HOSTCC scripts/kconfig/zconf.tab.o
+ HOSTLD scripts/kconfig/conf
+#
+# configuration written to .config
+#
+$ make -s all
+
+-> now you have the MLO and the u-boot.img file, you can put
+on your SD card or eMMC.
+
+Configuring
+===========
+
+There are a lot of board versions and boot configurations, which
+can be selected through "make menuconfig"
+
+ARM architecture --->
+ enable different boot versions for the shc board (enable eMMC) --->
+ (X) enable eMMC
+ ( ) enable ICT
+ ( ) enable NETBOOT
+ ( ) enable SDBOOT
+
+ enable different board versions for the shc board (C3 Sample board version) --->
+ ( ) B Sample board version
+ ( ) B2 Sample board version
+ ( ) C Sample board version
+ ( ) C2 Sample board version
+ (X) C3 Sample board version
+ ( ) Series board version
+
+Netboot
+=======
+- see also doc/SPL/README.am335x-network
+
+- set the jumper into netboot mode
+- compile the U-boot sources with:
+ make am335x_shc_netboot_defconfig
+ make all
+- copy the images into your tftp boot directory
+ cp spl/u-boot-spl.bin /tftpboot/.../u-boot-spl-restore.bin
+ cp u-boot.img /tftpboot/.../u-boot-restore.img
+- power on the board, and you should get something like this:
+
+U-Boot SPL 2016.05-rc2-00016-gf23b960-dirty (Apr 26 2016 - 09:02:18)
+#### NETBOOT ####
+SHC
+MPU reference clock runs at 6 MHz
+Setting MPU clock to 594 MHz
+Enabling Spread Spectrum of 18 permille for MPU
+Trying to boot from net
+Using default environment
+
+<ethaddr> not set. Validating first E-fuse MAC
+cpsw
+cpsw Waiting for PHY auto negotiation to complete... done
+link up on port 0, speed 100, full duplex
+BOOTP broadcast 1
+BOOTP broadcast 2
+DHCP client bound to address 192.168.20.91 (258 ms)
+Using cpsw device
+TFTP from server 192.168.1.1; our IP address is 192.168.20.91
+Filename 'shc/u-boot-restore.img'.
+Load address: 0x807fffc0
+Loading: ##################
+ 1.2 MiB/s
+done
+Bytes transferred = 262480 (40150 hex)
+
+
+U-Boot 2016.05-rc2-00016-gf23b960-dirty (Apr 26 2016 - 09:02:18 +0200)
+
+ Watchdog enabled
+I2C: ready
+DRAM: 512 MiB
+MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
+*** Warning - bad CRC, using default environment
+
+Net: cpsw
+switch to partitions #0, OK
diff --git a/board/bosch/shc/board.c b/board/bosch/shc/board.c
new file mode 100644
index 0000000000..e90693feea
--- /dev/null
+++ b/board/bosch/shc/board.c
@@ -0,0 +1,648 @@
+/*
+ * board.c
+ *
+ * (C) Copyright 2016
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * Board functions for TI AM335X based boards
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
+#include <power/tps65217.h>
+#include <environment.h>
+#include <watchdog.h>
+#include <environment.h>
+#include "mmc.h"
+#include "board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_SPL_BUILD) || \
+ (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_DM_ETH))
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+#endif
+static struct shc_eeprom __attribute__((section(".data"))) header;
+static int shc_eeprom_valid;
+
+/*
+ * Read header information from EEPROM into global structure.
+ */
+static int read_eeprom(void)
+{
+ /* Check if baseboard eeprom is available */
+ if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
+ puts("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n");
+ return -ENODEV;
+ }
+
+ /* read the eeprom using i2c */
+ if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header,
+ sizeof(header))) {
+ puts("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\n");
+ return -EIO;
+ }
+
+ if (header.magic != HDR_MAGIC) {
+ printf("Incorrect magic number (0x%x) in EEPROM\n",
+ header.magic);
+ return -EIO;
+ }
+
+ shc_eeprom_valid = 1;
+
+ return 0;
+}
+
+static void shc_request_gpio(void)
+{
+ gpio_request(LED_PWR_BL_GPIO, "LED PWR BL");
+ gpio_request(LED_PWR_RD_GPIO, "LED PWR RD");
+ gpio_request(RESET_GPIO, "reset");
+ gpio_request(WIFI_REGEN_GPIO, "WIFI REGEN");
+ gpio_request(WIFI_RST_GPIO, "WIFI rst");
+ gpio_request(ZIGBEE_RST_GPIO, "ZigBee rst");
+ gpio_request(BIDCOS_RST_GPIO, "BIDCOS rst");
+ gpio_request(ENOC_RST_GPIO, "ENOC rst");
+#if defined CONFIG_B_SAMPLE
+ gpio_request(LED_PWR_GN_GPIO, "LED PWR GN");
+ gpio_request(LED_CONN_BL_GPIO, "LED CONN BL");
+ gpio_request(LED_CONN_RD_GPIO, "LED CONN RD");
+ gpio_request(LED_CONN_GN_GPIO, "LED CONN GN");
+#else
+ gpio_request(LED_LAN_BL_GPIO, "LED LAN BL");
+ gpio_request(LED_LAN_RD_GPIO, "LED LAN RD");
+ gpio_request(LED_CLOUD_BL_GPIO, "LED CLOUD BL");
+ gpio_request(LED_CLOUD_RD_GPIO, "LED CLOUD RD");
+ gpio_request(LED_PWM_GPIO, "LED PWM");
+ gpio_request(Z_WAVE_RST_GPIO, "Z WAVE rst");
+#endif
+ gpio_request(BACK_BUTTON_GPIO, "Back button");
+ gpio_request(FRONT_BUTTON_GPIO, "Front button");
+}
+
+/*
+ * Function which forces all installed modules into running state for ICT
+ * testing. Called by SPL.
+ */
+static void __maybe_unused force_modules_running(void)
+{
+ /* Wi-Fi power regulator enable - high = enabled */
+ gpio_direction_output(WIFI_REGEN_GPIO, 1);
+ /*
+ * Wait for Wi-Fi power regulator to reach a stable voltage
+ * (soft-start time, max. 350 µs)
+ */
+ __udelay(350);
+
+ /* Wi-Fi module reset - high = running */
+ gpio_direction_output(WIFI_RST_GPIO, 1);
+
+ /* ZigBee reset - high = running */
+ gpio_direction_output(ZIGBEE_RST_GPIO, 1);
+
+ /* BidCos reset - high = running */
+ gpio_direction_output(BIDCOS_RST_GPIO, 1);
+
+#if !defined(CONFIG_B_SAMPLE)
+ /* Z-Wave reset - high = running */
+ gpio_direction_output(Z_WAVE_RST_GPIO, 1);
+#endif
+
+ /* EnOcean reset - low = running */
+ gpio_direction_output(ENOC_RST_GPIO, 0);
+}
+
+/*
+ * Function which forces all installed modules into reset - to be released by
+ * the OS, called by SPL
+ */
+static void __maybe_unused force_modules_reset(void)
+{
+ /* Wi-Fi module reset - low = reset */
+ gpio_direction_output(WIFI_RST_GPIO, 0);
+
+ /* Wi-Fi power regulator enable - low = disabled */
+ gpio_direction_output(WIFI_REGEN_GPIO, 0);
+
+ /* ZigBee reset - low = reset */
+ gpio_direction_output(ZIGBEE_RST_GPIO, 0);
+
+ /* BidCos reset - low = reset */
+ /*gpio_direction_output(BIDCOS_RST_GPIO, 0);*/
+
+#if !defined(CONFIG_B_SAMPLE)
+ /* Z-Wave reset - low = reset */
+ gpio_direction_output(Z_WAVE_RST_GPIO, 0);
+#endif
+
+ /* EnOcean reset - high = reset*/
+ gpio_direction_output(ENOC_RST_GPIO, 1);
+}
+
+/*
+ * Function to set the LEDs in the state "Bootloader booting"
+ */
+static void __maybe_unused leds_set_booting(void)
+{
+#if defined(CONFIG_B_SAMPLE)
+
+ /* Turn all red LEDs on */
+ gpio_direction_output(LED_PWR_RD_GPIO, 1);
+ gpio_direction_output(LED_CONN_RD_GPIO, 1);
+
+#else /* All other SHCs starting with B2-Sample */
+ /* Set the PWM GPIO */
+ gpio_direction_output(LED_PWM_GPIO, 1);
+ /* Turn all red LEDs on */
+ gpio_direction_output(LED_PWR_RD_GPIO, 1);
+ gpio_direction_output(LED_LAN_RD_GPIO, 1);
+ gpio_direction_output(LED_CLOUD_RD_GPIO, 1);
+
+#endif
+}
+
+/*
+ * Function to set the LEDs in the state "Bootloader error"
+ */
+static void leds_set_failure(int state)
+{
+#if defined(CONFIG_B_SAMPLE)
+ /* Turn all blue and green LEDs off */
+ gpio_set_value(LED_PWR_BL_GPIO, 0);
+ gpio_set_value(LED_PWR_GN_GPIO, 0);
+ gpio_set_value(LED_CONN_BL_GPIO, 0);
+ gpio_set_value(LED_CONN_GN_GPIO, 0);
+
+ /* Turn all red LEDs to 'state' */
+ gpio_set_value(LED_PWR_RD_GPIO, state);
+ gpio_set_value(LED_CONN_RD_GPIO, state);
+
+#else /* All other SHCs starting with B2-Sample */
+ /* Set the PWM GPIO */
+ gpio_direction_output(LED_PWM_GPIO, 1);
+
+ /* Turn all blue LEDs off */
+ gpio_set_value(LED_PWR_BL_GPIO, 0);
+ gpio_set_value(LED_LAN_BL_GPIO, 0);
+ gpio_set_value(LED_CLOUD_BL_GPIO, 0);
+
+ /* Turn all red LEDs to 'state' */
+ gpio_set_value(LED_PWR_RD_GPIO, state);
+ gpio_set_value(LED_LAN_RD_GPIO, state);
+ gpio_set_value(LED_CLOUD_RD_GPIO, state);
+#endif
+}
+
+/*
+ * Function to set the LEDs in the state "Bootloader finished"
+ */
+static void leds_set_finish(void)
+{
+#if defined(CONFIG_B_SAMPLE)
+ /* Turn all LEDs off */
+ gpio_set_value(LED_PWR_BL_GPIO, 0);
+ gpio_set_value(LED_PWR_RD_GPIO, 0);
+ gpio_set_value(LED_PWR_GN_GPIO, 0);
+ gpio_set_value(LED_CONN_BL_GPIO, 0);
+ gpio_set_value(LED_CONN_RD_GPIO, 0);
+ gpio_set_value(LED_CONN_GN_GPIO, 0);
+#else /* All other SHCs starting with B2-Sample */
+ /* Turn all LEDs off */
+ gpio_set_value(LED_PWR_BL_GPIO, 0);
+ gpio_set_value(LED_PWR_RD_GPIO, 0);
+ gpio_set_value(LED_LAN_BL_GPIO, 0);
+ gpio_set_value(LED_LAN_RD_GPIO, 0);
+ gpio_set_value(LED_CLOUD_BL_GPIO, 0);
+ gpio_set_value(LED_CLOUD_RD_GPIO, 0);
+
+ /* Turn off the PWM GPIO and mux it to EHRPWM */
+ gpio_set_value(LED_PWM_GPIO, 0);
+ enable_shc_board_pwm_pin_mux();
+#endif
+}
+
+static void check_button_status(void)
+{
+ ulong value;
+ gpio_direction_input(FRONT_BUTTON_GPIO);
+ value = gpio_get_value(FRONT_BUTTON_GPIO);
+
+ if (value == 0) {
+ printf("front button activated !\n");
+ setenv("harakiri", "1");
+ }
+}
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+ return 1;
+}
+#endif
+
+static void shc_board_early_init(void)
+{
+ shc_request_gpio();
+# ifdef CONFIG_SHC_ICT
+ /* Force all modules into enabled state for ICT testing */
+ force_modules_running();
+# else
+ /* Force all modules to enter Reset state until released by the OS */
+ force_modules_reset();
+# endif
+ leds_set_booting();
+}
+
+#define MPU_SPREADING_PERMILLE 18 /* Spread 1.8 percent */
+#define OSC (V_OSCK/1000000)
+/* Bosch: Predivider must be fixed to 4, so N = 4-1 */
+#define MPUPLL_N (4-1)
+/* Bosch: Fref = 24 MHz / (N+1) = 24 MHz / 4 = 6 MHz */
+#define MPUPLL_FREF (OSC / (MPUPLL_N + 1))
+
+const struct dpll_params dpll_ddr_shc = {
+ 400, OSC-1, 1, -1, -1, -1, -1};
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+ return &dpll_ddr_shc;
+}
+
+/*
+ * As we enabled downspread SSC with 1.8%, the values needed to be corrected
+ * such that the 20% overshoot will not lead to too high frequencies.
+ * In all cases, this is achieved by subtracting one from M (6 MHz less).
+ * Example: 600 MHz CPU
+ * Step size: 24 MHz OSC, N = 4 (fix) --> Fref = 6 MHz
+ * 600 MHz - 6 MHz (1x Fref) = 594 MHz
+ * SSC: 594 MHz * 1.8% = 10.7 MHz SSC
+ * Overshoot: 10.7 MHz * 20 % = 2.2 MHz
+ * --> Fmax = 594 MHz + 2.2 MHz = 596.2 MHz, lower than 600 MHz --> OK!
+ */
+const struct dpll_params dpll_mpu_shc_opp100 = {
+ 99, MPUPLL_N, 1, -1, -1, -1, -1};
+
+void am33xx_spl_board_init(void)
+{
+ int sil_rev;
+ int mpu_vdd;
+
+ puts(BOARD_ID_STR);
+
+ /*
+ * Set CORE Frequency to OPP100
+ * Hint: DCDC3 (CORE) defaults to 1.100V (for OPP100)
+ */
+ do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+
+ sil_rev = readl(&cdev->deviceid) >> 28;
+ if (sil_rev < 2) {
+ puts("We do not support Silicon Revisions below 2.0!\n");
+ return;
+ }
+
+ dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
+ if (i2c_probe(TPS65217_CHIP_PM))
+ return;
+
+ /*
+ * Retrieve the CPU max frequency by reading the efuse
+ * SHC-Default: 600 MHz
+ */
+ switch (dpll_mpu_opp100.m) {
+ case MPUPLL_M_1000:
+ mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
+ break;
+ case MPUPLL_M_800:
+ mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
+ break;
+ case MPUPLL_M_720:
+ mpu_vdd = TPS65217_DCDC_VOLT_SEL_1200MV;
+ break;
+ case MPUPLL_M_600:
+ mpu_vdd = TPS65217_DCDC_VOLT_SEL_1100MV;
+ break;
+ case MPUPLL_M_300:
+ mpu_vdd = TPS65217_DCDC_VOLT_SEL_950MV;
+ break;
+ default:
+ puts("Cannot determine the frequency, failing!\n");
+ return;
+ }
+
+ if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
+ puts("tps65217_voltage_update failure\n");
+ return;
+ }
+
+ /* Set MPU Frequency to what we detected */
+ printf("MPU reference clock runs at %d MHz\n", MPUPLL_FREF);
+ printf("Setting MPU clock to %d MHz\n", MPUPLL_FREF *
+ dpll_mpu_shc_opp100.m);
+ do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_shc_opp100);
+
+ /* Enable Spread Spectrum for this freq to be clean on EMI side */
+ set_mpu_spreadspectrum(MPU_SPREADING_PERMILLE);
+
+ /*
+ * Using the default voltages for the PMIC (TPS65217D)
+ * LS1 = 1.8V (VDD_1V8)
+ * LS2 = 3.3V (VDD_3V3A)
+ * LDO1 = 1.8V (VIO and VRTC)
+ * LDO2 = 3.3V (VDD_3V3AUX)
+ */
+ shc_board_early_init();
+}
+
+void set_uart_mux_conf(void)
+{
+ enable_uart0_pin_mux();
+}
+
+void set_mux_conf_regs(void)
+{
+ enable_shc_board_pin_mux();
+}
+
+const struct ctrl_ioregs ioregs_evmsk = {
+ .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+};
+
+static const struct ddr_data ddr3_shc_data = {
+ .datardsratio0 = MT41K256M16HA125E_RD_DQS,
+ .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
+ .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
+ .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
+};
+
+static const struct cmd_control ddr3_shc_cmd_ctrl_data = {
+ .cmd0csratio = MT41K256M16HA125E_RATIO,
+ .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+ .cmd1csratio = MT41K256M16HA125E_RATIO,
+ .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+ .cmd2csratio = MT41K256M16HA125E_RATIO,
+ .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_shc_emif_reg_data = {
+ .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
+ .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
+ .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
+ .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
+ .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
+ .zq_config = MT41K256M16HA125E_ZQ_CFG,
+ .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY |
+ PHY_EN_DYN_PWRDN,
+};
+
+void sdram_init(void)
+{
+ /* Configure the DDR3 RAM */
+ config_ddr(400, &ioregs_evmsk, &ddr3_shc_data,
+ &ddr3_shc_cmd_ctrl_data, &ddr3_shc_emif_reg_data, 0);
+}
+#endif
+
+/*
+ * Basic board specific setup. Pinmux has been handled already.
+ */
+int board_init(void)
+{
+#if defined(CONFIG_HW_WATCHDOG)
+ hw_watchdog_init();
+#endif
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ if (read_eeprom() < 0)
+ puts("EEPROM Content Invalid.\n");
+
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+#if defined(CONFIG_NOR) || defined(CONFIG_NAND)
+ gpmc_init();
+#endif
+ shc_request_gpio();
+
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ check_button_status();
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ if (shc_eeprom_valid)
+ if (is_valid_ethaddr(header.mac_addr))
+ eth_setenv_enetaddr("ethaddr", header.mac_addr);
+#endif
+
+ return 0;
+}
+#endif
+
+#ifndef CONFIG_DM_ETH
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+ (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+static void cpsw_control(int enabled)
+{
+ /* VTP can be added here */
+
+ return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+ {
+ .slave_reg_ofs = 0x208,
+ .sliver_reg_ofs = 0xd80,
+ .phy_addr = 0,
+ },
+ {
+ .slave_reg_ofs = 0x308,
+ .sliver_reg_ofs = 0xdc0,
+ .phy_addr = 1,
+ },
+};
+
+static struct cpsw_platform_data cpsw_data = {
+ .mdio_base = CPSW_MDIO_BASE,
+ .cpsw_base = CPSW_BASE,
+ .mdio_div = 0xff,
+ .channels = 8,
+ .cpdma_reg_ofs = 0x800,
+ .slaves = 1,
+ .slave_data = cpsw_slaves,
+ .ale_reg_ofs = 0xd00,
+ .ale_entries = 1024,
+ .host_port_reg_ofs = 0x108,
+ .hw_stats_reg_ofs = 0x900,
+ .bd_ram_ofs = 0x2000,
+ .mac_control = (1 << 5),
+ .control = cpsw_control,
+ .host_port_num = 0,
+ .version = CPSW_CTRL_VERSION_2,
+};
+#endif
+
+/*
+ * This function will:
+ * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
+ * in the environment
+ * Perform fixups to the PHY present on certain boards. We only need this
+ * function in:
+ * - SPL with either CPSW or USB ethernet support
+ * - Full U-Boot, with either CPSW or USB ethernet
+ * Build in only these cases to avoid warnings about unused variables
+ * when we build an SPL that has neither option but full U-Boot will.
+ */
+#if ((defined(CONFIG_SPL_ETH_SUPPORT) || \
+ defined(CONFIG_SPL_USBETH_SUPPORT)) && \
+ defined(CONFIG_SPL_BUILD)) || \
+ ((defined(CONFIG_DRIVER_TI_CPSW) || \
+ defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) && \
+ !defined(CONFIG_SPL_BUILD))
+int board_eth_init(bd_t *bis)
+{
+ int rv, n = 0;
+ uint8_t mac_addr[6];
+ uint32_t mac_hi, mac_lo;
+
+ /* try reading mac address from efuse */
+ mac_lo = readl(&cdev->macid0l);
+ mac_hi = readl(&cdev->macid0h);
+ mac_addr[0] = mac_hi & 0xFF;
+ mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+ mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+ mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+ mac_addr[4] = mac_lo & 0xFF;
+ mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+ (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+ if (!getenv("ethaddr")) {
+ printf("<ethaddr> not set. Validating first E-fuse MAC\n");
+
+ if (is_valid_ethaddr(mac_addr))
+ eth_setenv_enetaddr("ethaddr", mac_addr);
+ }
+
+ writel(MII_MODE_ENABLE, &cdev->miisel);
+ cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_MII;
+ cpsw_slaves[1].phy_if = cpsw_slaves[0].phy_if;
+ rv = cpsw_register(&cpsw_data);
+ if (rv < 0)
+ printf("Error %d registering CPSW switch\n", rv);
+ else
+ n += rv;
+#endif
+
+#if defined(CONFIG_USB_ETHER) && \
+ (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
+ if (is_valid_ethaddr(mac_addr))
+ eth_setenv_enetaddr("usbnet_devaddr", mac_addr);
+
+ rv = usb_eth_initialize(bis);
+ if (rv < 0)
+ printf("Error %d registering USB_ETHER\n", rv);
+ else
+ n += rv;
+#endif
+ return n;
+}
+#endif
+
+#endif /* CONFIG_DM_ETH */
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+static void bosch_check_reset_pin(void)
+{
+ if (readl(GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0) & RESET_MASK) {
+ printf("Resetting ...\n");
+ writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0);
+ disable_interrupts();
+ reset_cpu(0);
+ /*NOTREACHED*/
+ }
+}
+
+static void hang_bosch(const char *cause, int code)
+{
+ int lv;
+
+ gpio_direction_input(RESET_GPIO);
+
+ /* Enable reset pin interrupt on falling edge */
+ writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0);
+ writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_FALLINGDETECT);
+ enable_interrupts();
+
+ puts(cause);
+ for (;;) {
+ for (lv = 0; lv < code; lv++) {
+ bosch_check_reset_pin();
+ leds_set_failure(1);
+ __udelay(150 * 1000);
+ leds_set_failure(0);
+ __udelay(150 * 1000);
+ }
+#if defined(BLINK_CODE)
+ __udelay(300 * 1000);
+#endif
+ }
+}
+
+void show_boot_progress(int val)
+{
+ switch (val) {
+ case BOOTSTAGE_ID_NEED_RESET:
+ hang_bosch("need reset", 4);
+ break;
+ }
+}
+#endif
+
+void arch_preboot_os(void)
+{
+ leds_set_finish();
+}
+
+#if defined(CONFIG_GENERIC_MMC)
+int board_mmc_init(bd_t *bis)
+{
+ int ret;
+
+ /* Bosch: Do not enable 52MHz for eMMC device to avoid EMI */
+ ret = omap_mmc_init(0, MMC_MODE_HS_52MHz, 26000000, -1, -1);
+ if (ret)
+ return ret;
+
+ ret = omap_mmc_init(1, MMC_MODE_HS_52MHz, 26000000, -1, -1);
+ return ret;
+}
+#endif
diff --git a/board/bosch/shc/board.h b/board/bosch/shc/board.h
new file mode 100644
index 0000000000..46167fe59e
--- /dev/null
+++ b/board/bosch/shc/board.h
@@ -0,0 +1,187 @@
+/*
+ * board.h
+ *
+ * (C) Copyright 2016
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * TI AM335x boards information header
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/* Definition to control the GPIOs (for LEDs and Reset) */
+#define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
+
+static inline int board_is_b_sample(void)
+{
+#if defined CONFIG_B_SAMPLE
+ return 1;
+#else
+ return 0;
+#endif
+}
+
+static inline int board_is_c_sample(void)
+{
+#if defined CONFIG_C_SAMPLE
+ return 1;
+#else
+ return 0;
+#endif
+}
+
+static inline int board_is_c3_sample(void)
+{
+#if defined CONFIG_C3_SAMPLE
+ return 1;
+#else
+ return 0;
+#endif
+}
+
+static inline int board_is_series(void)
+{
+#if defined CONFIG_SERIES
+ return 1;
+#else
+ return 0;
+#endif
+}
+
+/*
+ * Definitions for pinmuxing header and Board ID strings
+ */
+#if defined CONFIG_B_SAMPLE
+# define BOARD_ID_STR "SHC B-Sample\n"
+#elif defined CONFIG_B2_SAMPLE
+# define BOARD_ID_STR "SHC B2-Sample\n"
+#elif defined CONFIG_C_SAMPLE
+# if defined(CONFIG_SHC_NETBOOT)
+# define BOARD_ID_STR "#### NETBOOT ####\nSHC C-Sample\n"
+# elif defined(CONFIG_SHC_SDBOOT)
+# define BOARD_ID_STR "#### SDBOOT ####\nSHC C-Sample\n"
+# else
+# define BOARD_ID_STR "SHC C-Sample\n"
+# endif
+#elif defined CONFIG_C2_SAMPLE
+# if defined(CONFIG_SHC_ICT)
+# define BOARD_ID_STR "#### ICT ####\nSHC C2-Sample\n"
+# elif defined(CONFIG_SHC_NETBOOT)
+# define BOARD_ID_STR "#### NETBOOT ####\nSHC C2-Sample\n"
+# elif defined(CONFIG_SHC_SDBOOT)
+# define BOARD_ID_STR "#### SDBOOT ####\nSHC C2-Sample\n"
+# else
+# define BOARD_ID_STR "SHC C2-Sample\n"
+# endif
+#elif defined CONFIG_C3_SAMPLE
+# if defined(CONFIG_SHC_ICT)
+# define BOARD_ID_STR "#### ICT ####\nSHC C3-Sample\n"
+# elif defined(CONFIG_SHC_NETBOOT)
+# define BOARD_ID_STR "#### NETBOOT ####\nSHC C3-Sample\n"
+# elif defined(CONFIG_SHC_SDBOOT)
+# define BOARD_ID_STR "#### SDBOOT ####\nSHC C3-Sample\n"
+# else
+# define BOARD_ID_STR "SHC C3-Sample\n"
+# endif
+#elif defined CONFIG_SERIES
+# if defined(CONFIG_SHC_ICT)
+# define BOARD_ID_STR "#### ICT ####\nSHC\n"
+# elif defined(CONFIG_SHC_NETBOOT)
+# define BOARD_ID_STR "#### NETBOOT ####\nSHC\n"
+# elif defined(CONFIG_SHC_SDBOOT)
+# define BOARD_ID_STR "#### SDBOOT ####\nSHC\n"
+# else
+# define BOARD_ID_STR "SHC\n"
+# endif
+#else
+# define BOARD_ID_STR "Unknown device!\n"
+#endif
+
+/*
+ * Definitions for GPIO pin assignments
+ */
+#if defined CONFIG_B_SAMPLE
+
+# define LED_PWR_BL_GPIO GPIO_TO_PIN(1, 17)
+# define LED_PWR_RD_GPIO GPIO_TO_PIN(1, 18)
+# define LED_PWR_GN_GPIO GPIO_TO_PIN(1, 19)
+# define LED_CONN_BL_GPIO GPIO_TO_PIN(0, 26)
+# define LED_CONN_RD_GPIO GPIO_TO_PIN(0, 22)
+# define LED_CONN_GN_GPIO GPIO_TO_PIN(0, 23)
+# define RESET_GPIO GPIO_TO_PIN(1, 29)
+# define WIFI_REGEN_GPIO GPIO_TO_PIN(1, 16)
+# define WIFI_RST_GPIO GPIO_TO_PIN(0, 27)
+# define ZIGBEE_RST_GPIO GPIO_TO_PIN(3, 18)
+# define BIDCOS_RST_GPIO GPIO_TO_PIN(0, 12)
+# define ENOC_RST_GPIO GPIO_TO_PIN(1, 22)
+
+#else
+
+# define LED_PWR_BL_GPIO GPIO_TO_PIN(0, 22)
+# define LED_PWR_RD_GPIO GPIO_TO_PIN(0, 23)
+# define LED_LAN_BL_GPIO GPIO_TO_PIN(1, 17)
+# define LED_LAN_RD_GPIO GPIO_TO_PIN(0, 26)
+# define LED_CLOUD_BL_GPIO GPIO_TO_PIN(1, 18)
+# define LED_CLOUD_RD_GPIO GPIO_TO_PIN(2, 2)
+# define LED_PWM_GPIO GPIO_TO_PIN(1, 19)
+# define RESET_GPIO GPIO_TO_PIN(1, 29)
+# define WIFI_REGEN_GPIO GPIO_TO_PIN(1, 16)
+# define WIFI_RST_GPIO GPIO_TO_PIN(0, 27)
+# define ZIGBEE_RST_GPIO GPIO_TO_PIN(3, 18)
+# define BIDCOS_RST_GPIO GPIO_TO_PIN(1, 24)
+# define Z_WAVE_RST_GPIO GPIO_TO_PIN(1, 21)
+# define ENOC_RST_GPIO GPIO_TO_PIN(1, 22)
+
+#endif
+
+#define BACK_BUTTON_GPIO GPIO_TO_PIN(1, 29)
+#define FRONT_BUTTON_GPIO GPIO_TO_PIN(1, 25)
+
+/* Reset is on GPIO pin 29 of GPIO bank 1 */
+#define RESET_MASK (0x1 << 29)
+
+#define HDR_MAGIC 0x43485342
+#define HDR_ETH_ALEN 6
+#define HDR_NAME_LEN 8
+#define HDR_REV_LEN 8
+#define HDR_SER_LEN 16
+#define HDR_ROOT_LEN 12
+#define HDR_FATC_LEN 12
+
+/*
+* SHC parameters held in On-Board I²C EEPROM device.
+*
+* Header Format
+*
+* Name Size Contents
+*-------------------------------------------------------------
+* Magic 4 0x42 0x53 0x48 0x43 [BSHC]
+*
+* Version 2 0x0100 for v1.0
+*
+* Lenght 2 The length of the complete structure, not only this header
+*
+* Eth-MAC 6 Ethernet MAC Address
+* SHC Pool: 7C:AC:B2:00:10:01 - TBD
+*
+* --- Further values follow, not important for Bootloader ---
+*/
+
+struct shc_eeprom {
+ u32 magic;
+ u16 version;
+ u16 lenght;
+ uint8_t mac_addr[HDR_ETH_ALEN];
+};
+
+void enable_uart0_pin_mux(void);
+void enable_shc_board_pin_mux(void);
+void enable_shc_board_pwm_pin_mux(void);
+
+#endif
diff --git a/board/bosch/shc/mux.c b/board/bosch/shc/mux.c
new file mode 100644
index 0000000000..e8ada6540c
--- /dev/null
+++ b/board/bosch/shc/mux.c
@@ -0,0 +1,261 @@
+/*
+ * mux.c
+ *
+ * (C) Copyright 2016
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+#include "board.h"
+
+static struct module_pin_mux uart0_pin_mux[] = {
+ {OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | RXACTIVE)}, /* UART0_RXD */
+ {OFFSET(uart0_txd), (MODE(0) | PULLUDDIS)}, /* UART0_TXD */
+ {OFFSET(uart0_ctsn), (MODE(0) | PULLUDEN | RXACTIVE)}, /* UART0_CTS */
+ {OFFSET(uart0_rtsn), (MODE(0) | PULLUDDIS)}, /* UART0_RTS */
+ {-1},
+};
+
+static struct module_pin_mux uart1_pin_mux[] = {
+ {OFFSET(uart1_rxd), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* UART1_RXD */
+ {OFFSET(uart1_txd), (MODE(0) | PULLUDDIS)}, /* UART1_TXD */
+ {OFFSET(uart1_ctsn), (MODE(0) | PULLUDEN | RXACTIVE)}, /* UART1_CTS */
+ {OFFSET(uart1_rtsn), (MODE(0) | PULLUDDIS)}, /* UART1_RTS */
+ {-1},
+};
+
+static struct module_pin_mux uart2_pin_mux[] = {
+ {OFFSET(spi0_sclk), (MODE(1) | PULLUDDIS | RXACTIVE)}, /* UART2_RXD */
+ {OFFSET(spi0_d0), (MODE(1) | PULLUDDIS)}, /* UART2_TXD */
+ {-1},
+};
+
+static struct module_pin_mux spi1_pin_mux[] = {
+ {OFFSET(mcasp0_aclkx), (MODE(3) | PULLUDEN | RXACTIVE)},/* SPI1_SCLK */
+ {OFFSET(mcasp0_fsx), (MODE(3) | PULLUDEN | RXACTIVE)},/* SPI1_D0 */
+ {OFFSET(mcasp0_axr0), (MODE(3) | PULLUDEN | RXACTIVE)},/* SPI1_D1 */
+ {OFFSET(mcasp0_ahclkr), (MODE(3) | PULLUDEN | RXACTIVE)},/* SPI1_CS0 */
+ {-1},
+};
+
+static struct module_pin_mux uart4_pin_mux[] = {
+ {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */
+ {OFFSET(gpmc_wpn), (MODE(6) | PULLUP_EN)}, /* UART4_TXD */
+ {-1},
+};
+
+static struct module_pin_mux mmc0_pin_mux[] = {
+ {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUDDIS)}, /* MMC0_DAT3 */
+ {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUDDIS)}, /* MMC0_DAT2 */
+ {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUDDIS)}, /* MMC0_DAT1 */
+ {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUDDIS)}, /* MMC0_DAT0 */
+ {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
+ {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUDDIS)}, /* MMC0_CMD */
+ {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUDDIS)}, /* MMC0_CD */
+ {-1},
+};
+
+static struct module_pin_mux mmc1_pin_mux[] = {
+ {OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
+ {OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
+ {OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
+ {OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
+ {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
+ {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
+ {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
+ {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */
+ {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUDDIS)}, /* MMC1_CLK */
+ {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
+ {-1},
+};
+
+static struct module_pin_mux mmc2_pin_mux[] = {
+ {OFFSET(gpmc_ad12), (MODE(3) | PULLUDDIS | RXACTIVE)}, /* MMC2_DAT0 */
+ {OFFSET(gpmc_ad13), (MODE(3) | PULLUDDIS | RXACTIVE)}, /* MMC2_DAT1 */
+ {OFFSET(gpmc_ad14), (MODE(3) | PULLUDDIS | RXACTIVE)}, /* MMC2_DAT2 */
+ {OFFSET(gpmc_ad15), (MODE(3) | PULLUDDIS | RXACTIVE)}, /* MMC2_DAT3 */
+ {OFFSET(gpmc_csn3), (MODE(3) | RXACTIVE | PULLUDDIS)}, /* MMC2_CMD */
+ {OFFSET(gpmc_clk), (MODE(3) | RXACTIVE | PULLUDDIS)}, /* MMC2_CLK */
+ {-1},
+};
+static struct module_pin_mux i2c0_pin_mux[] = {
+ {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDDIS)}, /* I2C_DATA */
+ {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDDIS)}, /* I2C_SCLK */
+ {-1},
+};
+
+static struct module_pin_mux gpio0_7_pin_mux[] = {
+ {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUP_EN)}, /* GPIO0_7 */
+ {-1},
+};
+
+static struct module_pin_mux jtag_pin_mux[] = {
+ {OFFSET(xdma_event_intr0), (MODE(6) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(xdma_event_intr1), (MODE(6) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(nresetin_out), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(nnmi), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(tms), (MODE(0) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(tdi), (MODE(0) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(tdo), (MODE(0) | PULLUP_EN)},
+ {OFFSET(tck), (MODE(0) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(ntrst), (MODE(0) | RXACTIVE)},
+ {OFFSET(emu0), (MODE(0) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(emu1), (MODE(0) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(pmic_power_en), (MODE(0) | PULLUP_EN)},
+ {OFFSET(rsvd2), (MODE(0) | PULLUP_EN)},
+ {OFFSET(rtc_porz), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(ext_wakeup), (MODE(0) | RXACTIVE)},
+ {OFFSET(enz_kaldo_1p8v), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(usb0_drvvbus), (MODE(0) | PULLUDEN)},
+ {OFFSET(usb1_drvvbus), (MODE(0) | PULLUDDIS)},
+ {-1},
+};
+
+static struct module_pin_mux gpio_pin_mux[] = {
+ {OFFSET(gpmc_ad8), (MODE(7) | PULLUDDIS)}, /* gpio0[22] - LED_PWR_BL (external pull-down) */
+ {OFFSET(gpmc_ad9), (MODE(7) | PULLUDDIS)}, /* gpio0[23] - LED_PWR_RD (external pull-down) */
+ {OFFSET(gpmc_ad10), (MODE(7) | PULLUDDIS)}, /* gpio0[26] - LED_LAN_RD (external pull-down) */
+ {OFFSET(gpmc_ad11), (MODE(7) | PULLUDDIS)}, /* gpio0[27] - #WIFI_RST (external pull-down) */
+ {OFFSET(gpmc_a0), (MODE(7) | PULLUDDIS)}, /* gpio1[16] - WIFI_REGEN */
+ {OFFSET(gpmc_a1), (MODE(7) | PULLUDDIS)}, /* gpio1[17] - LED_LAN_BL */
+ {OFFSET(gpmc_a2), (MODE(7) | PULLUDDIS)}, /* gpio1[18] - LED_Cloud_BL */
+ {OFFSET(gpmc_a3), (MODE(7) | PULLUDDIS)}, /* gpio1[19] - LED_PWM as GPIO */
+ {OFFSET(gpmc_a4), (MODE(7))}, /* gpio1[20] - #eMMC_RST */
+ {OFFSET(gpmc_a5), (MODE(7) | PULLUDDIS)}, /* gpio1[21] - #Z-Wave_RST */
+ {OFFSET(gpmc_a6), (MODE(7) | PULLUDDIS)}, /* gpio1[22] - ENOC_RST */
+ {OFFSET(gpmc_a7), (MODE(7) | PULLUP_EN)}, /* gpio1[23] - WIFI_MODE */
+ {OFFSET(gpmc_a8), (MODE(7) | RXACTIVE | PULLUDDIS)}, /* gpio1[24] - #BIDCOS_RST */
+ {OFFSET(gpmc_a9), (MODE(7) | RXACTIVE | PULLUDDIS)}, /* gpio1[25] - USR_BUTTON */
+ {OFFSET(gpmc_a10), (MODE(7) | RXACTIVE | PULLUDDIS)}, /* gpio1[26] - #USB1_OC */
+ {OFFSET(gpmc_a11), (MODE(7) | RXACTIVE | PULLUDDIS)}, /* gpio1[27] - BIDCOS_PROG */
+ {OFFSET(gpmc_be1n), (MODE(7) | PULLUP_EN)}, /* gpio1[28] - ZIGBEE_PC7 */
+ {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUDDIS)}, /* gpio1[29] - RESET_BUTTON */
+ {OFFSET(gpmc_advn_ale), (MODE(7) | PULLUDDIS)}, /* gpio2[2] - LED_Cloud_RD */
+ {OFFSET(gpmc_oen_ren), (MODE(7) | PULLUDDIS | RXACTIVE)}, /* gpio2[3] - #WIFI_POR */
+ {OFFSET(gpmc_wen), (MODE(7) | PULLUDDIS)}, /* gpio2[4] - N/C */
+ {OFFSET(gpmc_be0n_cle), (MODE(7) | PULLUDDIS)}, /* gpio2[5] - EEPROM_WP */
+ {OFFSET(lcd_data0), (MODE(7) | PULLUDDIS)}, /* gpio2[6] */
+ {OFFSET(lcd_data1), (MODE(7) | PULLUDDIS)}, /* gpio2[7] */
+ {OFFSET(lcd_data2), (MODE(7) | PULLUDDIS)}, /* gpio2[8] */
+ {OFFSET(lcd_data3), (MODE(7) | PULLUDDIS)}, /* gpio2[9] */
+ {OFFSET(lcd_data4), (MODE(7) | PULLUDDIS)}, /* gpio2[10] */
+ {OFFSET(lcd_data5), (MODE(7) | PULLUDDIS)}, /* gpio2[11] */
+ {OFFSET(lcd_data6), (MODE(7) | PULLUDDIS)}, /* gpio2[12] */
+ {OFFSET(lcd_data7), (MODE(7) | PULLUDDIS)}, /* gpio2[13] */
+ {OFFSET(lcd_data8), (MODE(7) | PULLUDDIS)}, /* gpio2[14] */
+ {OFFSET(lcd_data9), (MODE(7) | PULLUDDIS)}, /* gpio2[15] */
+ {OFFSET(lcd_data10), (MODE(7) | PULLUDDIS)}, /* gpio2[16] */
+ {OFFSET(lcd_data11), (MODE(7) | PULLUDDIS)}, /* gpio2[17] */
+ {OFFSET(lcd_data12), (MODE(7) | PULLUDDIS)}, /* gpio0[8] */
+ {OFFSET(lcd_data13), (MODE(7) | PULLUDDIS)}, /* gpio0[9] */
+ {OFFSET(lcd_data14), (MODE(7) | PULLUDDIS)}, /* gpio0[10] */
+ {OFFSET(lcd_data15), (MODE(7) | PULLUDDIS)}, /* gpio0[11] */
+ {OFFSET(lcd_vsync), (MODE(7) | PULLUDDIS)}, /* gpio2[22] */
+ {OFFSET(lcd_hsync), (MODE(7) | PULLUDDIS)}, /* gpio2[23] */
+ {OFFSET(lcd_pclk), (MODE(7) | PULLUDDIS)}, /* gpio2[24] */
+ {OFFSET(lcd_ac_bias_en), (MODE(7) | PULLUDDIS)},/* gpio2[25] */
+ {OFFSET(spi0_d1), (MODE(7) | PULLUDDIS)}, /* gpio0[4] */
+ {OFFSET(spi0_cs0), (MODE(7) | PULLUDDIS)}, /* gpio0[5] */
+ {OFFSET(mcasp0_aclkr), (MODE(7) | PULLUDDIS)}, /* gpio3[18] - #ZIGBEE_RST */
+ {OFFSET(mcasp0_fsr), (MODE(7)) | PULLUDDIS}, /* gpio3[19] - ZIGBEE_BOOT */
+ {OFFSET(mcasp0_axr1), (MODE(7) | RXACTIVE)}, /* gpio3[19] - ZIGBEE_BOOT */
+ {OFFSET(mcasp0_ahclkx), (MODE(7) | RXACTIVE | PULLUP_EN)},/* gpio3[21] - ZIGBEE_PC5 */
+ {-1},
+};
+
+static struct module_pin_mux mii1_pin_mux[] = {
+ {OFFSET(mii1_col), MODE(0) | RXACTIVE},
+ {OFFSET(mii1_crs), MODE(0) | RXACTIVE},
+ {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE},
+ {OFFSET(mii1_txen), MODE(0)},
+ {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE},
+ {OFFSET(mii1_txd3), MODE(0)},
+ {OFFSET(mii1_txd2), MODE(0)},
+ {OFFSET(mii1_txd1), MODE(0) | RXACTIVE},
+ {OFFSET(mii1_txd0), MODE(0) | RXACTIVE},
+ {OFFSET(mii1_txclk), MODE(0) | RXACTIVE},
+ {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE},
+ {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE},
+ {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE},
+ {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE},
+ {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE},
+ {OFFSET(rmii1_refclk), MODE(7) | RXACTIVE},
+ {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},
+ {OFFSET(mdio_clk), MODE(0) | PULLUP_EN},
+ {-1},
+};
+
+static struct module_pin_mux pwm_pin_mux[] = {
+ {OFFSET(gpmc_a3), (MODE(6) | PULLUDDIS)},
+ {-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+ configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_uart1_pin_mux(void)
+{
+ configure_module_pin_mux(uart1_pin_mux);
+}
+
+void enable_uart2_pin_mux(void)
+{
+ configure_module_pin_mux(uart2_pin_mux);
+}
+
+void enable_uart3_pin_mux(void)
+{
+}
+
+void enable_uart4_pin_mux(void)
+{
+ configure_module_pin_mux(uart4_pin_mux);
+}
+
+void enable_uart5_pin_mux(void)
+{
+}
+
+void enable_i2c0_pin_mux(void)
+{
+ configure_module_pin_mux(i2c0_pin_mux);
+}
+
+void enable_shc_board_pwm_pin_mux(void)
+{
+ configure_module_pin_mux(pwm_pin_mux);
+}
+
+void enable_shc_board_pin_mux(void)
+{
+ /* Do board-specific muxes. */
+ if (board_is_c3_sample() || board_is_series()) {
+ configure_module_pin_mux(mii1_pin_mux);
+ configure_module_pin_mux(mmc0_pin_mux);
+ configure_module_pin_mux(mmc1_pin_mux);
+ configure_module_pin_mux(mmc2_pin_mux);
+ configure_module_pin_mux(i2c0_pin_mux);
+ configure_module_pin_mux(gpio0_7_pin_mux);
+ configure_module_pin_mux(gpio_pin_mux);
+ configure_module_pin_mux(uart1_pin_mux);
+ configure_module_pin_mux(uart2_pin_mux);
+ configure_module_pin_mux(uart4_pin_mux);
+ configure_module_pin_mux(spi1_pin_mux);
+ configure_module_pin_mux(jtag_pin_mux);
+ } else {
+ puts("Unknown board, cannot configure pinmux.");
+ hang();
+ }
+}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-24 05:03:35 +0000