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-rw-r--r--arch/riscv/Kconfig6
-rw-r--r--arch/riscv/cpu/ax25/Kconfig2
-rw-r--r--arch/riscv/dts/ae350-u-boot.dtsi2
-rw-r--r--arch/riscv/dts/ae350_32.dts6
-rw-r--r--arch/riscv/dts/ae350_64.dts6
-rw-r--r--arch/riscv/dts/microchip-mpfs-icicle-kit.dts91
-rw-r--r--arch/riscv/include/asm/global_data.h4
-rw-r--r--arch/riscv/include/asm/syscon.h2
-rw-r--r--arch/riscv/lib/Makefile2
-rw-r--r--arch/riscv/lib/andes_plicsw.c (renamed from arch/riscv/lib/andes_plic.c)26
10 files changed, 61 insertions, 86 deletions
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 8f9578171d..4d64e9be3f 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -199,7 +199,7 @@ config SIFIVE_CACHE
help
This enables the operations to configure SiFive cache
-config ANDES_PLIC
+config ANDES_PLICSW
bool
depends on RISCV_MMODE || SPL_RISCV_MMODE
select REGMAP
@@ -207,8 +207,8 @@ config ANDES_PLIC
select SPL_REGMAP if SPL
select SPL_SYSCON if SPL
help
- The Andes PLIC block holds memory-mapped claim and pending registers
- associated with software interrupt.
+ The Andes PLICSW block holds memory-mapped claim and pending
+ registers associated with software interrupt.
config SMP
bool "Symmetric Multi-Processing"
diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig
index 941d963ece..4a7295d30c 100644
--- a/arch/riscv/cpu/ax25/Kconfig
+++ b/arch/riscv/cpu/ax25/Kconfig
@@ -4,7 +4,7 @@ config RISCV_NDS
imply CPU
imply CPU_RISCV
imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
- imply ANDES_PLIC if (RISCV_MMODE || SPL_RISCV_MMODE)
+ imply ANDES_PLICSW if (RISCV_MMODE || SPL_RISCV_MMODE)
imply ANDES_PLMT_TIMER if (RISCV_MMODE || SPL_RISCV_MMODE)
imply SPL_CPU
imply SPL_OPENSBI
diff --git a/arch/riscv/dts/ae350-u-boot.dtsi b/arch/riscv/dts/ae350-u-boot.dtsi
index 0d4201cfae..7011f59831 100644
--- a/arch/riscv/dts/ae350-u-boot.dtsi
+++ b/arch/riscv/dts/ae350-u-boot.dtsi
@@ -36,7 +36,7 @@
soc {
u-boot,dm-spl;
- plic1: interrupt-controller@e6400000 {
+ plicsw: interrupt-controller@e6400000 {
u-boot,dm-spl;
};
diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
index 083f676333..96ef8bd8dd 100644
--- a/arch/riscv/dts/ae350_32.dts
+++ b/arch/riscv/dts/ae350_32.dts
@@ -146,8 +146,8 @@
&CPU3_intc 11 &CPU3_intc 9>;
};
- plic1: interrupt-controller@e6400000 {
- compatible = "riscv,plic1";
+ plicsw: interrupt-controller@e6400000 {
+ compatible = "andestech,plicsw";
#interrupt-cells = <1>;
interrupt-controller;
reg = <0xe6400000 0x400000>;
@@ -159,7 +159,7 @@
};
plmt0@e6000000 {
- compatible = "riscv,plmt0";
+ compatible = "andestech,plmt0";
interrupts-extended = <&CPU0_intc 7
&CPU1_intc 7
&CPU2_intc 7
diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts
index 74cff9122d..cddbaec98a 100644
--- a/arch/riscv/dts/ae350_64.dts
+++ b/arch/riscv/dts/ae350_64.dts
@@ -146,8 +146,8 @@
&CPU3_intc 11 &CPU3_intc 9>;
};
- plic1: interrupt-controller@e6400000 {
- compatible = "riscv,plic1";
+ plicsw: interrupt-controller@e6400000 {
+ compatible = "andestech,plicsw";
#interrupt-cells = <2>;
interrupt-controller;
reg = <0x0 0xe6400000 0x0 0x400000>;
@@ -159,7 +159,7 @@
};
plmt0@e6000000 {
- compatible = "riscv,plmt0";
+ compatible = "andestech,plmt0";
interrupts-extended = <&CPU0_intc 7
&CPU1_intc 7
&CPU2_intc 7
diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
index 287ef3d23b..762dcfc694 100644
--- a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
+++ b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * Copyright (C) 2021 Microchip Technology Inc.
+ * Copyright (C) 2021-2022 Microchip Technology Inc.
* Padmarao Begari <padmarao.begari@microchip.com>
*/
@@ -13,11 +13,13 @@
/ {
model = "Microchip PolarFire-SoC Icicle Kit";
- compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs";
+ compatible = "microchip,mpfs-icicle-reference-rtlv2210",
+ "microchip,mpfs-icicle-kit", "microchip,mpfs";
aliases {
serial1 = &uart1;
ethernet0 = &mac1;
+ spi0 = &qspi;
};
chosen {
@@ -28,70 +30,28 @@
timebase-frequency = <RTCCLK_FREQ>;
};
- reserved-memory {
- ranges;
- #size-cells = <2>;
- #address-cells = <2>;
-
- fabricbuf0: fabricbuf@0 {
- compatible = "shared-dma-pool";
- reg = <0x0 0xae000000 0x0 0x2000000>;
- label = "fabricbuf0-ddr-c";
- };
-
- fabricbuf1: fabricbuf@1 {
- compatible = "shared-dma-pool";
- reg = <0x0 0xc0000000 0x0 0x8000000>;
- label = "fabricbuf1-ddr-nc";
- };
-
- fabricbuf2: fabricbuf@2 {
- compatible = "shared-dma-pool";
- reg = <0x0 0xd8000000 0x0 0x8000000>;
- label = "fabricbuf2-ddr-nc-wcb";
- };
- };
-
- udmabuf0 {
- compatible = "ikwzm,u-dma-buf";
- device-name = "udmabuf-ddr-c0";
- minor-number = <0>;
- size = <0x0 0x2000000>;
- memory-region = <&fabricbuf0>;
- sync-mode = <3>;
- };
-
- udmabuf1 {
- compatible = "ikwzm,u-dma-buf";
- device-name = "udmabuf-ddr-nc0";
- minor-number = <1>;
- size = <0x0 0x8000000>;
- memory-region = <&fabricbuf1>;
- sync-mode = <3>;
- };
-
- udmabuf2 {
- compatible = "ikwzm,u-dma-buf";
- device-name = "udmabuf-ddr-nc-wcb0";
- minor-number = <2>;
- size = <0x0 0x8000000>;
- memory-region = <&fabricbuf2>;
- sync-mode = <3>;
- };
-
ddrc_cache_lo: memory@80000000 {
device_type = "memory";
- reg = <0x0 0x80000000 0x0 0x2e000000>;
- clocks = <&clkcfg CLK_DDRC>;
+ reg = <0x0 0x80000000 0x0 0x40000000>;
status = "okay";
};
- ddrc_cache_hi: memory@1000000000 {
+ ddrc_cache_hi: memory@1040000000 {
device_type = "memory";
- reg = <0x10 0x0 0x0 0x40000000>;
- clocks = <&clkcfg CLK_DDRC>;
+ reg = <0x10 0x40000000 0x0 0x40000000>;
status = "okay";
};
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ hss_payload: region@BFC00000 {
+ reg = <0x0 0xBFC00000 0x0 0x400000>;
+ no-map;
+ };
+ };
};
&uart1 {
@@ -155,3 +115,18 @@
ti,fifo-depth = <0x1>;
};
};
+
+&qspi {
+ status = "okay";
+ num-cs = <1>;
+
+ flash0: flash@0 {
+ compatible = "spi-nand";
+ reg = <0x0>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <20000000>;
+ spi-cpol;
+ spi-cpha;
+ };
+};
diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h
index 858594a191..6fdc86dd8b 100644
--- a/arch/riscv/include/asm/global_data.h
+++ b/arch/riscv/include/asm/global_data.h
@@ -21,8 +21,8 @@ struct arch_global_data {
#if CONFIG_IS_ENABLED(SIFIVE_CLINT)
void __iomem *clint; /* clint base address */
#endif
-#ifdef CONFIG_ANDES_PLIC
- void __iomem *plic; /* plic base address */
+#ifdef CONFIG_ANDES_PLICSW
+ void __iomem *plicsw; /* plic base address */
#endif
#if CONFIG_IS_ENABLED(SMP)
struct ipi_data ipi[CONFIG_NR_CPUS];
diff --git a/arch/riscv/include/asm/syscon.h b/arch/riscv/include/asm/syscon.h
index c3629e4b53..f2b37975f3 100644
--- a/arch/riscv/include/asm/syscon.h
+++ b/arch/riscv/include/asm/syscon.h
@@ -13,7 +13,7 @@
enum {
RISCV_NONE,
RISCV_SYSCON_CLINT, /* Core Local Interruptor (CLINT) */
- RISCV_SYSCON_PLIC, /* Platform Level Interrupt Controller (PLIC) */
+ RISCV_SYSCON_PLICSW, /* Andes PLICSW */
};
#endif /* _ASM_SYSCON_H */
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index 06020fcc2a..d6a8ae9728 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -13,7 +13,7 @@ obj-y += cache.o
obj-$(CONFIG_SIFIVE_CACHE) += sifive_cache.o
ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y)
obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint.o
-obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
+obj-$(CONFIG_ANDES_PLICSW) += andes_plicsw.o
else
obj-$(CONFIG_SBI) += sbi.o
obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plicsw.c
index 1eabcacd09..324eb445aa 100644
--- a/arch/riscv/lib/andes_plic.c
+++ b/arch/riscv/lib/andes_plicsw.c
@@ -37,8 +37,8 @@ static int enable_ipi(int hart)
unsigned int en;
en = ENABLE_HART_IPI << hart;
- writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart));
- writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic + 0x4, hart));
+ writel(en, (void __iomem *)ENABLE_REG(gd->arch.plicsw, hart));
+ writel(en, (void __iomem *)ENABLE_REG(gd->arch.plicsw + 0x4, hart));
return 0;
}
@@ -46,14 +46,14 @@ static int enable_ipi(int hart)
int riscv_init_ipi(void)
{
int ret;
- long *base = syscon_get_first_range(RISCV_SYSCON_PLIC);
+ long *base = syscon_get_first_range(RISCV_SYSCON_PLICSW);
ofnode node;
struct udevice *dev;
u32 reg;
if (IS_ERR(base))
return PTR_ERR(base);
- gd->arch.plic = base;
+ gd->arch.plicsw = base;
ret = uclass_find_first_device(UCLASS_CPU, &dev);
if (ret)
@@ -88,7 +88,7 @@ int riscv_send_ipi(int hart)
{
unsigned int ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart));
- writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plic,
+ writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plicsw,
gd->arch.boot_hart));
return 0;
@@ -98,8 +98,8 @@ int riscv_clear_ipi(int hart)
{
u32 source_id;
- source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plic, hart));
- writel(source_id, (void __iomem *)CLAIM_REG(gd->arch.plic, hart));
+ source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plicsw, hart));
+ writel(source_id, (void __iomem *)CLAIM_REG(gd->arch.plicsw, hart));
return 0;
}
@@ -108,21 +108,21 @@ int riscv_get_ipi(int hart, int *pending)
{
unsigned int ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart));
- *pending = readl((void __iomem *)PENDING_REG(gd->arch.plic,
+ *pending = readl((void __iomem *)PENDING_REG(gd->arch.plicsw,
gd->arch.boot_hart));
*pending = !!(*pending & ipi);
return 0;
}
-static const struct udevice_id andes_plic_ids[] = {
- { .compatible = "riscv,plic1", .data = RISCV_SYSCON_PLIC },
+static const struct udevice_id andes_plicsw_ids[] = {
+ { .compatible = "andestech,plicsw", .data = RISCV_SYSCON_PLICSW },
{ }
};
-U_BOOT_DRIVER(andes_plic) = {
- .name = "andes_plic",
+U_BOOT_DRIVER(andes_plicsw) = {
+ .name = "andes_plicsw",
.id = UCLASS_SYSCON,
- .of_match = andes_plic_ids,
+ .of_match = andes_plicsw_ids,
.flags = DM_FLAG_PRE_RELOC,
};
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-24 01:23:15 +0000