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Diffstat (limited to 'arch/microblaze/cpu/cache.c')
-rw-r--r--arch/microblaze/cpu/cache.c86
1 files changed, 67 insertions, 19 deletions
diff --git a/arch/microblaze/cpu/cache.c b/arch/microblaze/cpu/cache.c
index aa832d6be6..829e6c7ae6 100644
--- a/arch/microblaze/cpu/cache.c
+++ b/arch/microblaze/cpu/cache.c
@@ -9,6 +9,61 @@
#include <cpu_func.h>
#include <asm/asm.h>
#include <asm/cache.h>
+#include <asm/cpuinfo.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void __invalidate_icache(ulong addr, ulong size)
+{
+ if (CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USE_WIC)) {
+ for (int i = 0; i < size;
+ i += gd_cpuinfo()->icache_line_length) {
+ asm volatile (
+ "wic %0, r0;"
+ "nop;"
+ :
+ : "r" (addr + i)
+ : "memory");
+ }
+ }
+}
+
+void invalidate_icache_all(void)
+{
+ __invalidate_icache(0, gd_cpuinfo()->icache_size);
+}
+
+static void __flush_dcache(ulong addr, ulong size)
+{
+ if (CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USE_WDC)) {
+ for (int i = 0; i < size;
+ i += gd_cpuinfo()->dcache_line_length) {
+ asm volatile (
+ "wdc.flush %0, r0;"
+ "nop;"
+ :
+ : "r" (addr + i)
+ : "memory");
+ }
+ }
+}
+
+void flush_dcache_range(unsigned long start, unsigned long end)
+{
+ if (start >= end) {
+ debug("Invalid dcache range - start: 0x%08lx end: 0x%08lx\n",
+ start, end);
+ return;
+ }
+
+ __flush_dcache(start, end - start);
+}
+
+void flush_dcache_all(void)
+{
+ __flush_dcache(0, gd_cpuinfo()->dcache_size);
+}
int dcache_status(void)
{
@@ -37,8 +92,8 @@ void icache_enable(void)
void icache_disable(void)
{
- /* we are not generate ICACHE size -> flush whole cache */
- flush_cache(0, 32768);
+ invalidate_icache_all();
+
MSRCLR(0x20);
}
@@ -49,26 +104,19 @@ void dcache_enable(void)
void dcache_disable(void)
{
-#ifdef XILINX_USE_DCACHE
- flush_cache(0, XILINX_DCACHE_BYTE_SIZE);
-#endif
+ flush_dcache_all();
+
MSRCLR(0x80);
}
void flush_cache(ulong addr, ulong size)
{
- int i;
- for (i = 0; i < size; i += 4)
- asm volatile (
-#ifdef CONFIG_ICACHE
- "wic %0, r0;"
-#endif
- "nop;"
-#ifdef CONFIG_DCACHE
- "wdc.flush %0, r0;"
-#endif
- "nop;"
- :
- : "r" (addr + i)
- : "memory");
+ __invalidate_icache(addr, size);
+ __flush_dcache(addr, size);
+}
+
+void flush_cache_all(void)
+{
+ invalidate_icache_all();
+ flush_dcache_all();
}