diff options
| -rw-r--r-- | CHANGELOG | 24 | ||||
| -rw-r--r-- | MAKEALL | 2 | ||||
| -rw-r--r-- | Makefile | 5 | ||||
| -rw-r--r-- | board/altera/common/flash.c | 40 | ||||
| -rw-r--r-- | board/altera/dk1c20/dk1c20.c | 2 | ||||
| -rw-r--r-- | board/altera/dk1s10/dk1s10.c | 10 | ||||
| -rw-r--r-- | board/altera/dk1s10/vectors.S | 21 | ||||
| -rw-r--r-- | cpu/nios/Makefile | 2 | ||||
| -rw-r--r-- | cpu/nios/spi.c | 158 | ||||
| -rw-r--r-- | doc/README.dk1c20 | 12 | ||||
| -rw-r--r-- | doc/README.dk1c20_std32 | 5 | ||||
| -rw-r--r-- | doc/README.dk1s10 | 131 | ||||
| -rw-r--r-- | doc/README.dk1s10_mldk20 | 286 | ||||
| -rw-r--r-- | doc/README.dk1s10_std32 | 5 | ||||
| -rw-r--r-- | doc/README.dk20k200_std32 | 2 | ||||
| -rw-r--r-- | doc/README.nios | 9 | ||||
| -rw-r--r-- | include/configs/DK1C20.h | 280 | ||||
| -rw-r--r-- | include/configs/DK1C20_safe_32.h | 34 | ||||
| -rw-r--r-- | include/configs/DK1C20_standard_32.h | 279 | ||||
| -rw-r--r-- | include/configs/DK1S10.h | 352 | ||||
| -rw-r--r-- | include/configs/DK1S10_mtx_ldk_20.h | 187 | ||||
| -rw-r--r-- | include/configs/DK1S10_safe_32.h | 34 | ||||
| -rw-r--r-- | include/configs/DK1S10_standard_32.h | 274 | ||||
| -rw-r--r-- | include/nios-io.h | 2 | ||||
| -rw-r--r-- | lib_nios/board.c | 2 | ||||
| -rw-r--r-- | rtc/ds1306.c | 515 |
26 files changed, 1925 insertions, 748 deletions
@@ -2,6 +2,30 @@ Changes since U-Boot 1.0.1: ====================================================================== +* Patches by Stephan Linz, 30 Jan 2004: + 1: - board/altera/common/flash.c:flash_erase(): + o allow interrupts befor get_timer() call + o check-up each erased sector and avoid unexpected timeouts + - board/altera/dk1c20/dk1s10.c:board_early_init_f(): + o enclose sevenseg_set() in cpp condition + - remove the ASMI configuration for DK1S10_standard_32 (never present) + - fix some typed in mistakes in the NIOS documentation + 2: - split DK1C20 configuration into several header files: + o two new files for each NIOS CPU description + o U-Boot related part is remaining in DK1C20.h + 3: - split DK1S10 configuration into several header files: + o two new files for each NIOS CPU description + o U-Boot related part is remaining in DK1S10.h + 4: - Add support for the Microtronix Linux Development Kit + NIOS CPU configuration at the Altera Nios Development Kit, + Stratix Edition (DK-1S10) + 5: - Add documentation for the Altera Nios Development Kit, + Stratix Edition (DK-1S10) + 6: - Add support for the Nios Serial Peripharel Interface (SPI) + (master only) + 7: - Add support for the common U-Boot SPI framework at + RTC driver DS1306 + * Patch by Rahul Shanbhag, 28 Jan 2004: Fix flash protection/locking handling for OMAP1610 innovator board. @@ -177,7 +177,7 @@ LIST_x86="${LIST_I486}" LIST_nios=" \ DK1C20 DK1C20_standard_32 \ - DK1S10 DK1S10_standard_32 \ + DK1S10 DK1S10_standard_32 DK1S10_mtx_ldk_20 \ " #----------------------------------------------------------------------- @@ -1064,6 +1064,7 @@ DK1C20_config: unconfig DK1S10_safe_32_config \ DK1S10_standard_32_config \ +DK1S10_mtx_ldk_20_config \ DK1S10_config: unconfig @ >include/config.h @[ -z "$(findstring _safe_32,$@)" ] || \ @@ -1074,6 +1075,10 @@ DK1S10_config: unconfig { echo "#define CONFIG_NIOS_STANDARD_32 1" >>include/config.h ; \ echo "... NIOS 'standard_32' configuration" ; \ } + @[ -z "$(findstring _mtx_ldk_20,$@)" ] || \ + { echo "#define CONFIG_NIOS_MTX_LDK_20 1" >>include/config.h ; \ + echo "... NIOS 'mtx_ldk_20' configuration" ; \ + } @[ -z "$(findstring DK1S10_config,$@)" ] || \ { echo "#define CONFIG_NIOS_STANDARD_32 1" >>include/config.h ; \ echo "... NIOS 'standard_32' configuration (DEFAULT)" ; \ diff --git a/board/altera/common/flash.c b/board/altera/common/flash.c index 0fa74abfd4..2638ea899a 100644 --- a/board/altera/common/flash.c +++ b/board/altera/common/flash.c @@ -71,7 +71,6 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]); volatile CFG_FLASH_WORD_SIZE *addr2; int prot, sect; - int any = 0; unsigned oldpri; ulong start; @@ -94,6 +93,12 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) printf ("\n"); } +#ifdef DEBUG + for (sect = s_first; sect <= s_last; sect++) { + printf("- Erase: Sect: %i @ 0x%08x\n", sect, info->start[sect]); + } +#endif + /* NOTE: disabling interrupts on Nios can be very bad since it * also disables the LO_LIMIT exception. It's better here to * set the interrupt priority to 3 & restore it when we're done. @@ -114,27 +119,26 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) *addr = 0xaa; *addr = 0x55; *addr2 = 0x30; - any = 1; - } - } - - /* Now just wait for 0xff & provide some user feedback while - * we wait. - */ - if (any) { - addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]); - start = get_timer (0); - while (*addr2 != 0xff) { - udelay (1000 * 1000); - putc ('.'); - if (get_timer (start) > CFG_FLASH_ERASE_TOUT) { - printf ("timeout\n"); - return 1; + /* Now just wait for 0xff & provide some user + * feedback while we wait. Here we have to grant + * timer interrupts. Otherwise get_timer() can't + * work right. */ + ipri(oldpri); + start = get_timer (0); + while (*addr2 != 0xff) { + udelay (1000 * 1000); + putc ('.'); + if (get_timer (start) > CFG_FLASH_ERASE_TOUT) { + printf ("timeout\n"); + return 1; + } } + oldpri = ipri (3); /* disallow non important irqs again */ } - printf ("\n"); } + printf ("\n"); + /* Restore interrupt priority */ ipri (oldpri); diff --git a/board/altera/dk1c20/dk1c20.c b/board/altera/dk1c20/dk1c20.c index 3954486791..fd85706825 100644 --- a/board/altera/dk1c20/dk1c20.c +++ b/board/altera/dk1c20/dk1c20.c @@ -33,8 +33,10 @@ void _default_hdlr (void) int board_early_init_f (void) { +#if defined(CONFIG_SEVENSEG) /* init seven segment led display and switch off */ sevenseg_set(SEVENSEG_OFF); +#endif return 0; } diff --git a/board/altera/dk1s10/dk1s10.c b/board/altera/dk1s10/dk1s10.c index 832a0b9dd8..c45e7f15d7 100644 --- a/board/altera/dk1s10/dk1s10.c +++ b/board/altera/dk1s10/dk1s10.c @@ -33,14 +33,24 @@ void _default_hdlr (void) int board_early_init_f (void) { +#if defined(CONFIG_SEVENSEG) /* init seven segment led display and switch off */ sevenseg_set(SEVENSEG_OFF); +#endif return 0; } int checkboard (void) { puts ("Board: Altera Nios 1S10 Development Kit\n"); +#if defined(CONFIG_NIOS_SAFE_32) + puts ("Conf.: Altera Safe 32 (safe_32)\n"); +#elif defined(CONFIG_NIOS_STANDARD_32) + puts ("Conf.: Altera Standard 32 (standard_32)\n"); +#elif defined(CONFIG_NIOS_MTX_LDK_20) + puts ("Conf.: Microtronix LDK 2.0 (LDK2)\n"); +#endif + return 0; } diff --git a/board/altera/dk1s10/vectors.S b/board/altera/dk1s10/vectors.S index 7094eb63ea..2f44875dcc 100644 --- a/board/altera/dk1s10/vectors.S +++ b/board/altera/dk1s10/vectors.S @@ -1,6 +1,7 @@ /* * (C) Copyright 2003, Psyent Corporation <www.psyent.com> * Scott McNutt <smcnutt@psyent.com> + * Stephan Linz <linz@li-pro.net> * * See file CREDITS for list of people who contributed to this * project. @@ -21,6 +22,8 @@ * MA 02111-1307 USA */ +#include <config.h> + /************************************************************************* * Exception Vector Table @@ -55,8 +58,14 @@ .align 4 _vectors: - .long _def_xhandler@h /* Vector 0 - NMI */ - .long _cwp_lolimit@h /* Vector 1 - underflow */ +#if defined(CFG_NIOS_CPU_OCI_BASE) + /* OCI does the reset job */ + .long _def_xhandler@h /* Vector 0 - NMI / Reset */ +#else + /* there is no OCI, so we have to do a direct reset jump here */ + .long CFG_NIOS_CPU_RST_VECT /* Vector 0 - Reset to GERMS */ +#endif + .long _cwp_lolimit@h /* Vector 1 - underflow */ .long _cwp_hilimit@h /* Vector 2 - overflow */ .long _def_xhandler@h /* Vector 3 - GNUPro debug */ @@ -72,7 +81,11 @@ _vectors: .long _def_xhandler@h /* Vector 13 - future reserved */ .long _def_xhandler@h /* Vector 14 - future reserved */ .long _def_xhandler@h /* Vector 15 - future reserved */ +#if (CFG_NIOS_TMRIRQ == 16) + .long _timebase_int@h /* Vector 16 - lopri timer*/ +#else .long _def_xhandler@h /* Vector 16 */ +#endif .long _def_xhandler@h /* Vector 17 */ .long _def_xhandler@h /* Vector 18 */ .long _def_xhandler@h /* Vector 19 */ @@ -106,7 +119,11 @@ _vectors: .long _def_xhandler@h /* Vector 47 */ .long _def_xhandler@h /* Vector 48 */ .long _def_xhandler@h /* Vector 49 */ +#if (CFG_NIOS_TMRIRQ == 50) .long _timebase_int@h /* Vector 50 - lopri timer*/ +#else + .long _def_xhandler@h /* Vector 50 */ +#endif .long _def_xhandler@h /* Vector 51 */ .long _def_xhandler@h /* Vector 52 */ .long _def_xhandler@h /* Vector 53 */ diff --git a/cpu/nios/Makefile b/cpu/nios/Makefile index a9adbc593c..78553256a0 100644 --- a/cpu/nios/Makefile +++ b/cpu/nios/Makefile @@ -27,7 +27,7 @@ LIB = lib$(CPU).a START = start.o AOBJS = traps.o -OBJS = cpu.o interrupts.o serial.o asmi.o +OBJS = cpu.o interrupts.o serial.o asmi.o spi.o all: .depend $(START) $(LIB) diff --git a/cpu/nios/spi.c b/cpu/nios/spi.c new file mode 100644 index 0000000000..f37146b793 --- /dev/null +++ b/cpu/nios/spi.c @@ -0,0 +1,158 @@ +/* + * (C) Copyright 2004, Li-Pro.Net <www.li-pro.net> + * Stephan Linz <linz@li-pro.net> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <linux/ctype.h> + +#if defined(CONFIG_NIOS_SPI) +#include <nios-io.h> +#include <spi.h> + +#if !defined(CFG_NIOS_SPIBASE) +#error "*** CFG_NIOS_SPIBASE not defined ***" +#endif + +#if !defined(CFG_NIOS_SPIBITS) +#error "*** CFG_NIOS_SPIBITS not defined ***" +#endif + +#if (CFG_NIOS_SPIBITS != 8) && (CFG_NIOS_SPIBITS != 16) +#error "*** CFG_NIOS_SPIBITS should be either 8 or 16 ***" +#endif + +static nios_spi_t *spi = (nios_spi_t *)CFG_NIOS_SPIBASE; + +/* Warning: + * You cannot enable DEBUG for early system initalization, i. e. when + * this driver is used to read environment parameters like "baudrate" + * from EEPROM which are used to initialize the serial port which is + * needed to print the debug messages... + */ +#undef DEBUG + +#ifdef DEBUG + +#define DPRINT(a) printf a; +/* ----------------------------------------------- + * Helper functions to peek into tx and rx buffers + * ----------------------------------------------- */ +static const char * const hex_digit = "0123456789ABCDEF"; + +static char quickhex (int i) +{ + return hex_digit[i]; +} + +static void memdump (void *pv, int num) +{ + int i; + unsigned char *pc = (unsigned char *) pv; + + for (i = 0; i < num; i++) + printf ("%c%c ", quickhex (pc[i] >> 4), quickhex (pc[i] & 0x0f)); + printf ("\t"); + for (i = 0; i < num; i++) + printf ("%c", isprint (pc[i]) ? pc[i] : '.'); + printf ("\n"); +} +#else /* !DEBUG */ + +#define DPRINT(a) +#define memdump(p,n) + +#endif /* DEBUG */ + + +/* + * SPI transfer: + * + * See include/spi.h and http://www.altera.com/literature/ds/ds_nios_spi.pdf + * for more informations. + */ +int spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar *dout, uchar *din) +{ + int j; + + DPRINT(("spi_xfer: chipsel %08X dout %08X din %08X bitlen %d\n", + (int)chipsel, *(uint *)dout, *(uint *)din, bitlen)); + + memdump((void*)dout, (bitlen + 7) / 8); + + if(chipsel != NULL) { + chipsel(1); /* select the target chip */ + } + + if (bitlen > CFG_NIOS_SPIBITS) { /* leave chip select active */ + spi->control |= NIOS_SPI_SSO; + } + + for ( j = 0; /* count each byte in */ + j < ((bitlen + 7) / 8); /* dout[] and din[] */ + +#if (CFG_NIOS_SPIBITS == 8) + j++) { + + while ((spi->status & NIOS_SPI_TRDY) == 0) + ; + spi->txdata = (unsigned)(dout[j]); + + while ((spi->status & NIOS_SPI_RRDY) == 0) + ; + din[j] = (unsigned char)(spi->rxdata & 0xff); + +#elif (CFG_NIOS_SPIBITS == 16) + j++, j++) { + + while ((spi->status & NIOS_SPI_TRDY) == 0) + ; + if ((j+1) < ((bitlen + 7) / 8)) + spi->txdata = (unsigned)((dout[j] << 8) | dout[j+1]); + else + spi->txdata = (unsigned)(dout[j] << 8); + + while ((spi->status & NIOS_SPI_RRDY) == 0) + ; + din[j] = (unsigned char)((spi->rxdata >> 8) & 0xff); + if ((j+1) < ((bitlen + 7) / 8)) + din[j+1] = (unsigned char)(spi->rxdata & 0xff); + +#else +#error "*** unsupported value of CFG_NIOS_SPIBITS ***" +#endif + + } + + if (bitlen > CFG_NIOS_SPIBITS) { + spi->control &= ~NIOS_SPI_SSO; + } + + if(chipsel != NULL) { + chipsel(0); /* deselect the target chip */ + } + + memdump((void*)din, (bitlen + 7) / 8); + + return 0; +} + +#endif /* CONFIG_NIOS_SPI */ diff --git a/doc/README.dk1c20 b/doc/README.dk1c20 index bf3b6995e1..3c0e41bf7d 100644 --- a/doc/README.dk1c20 +++ b/doc/README.dk1c20 @@ -24,7 +24,7 @@ Contents: 1. Files ========= - board/dk1c20/* + board/altera/dk1c20/* include/configs/DK1C20.h 2. Memory Organization @@ -73,11 +73,7 @@ see the following: 2. Quit nios-run and start your terminal application (e.g. start Hyperterminal or minicom). -3. From the U-Boot command prompt, erase flash 0x40000 to 0x 5ffff: - - ==> erase 1:4-5 - -4. Download the u-boot code to RAM. When using Hyperterminal, do the +3. Download the u-boot code to RAM. When using Hyperterminal, do the following: a. From the u-boot command prompt start a binary download to SRAM: @@ -86,6 +82,10 @@ following: b. Download u-boot.bin using kermit. +4. From the U-Boot command prompt, erase flash 0x40000 to 0x5ffff: + + ==> erase 1:4-5 + 5. Copy the binary image from SRAM to flash: ==> cp.b 800000 40000 10000 diff --git a/doc/README.dk1c20_std32 b/doc/README.dk1c20_std32 index 4822c6fa70..521fab75fd 100644 --- a/doc/README.dk1c20_std32 +++ b/doc/README.dk1c20_std32 @@ -91,10 +91,10 @@ IDE: (TODO) 0x02000000 ---32-----------16|15------------0- | : | \ | : | | - SDRAM | : | > CFG_NIOS_CPU_SRAM_SIZE + SDRAM | : | > CFG_NIOS_CPU_SDRAM_SIZE | : | | = 0x01000000 | : | / - 0x01000000 ---32-----------16|15------------0- CFG_NIOS_CPU_SRAM_BASE + 0x01000000 ---32-----------16|15------------0- CFG_NIOS_CPU_SDRAM_BASE | | : gap : : : @@ -345,6 +345,7 @@ IDE: (TODO) | : | | 0x00040000 --+- - - - - - - -:- - - - - - - -+-|- u-boot _start() | : | / + 0x00000000 |- - - - - - - -:- - - - - - - -+- - u-boot environment 0x00000000 ---8-------------4|3-------------0- diff --git a/doc/README.dk1s10 b/doc/README.dk1s10 new file mode 100644 index 0000000000..bb8375a6b8 --- /dev/null +++ b/doc/README.dk1s10 @@ -0,0 +1,131 @@ + + Nios Development Kit + Startix Editions + + Last Update: January 28, 2004 +==================================================================== + +This file contains information regarding U-Boot and the Altera +Nios Development Kit, Startix Edition (DK-1S10). For general Nios +information see doc/README.nios. + +Most stuff of this file was borrowed and based on README.dk1c20, +the DK-1C20 related information file. + +For those interested in contributing ... see HELP WANTED section +in doc/README.nios. + +Contents: + + 1. Files + 2. Memory Organization + 3. CPU Variations + 4. Examples + 5. Programming U-Boot into FLASH with GERMS + +==================================================================== + +1. Files +========= + board/altera/dk1s10/* + include/configs/DK1S10.h + +2. Memory Organization +======================= + + -The heap is placed below the monitor (U-Boot code). + -Global data is placed below the heap. + -The stack is placed below global data (&grows down). + +3. CPU Variations +================= + +There are more than one NIOS CPU variation for the DK-1S10. U-Boot +supports the following CPU configurations: + + - Altera Standard 32 (make DK1S10_standard_32_config) + - Microtronix LDK 2.0 (make DK1S10_mtx_ldk_20_config) + +4. Examples +============ + +The hello_world example was never tested on DK-1S10. Neverthelse +it should work as far as possible, because the DK-1S10 port is +more than ninetieth percents equal to the DK-1C20 port and at +this platform the hello_world example was already tested +successfully (see README.dk1c20). + + +5. Programming U-Boot into FLASH with GERMS +============================================ +The current version of the DK-1S10 port with the default +configuration settings occupies about 78 KBytes of flash. +A minimal configuration occupies less than 60 KByte +(network support disabled). + +To program U-Boot into the DK-1S10 flash using GERMS do the +following: + +1. From the command line, download U-Boot using the nios-run: + + $ nios-run -r u-boot.srec + +This takes about 45 seconds (GERMS is not very speedy here). +After u-boot is downloaded it will be executed. You should +see the following: + + U-Boot 1.0.2 (Jan 28 2004 - 19:02:30) + + CPU: Nios-32 Rev. 3.3 (0x3038) + Reg file size: 256 LO_LIMIT/HI_LIMIT: 2/14 + Board: Altera Nios 1S10 Development Kit + In: serial + Out: serial + Err: serial + DK1S10 > + + +2. Quit nios-run and start your terminal application (e.g. start + Hyperterminal or minicom). + +3. Download the u-boot code to RAM. When using Hyperterminal, do the + following: + + a. From the u-boot command prompt start a binary download to + SRAM / SDRAM: + + at the Altera Standard 32 to SRAM: + + ==> loadb 800000 + + at the Microtronix LDK 2.0 to SDRAM: + + ==> loadb 1010000 + + b. Download u-boot.bin using kermit. + +4. From the U-Boot command prompt, erase flash: + + at the Altera Standard 32 from 0x40000 to 0x5ffff: + + ==> erase 1:4-5 + + at the Microtronix LDK 2.0 from 0x8000000 to 0x81ffff: + + ==> erase 1:0-1 + +5. Copy the binary image from SRAM / SDRAM to flash: + + at the Altera Standard 32 to SRAM: + + ==> cp.b 800000 40000 $(filesize) + + at the Microtronix LDK 2.0 to SDRAM: + + ==> cp.b 1010000 8000000 $(filesize) + +U-Boot will now automatically start when the board is powered on or +reset using the Standard-32 configuration. To start U-Boot with the +Safe-32 configuration, enter the following GERMS command: + + + g 40000 diff --git a/doc/README.dk1s10_mldk20 b/doc/README.dk1s10_mldk20 new file mode 100644 index 0000000000..fcf8170d66 --- /dev/null +++ b/doc/README.dk1s10_mldk20 @@ -0,0 +1,286 @@ + +TODO: specify IDE i/f + + +=============================================================================== + C P U , M E M O R Y , I N / O U T C O M P O N E N T S +=============================================================================== +see also [1]-[5] + +CPU: "LDK2" + 32 bit NIOS for 75 MHz + 512 Byte for register file (30 levels) + with out instruction cache + with out data cache + 2 KByte On Chip ROM with GERMS boot monitor + with out On Chip RAM + MSTEP multiplier + no Debug Core + no On Chip Instrumentation (OCI) + + U-Boot CFG: CFG_NIOS_CPU_CLK = 75000000 + CFG_NIOS_CPU_ICACHE = (not present) + CFG_NIOS_CPU_DCACHE = (not present) + CFG_NIOS_CPU_REG_NUMS = 512 + CFG_NIOS_CPU_MUL = 0 + CFG_NIOS_CPU_MSTEP = 1 + CFG_NIOS_CPU_DBG_CORE = 0 + +IRQ: Nr. | used by + ------+-------------------------------------------------------- + 16 | TIMER0 | CFG_NIOS_CPU_TIMER0_IRQ = 16 + 17 | UART0 | CFG_NIOS_CPU_UART0_IRQ = 17 + 18 | UART1 | CFG_NIOS_CPU_UART1_IRQ = 18 + 20 | LAN91C111 | CFG_NIOS_CPU_LAN0_IRQ = 20 + 25 | IDE0 | CFG_NIOS_CPU_IDE0_IRQ = 25 + +MEMORY: 8 MByte Flash + 16 MByte SDRAM + +Timer: TIMER0: high priority programmable timer (IRQ16) + + U-Boot CFG: CFG_NIOS_CPU_TICK_TIMER = 0 + CFG_NIOS_CPU_USER_TIMER = (not present) + +PIO: Nr. | description + ------+-------------------------------------------------------- + PIO0 | CFPOWER: 1 output to controll CF power supply + PIO1 | BUTTON: 4 inputs for user push buttons (no IRQ) + ------+-------------------------------------------------------- + not | LCD: 11 in/outputs for ASCII LCD + pres.| LED: 8 outputs for user LEDs + | SEVENSEG: 16 outputs for user seven segment display + | RECONF: 1 in/output for . . . . . . . . . . . . + | CFPRESENT: 1 input for CF present event (IRQ35) + | CFATASEL: 1 output to controll CF ATA card select + + U-Boot CFG: CFG_NIOS_CPU_BUTTON_PIO = 1 + CFG_NIOS_CPU_LCD_PIO = (not present) + CFG_NIOS_CPU_LED_PIO = (not present) + CFG_NIOS_CPU_SEVENSEG_PIO = (not present) + CFG_NIOS_CPU_RECONF_PIO = (not present) + CFG_NIOS_CPU_CFPRESENT_PIO = (not present) + CFG_NIOS_CPU_CFPOWER_PIO = 0 + CFG_NIOS_CPU_CFATASEL_PIO = (not present) + +UART: UART0: fixed baudrate of 115200, fixed protocol 8N2, + without handshake RTS/CTS (IRQ17) + UART1: fixed baudrate of 115200, fixed protocol 8N1, + without handshake RTS/CTS (IRQ18) + +LAN: SMsC LAN91C111 with: + - offset 0x300 (LAN91C111_REGISTERS_OFFSET) + - data bus width 32 bit (LAN91C111_DATA_BUS_WIDTH) + +IDE: (TODO) + + +=============================================================================== + M E M O R Y M A P +=============================================================================== + +- - - - - - - - - - - external memory - - - - - - - - - - - - - - - - - - - + + 0x02000000 ---32-----------16|15------------0- CFG_NIOS_CPU_STACK + 0x02000000 --+32-----------16|15------------0+ + | . | \ \ + | . | | | + | . | | > stack area + | . | | | + | . | | V + | . | | + | . | | + SDRAM | . | > CFG_NIOS_CPU_SDRAM_SIZE + | . | | = 0x01000000 + | . | | + 0x01000100 |- - - - - - - - - - - - - - - -+-|- + | . | | \ + | . | | | + | . | | > CFG_NIOS_CPU_VEC_SIZE + | . | | | = 0x00000100 + | | / / + 0x01000000 |- - - - - - - - - - - - - - - -+- - CFG_NIOS_CPU_VEC_BASE + 0x01000000 ---32-----------16|15------------0- CFG_NIOS_CPU_SDRAM_BASE + | sector 127 | \ + + 0x7f0000 |- - - - - - - - - - - - - - - -| | + | : | | + Flash |- - - - : - - - -| > CFG_NIOS_CPU_FLASH_SIZE + | sector 1 : | | = 0x00800000 + + 0x010000 |- - - - - - - - - - - - - - - -| | + | sector 0 (size = 0x10000) | / + 0x00800000 ---8-------------4|3-------------0- CFG_NIOS_CPU_FLASH_BASE + | | + : gap : + : : + +- - - - - - - - - - - external i/o - - - - - - - - - - - - - - - - - - - + + : : + : gap : + | | + 0x00020000 ---32-----------16|15------------0- + | gap | \ + 0x00010310 --+-------------------------------| | + | | | + | register bank (size = 0x10) | | + | +--------.---.---.--- | | + | | bank 0 \ 1 \ 2 \ 3 \ | | + | |---------------------------+ | | + LAN91C111 | | BANK | RESERVED | | | + | |- - - - - - -|- - - - - - -| | > na_enet_size + | | RPCR | MIR | | | = 0x00010000 + | |- - - - - - -|- - - - - - -| | | + | | COUNTER | RCR | | | + | |- - - - - - -|- - - - - - -| | | + | | EPH STATUS | TCR | | | + | +---------------------------+ | | + 0x00010300 --+--LAN91C111_REGISTERS_OFFSET---| | + | gap | / + 0x00010000 ---32-----------16|15------------0- CFG_NIOS_CPU_LAN0_BASE + | | + : gap : + : : + +- - - - - - - - - - - on chip i/o - - - - - - - - - - - - - - - - - - - + + : : + : gap : + | | + 0x00000980 ---32-----------16|15------------0- + | | | \ + : (real size : : | + IDE i/f : and content : : > 0x00000080 + [5] : unknown) : : | + | | | / + 0x00000900 ---32-----------16|15------------0- CFG_NIOS_CPU_IDE0 + | | \ + : gap : > (space for PIO4..7) + | | / + 0x000008c0 ---32-----------16|15------------0- + | (unused) | \ + + 0x1c |- - - - - - - - - - - - - - - -| | + | (unused) | | + + 0x18 |- - - - - - - - - - - - - - - -| | + | (unused) | | + + 0x14 |- - - - - - - - - - - - - - - -| | + UART1 | (unused) | > 0x00000020 + [2] + 0x10 |- - - - - - - - - - - - - - - -| | + | control (10 bit) (rw) | | + + 0x0c |- - - - - - - - - - - - - - - -| | + | status (10 bit) (rw) | | + + 0x08 |- - - - - - - - - - - - - - - -| | + | txdata (8 bit) (wo) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | rxdata (8 bit) (ro) | / + 0x000008a0 ---32-----------16|15------------0- CFG_NIOS_CPU_UART1 + | | \ + : gap : > (space for PIO2..3) + | | / + 0x00000880 ---32-----------16|15------------0- + | edgecapture (4 bit) (rw) | \ + + 0x0c |- - - - - - - - - - - - - - - -| | + PIO1 | interruptmask (4 bit) (rw) | | + [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010 + | (unused) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | data (4 bit) (ro) | / + 0x00000870 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO1 + | (unused) | \ + + 0x0c |- - - - - - - - - - - - - - - -| | + PIO0 | (unused) | | + [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010 + | (unused) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | data (1 bit) (wo) | / + 0x00000860 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO0 + | (unused) | \ + + 0x1c |- - - - - - - - - - - - - - - -| | + | (unused) | | + + 0x18 |- - - - - - - - - - - - - - - -| | + | snaph (16 bit) (rw) | | + + 0x14 |- - - - - - - - - - - - - - - -| | + TIMER0 | snapl (16 bit) (rw) | | + [3] + 0x10 |- - - - - - - - - - - - - - - -| > 0x00000020 + | periodh (16 bit) (rw) | | + + 0x0c |- - - - - - - - - - - - - - - -| | + | periodl (16 bit) (rw) | | + + 0x08 |- - - - - - - - - - - - - - - -| | + | control (4 bit) (rw) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | status (2 bit) (rw) | / + 0x00000840 ---32-----------16|15------------0- CFG_NIOS_CPU_TIMER0 + | | \ + : gap : > (space for UART2) + | | / + 0x00000820 ---32-----------16|15------------0- + | (unused) | \ + + 0x1c |- - - - - - - - - - - - - - - -| | + | (unused) | | + + 0x18 |- - - - - - - - - - - - - - - -| | + | (unused) | | + + 0x14 |- - - - - - - - - - - - - - - -| | + UART0 | (unused) | > 0x00000020 + [2] + 0x10 |- - - - - - - - - - - - - - - -| | + | control (10 bit) (rw) | | + + 0x0c |- - - - - - - - - - - - - - - -| | + | status (10 bit) (rw) | | + + 0x08 |- - - - - - - - - - - - - - - -| | + | txdata (8 bit) (wo) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | rxdata (8 bit) (ro) | / + 0x00000800 ---32-----------16|15------------0- CFG_NIOS_CPU_UART0 + +- - - - - - - - - - - on chip memory 1 - - - - - - - - - - - + + 0x00000800 ---32-----------16|15------------0- + | : | \ + | : | | + GERMS | : | > CFG_NIOS_CPU_ROM_SIZE + | : | | = 0x00000800 + | : | / + 0x00000000 |- - - - - - - - - - - - - - - -+- - CFG_NIOS_CPU_RST_VECT + 0x00000000 ---32-----------16|15------------0- CFG_NIOS_CPU_ROM_BASE + +=============================================================================== + F L A S H M E M O R Y A L L O C A T I O N +=============================================================================== + + 0x01000000 ---8-------------4|3-------------0- + | : | \ + SAFE | : | > 1 MByte + FPGA conf. | : | / (NOT usable by software) + 0x00f00000 --+- - - - - - - -:- - - - - - - -+- + | : | \ + USER | : | > 1 MByte + FPGA conf. | : | / (NOT usable by software) + 0x00e00000 --+- - - - - - - -:- - - - - - - -+- + | : | \ + | : | | + WEB pages | : | > 2 MByte + | : | | (provisory usable) + | : | / + 0x00c00000 --+- - - - - - - -:- - - - - - - -+- + | : | \ + | : | | + | : | | + | : | > 4 MByte free for use + | : | | + 0x00840000 --+- - - - - - - -:- - - - - - - -+-|- u-boot environment + | : | / + 0x00800000 |- - - - - - - -:- - - - - - - -+- - u-boot _start() + 0x00800000 ---8-------------4|3-------------0- + + +=============================================================================== + R E F E R E N C E S +=============================================================================== +[1] http://www.altera.com/literature/manual/mnl_nios_board_stratix_1s10.pdf +[2] http://www.altera.com/literature/ds/ds_nios_uart.pdf +[3] http://www.altera.com/literature/ds/ds_nios_timer.pdf +[4] http://www.altera.com/literature/ds/ds_nios_pio.pdf +[5] http://www.opencores.org/projects/ata/ + http://www.t13.org/index.html + + +=============================================================================== +Stephan Linz <linz@li-pro.net> diff --git a/doc/README.dk1s10_std32 b/doc/README.dk1s10_std32 index 33ae15e6dd..d649eb3793 100644 --- a/doc/README.dk1s10_std32 +++ b/doc/README.dk1s10_std32 @@ -87,10 +87,10 @@ IDE: (TODO) 0x02000000 ---32-----------16|15------------0- | : | \ | : | | - SDRAM | : | > CFG_NIOS_CPU_SRAM_SIZE + SDRAM | : | > CFG_NIOS_CPU_SDRAM_SIZE | : | | = 0x01000000 | : | / - 0x01000000 ---32-----------16|15------------0- CFG_NIOS_CPU_SRAM_BASE + 0x01000000 ---32-----------16|15------------0- CFG_NIOS_CPU_SDRAM_BASE | | : gap : : : @@ -335,6 +335,7 @@ IDE: (TODO) | : | | 0x00040000 --+- - - - - - - -:- - - - - - - -+-|- u-boot _start() | : | / + 0x00000000 |- - - - - - - -:- - - - - - - -+- - u-boot environment 0x00000000 ---8-------------4|3-------------0- diff --git a/doc/README.dk20k200_std32 b/doc/README.dk20k200_std32 index 2c2b1d6b41..7b5d4d4810 100644 --- a/doc/README.dk20k200_std32 +++ b/doc/README.dk20k200_std32 @@ -117,7 +117,7 @@ UART: UART0: fixed baudrate of 115200, fixed protocol 8N2, + 0x18 |- - - - - - - - - - - - - - - -| | | (unused) | | + 0x14 |- - - - - - - - - - - - - - - -| | - UART0 | (unused) | > 0x00000020 + UART1 | (unused) | > 0x00000020 [2] + 0x10 |- - - - - - - - - - - - - - - -| | | control (10 bit) (rw) | | + 0x0c |- - - - - - - - - - - - - - - -| | diff --git a/doc/README.nios b/doc/README.nios index af21b3e427..08f4e7ef98 100644 --- a/doc/README.nios +++ b/doc/README.nios @@ -1,7 +1,7 @@ U-Boot for Nios-32 - Last Update: January 2, 2004 + Last Update: February 1, 2004 ==================================================================== This file contains information regarding U-Boot and the Altera @@ -103,6 +103,13 @@ CFG_NIOS_TMRMS -- the period of the timer in milliseconds. CFG_NIOS_ASMIBASE -- the base address of the ASMI peripheral. (standard-32: na_asmi_base). +CFG_NIOS_SPIBASE -- the base address of the SPI master (!) peripheral. + (nasys_spi_0) + +CFG_NIOS_SPIBITS -- the amount of configured SPI data bits in PTF. + This value can be 8 or 16 only! (PTF: databits) + + 2.2 Differences in U-Boot Options/Settings ------------------------------------------- Some 'standard' U-Boot options/settings are treated differently in diff --git a/include/configs/DK1C20.h b/include/configs/DK1C20.h index f3570512e2..2d77dd7938 100644 --- a/include/configs/DK1C20.h +++ b/include/configs/DK1C20.h @@ -25,264 +25,17 @@ #ifndef __CONFIG_H #define __CONFIG_H -/* - * NIOS CPU configuration. +/*********************************************************************** + * Include the whole NIOS CPU configuration. * - * Here we must define CPU dependencies. Any unsupported option have to - * be defined with zero, example CPU without data cache / OCI: + * !!! HAVE TO BE HERE !!! DON'T MOVE THIS PART !!! * - * #define CFG_NIOS_CPU_ICACHE 4096 - * #define CFG_NIOS_CPU_DCACHE 0 - * #define CFG_NIOS_CPU_OCI_BASE 0 - * #define CFG_NIOS_CPU_OCI_SIZE 0 - */ + ***********************************************************************/ #if defined(CONFIG_NIOS_SAFE_32) - -/* TODO */ - +#include <configs/DK1C20_safe_32.h> #elif defined(CONFIG_NIOS_STANDARD_32) - -/* CPU core */ -#define CFG_NIOS_CPU_CLK 50000000 /* NIOS CPU clock */ -#define CFG_NIOS_CPU_ICACHE (4 * 1024) /* instruction cache */ -#define CFG_NIOS_CPU_DCACHE (4 * 1024) /* data cache */ -#define CFG_NIOS_CPU_REG_NUMS 256 /* number of register */ -#define CFG_NIOS_CPU_MUL 0 /* 16x16 MUL: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_MSTEP 1 /* 16x16 MSTEP: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_STACK 0x008fff00 /* stack top addr */ -#define CFG_NIOS_CPU_VEC_BASE 0x008fff00 /* IRQ vectors addr */ -#define CFG_NIOS_CPU_VEC_SIZE 256 /* size */ -#define CFG_NIOS_CPU_VEC_NUMS 64 /* numbers */ -#define CFG_NIOS_CPU_RST_VECT 0x00920000 /* RESET vector addr */ -#define CFG_NIOS_CPU_DBG_CORE 0 /* CPU debug: no(0) */ - /* yes(1) */ - -/* on-chip extensions */ -#define CFG_NIOS_CPU_RAM_BASE 0 /* on chip RAM addr */ -#define CFG_NIOS_CPU_RAM_SIZE 0 /* size */ - -#define CFG_NIOS_CPU_ROM_BASE 0x00920000 /* on chip ROM addr */ -#define CFG_NIOS_CPU_ROM_SIZE (2 * 1024) /* 2 KB size */ - -#define CFG_NIOS_CPU_OCI_BASE 0x00920800 /* OCI core addr */ -#define CFG_NIOS_CPU_OCI_SIZE 256 /* size */ - -/* timer */ -#define CFG_NIOS_CPU_TIMER_NUMS 2 /* number of timer */ - -#define CFG_NIOS_CPU_TIMER0 0x00920940 /* TIMER0 addr */ -#define CFG_NIOS_CPU_TIMER0_IRQ 16 /* IRQ */ -#define CFG_NIOS_CPU_TIMER0_PER 1000 /* periode usec */ -#define CFG_NIOS_CPU_TIMER0_AR 0 /* always run: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_TIMER0_FP 0 /* fixed per: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_TIMER0_SS 1 /* snaphot: no(0) */ - /* yes(1) */ - -#define CFG_NIOS_CPU_TIMER1 0x009209e0 /* TIMER1 addr */ -#define CFG_NIOS_CPU_TIMER1_IRQ 50 /* IRQ */ -#define CFG_NIOS_CPU_TIMER1_PER 10000 /* periode usec */ -#define CFG_NIOS_CPU_TIMER1_AR 1 /* always run: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_TIMER1_FP 1 /* fixed per: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_TIMER1_SS 0 /* snaphot: no(0) */ - /* yes(1) */ - -/* serial i/o */ -#define CFG_NIOS_CPU_UART_NUMS 1 /* number of uarts */ - -#define CFG_NIOS_CPU_UART0 0x00920900 /* UART0 addr */ -#define CFG_NIOS_CPU_UART0_IRQ 25 /* IRQ */ -#define CFG_NIOS_CPU_UART0_BR 115200 /* baudrate var(0) */ -#define CFG_NIOS_CPU_UART0_DB 8 /* data bit */ -#define CFG_NIOS_CPU_UART0_SB 1 /* stop bit */ -#define CFG_NIOS_CPU_UART0_PA 0 /* parity none(0) */ - /* odd(1) */ - /* even(2) */ -#define CFG_NIOS_CPU_UART0_HS 0 /* handshake: no(0) */ - /* crts(1) */ -#define CFG_NIOS_CPU_UART0_EOP 0 /* eop reg: no(0) */ - /* yes(1) */ - -/* parallel i/o */ -#define CFG_NIOS_CPU_PIO_NUMS 8 /* number of parports */ - -#define CFG_NIOS_CPU_PIO0 0x00920960 /* PIO0 addr */ -#define CFG_NIOS_CPU_PIO0_IRQ 40 /* IRQ */ -#define CFG_NIOS_CPU_PIO0_BITS 4 /* number of bits */ -#define CFG_NIOS_CPU_PIO0_TYPE 2 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO0_CAP 1 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO0_EDGE 3 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO0_ITYPE 2 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CFG_NIOS_CPU_PIO1 0x00920970 /* PIO1 addr */ -#undef CFG_NIOS_CPU_PIO1_IRQ /* w/o IRQ */ -#define CFG_NIOS_CPU_PIO1_BITS 11 /* number of bits */ -#define CFG_NIOS_CPU_PIO1_TYPE 0 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO1_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO1_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO1_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CFG_NIOS_CPU_PIO2 0x00920980 /* PIO2 addr */ -#undef CFG_NIOS_CPU_PIO2_IRQ /* w/o IRQ */ -#define CFG_NIOS_CPU_PIO2_BITS 8 /* number of bits */ -#define CFG_NIOS_CPU_PIO2_TYPE 1 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO2_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO2_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO2_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CFG_NIOS_CPU_PIO3 0x00920990 /* PIO3 addr */ -#undef CFG_NIOS_CPU_PIO3_IRQ /* w/o IRQ */ -#define CFG_NIOS_CPU_PIO3_BITS 16 /* number of bits */ -#define CFG_NIOS_CPU_PIO3_TYPE 1 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO3_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO3_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO3_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CFG_NIOS_CPU_PIO4 0x009209a0 /* PIO4 addr */ -#undef CFG_NIOS_CPU_PIO4_IRQ /* w/o IRQ */ -#define CFG_NIOS_CPU_PIO4_BITS 1 /* number of bits */ -#define CFG_NIOS_CPU_PIO4_TYPE 0 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO4_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO4_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO4_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CFG_NIOS_CPU_PIO5 0x009209b0 /* PIO5 addr */ -#define CFG_NIOS_CPU_PIO5_IRQ 35 /* IRQ */ -#define CFG_NIOS_CPU_PIO5_BITS 1 /* number of bits */ -#define CFG_NIOS_CPU_PIO5_TYPE 2 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO5_CAP 1 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO5_EDGE 3 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO5_ITYPE 2 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CFG_NIOS_CPU_PIO6 0x009209c0 /* PIO6 addr */ -#undef CFG_NIOS_CPU_PIO6_IRQ /* w/o IRQ */ -#define CFG_NIOS_CPU_PIO6_BITS 1 /* number of bits */ -#define CFG_NIOS_CPU_PIO6_TYPE 1 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO6_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO6_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO6_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CFG_NIOS_CPU_PIO7 0x009209d0 /* PIO7 addr */ -#undef CFG_NIOS_CPU_PIO7_IRQ /* w/o IRQ */ -#define CFG_NIOS_CPU_PIO7_BITS 1 /* number of bits */ -#define CFG_NIOS_CPU_PIO7_TYPE 1 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO7_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO7_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO7_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -/* IDE i/f */ -#define CFG_NIOS_CPU_IDE_NUMS 1 /* number of IDE contr. */ -#define CFG_NIOS_CPU_IDE0 0x00920a00 /* IDE0 addr */ - -/* active serial memory i/f */ -#define CFG_NIOS_CPU_ASMI_NUMS 1 /* number of ASMI */ -#define CFG_NIOS_CPU_ASMI0 0x00920b00 /* ASMI0 addr */ -#define CFG_NIOS_CPU_ASMI0_IRQ 45 /* IRQ */ - -/* memory accessibility */ -#define CFG_NIOS_CPU_SRAM_BASE 0x00800000 /* board SRAM addr */ -#define CFG_NIOS_CPU_SRAM_SIZE (1024 * 1024) /* 1 MB size */ - -#define CFG_NIOS_CPU_SDRAM_BASE 0x01000000 /* board SDRAM addr */ -#define CFG_NIOS_CPU_SDRAM_SIZE (16*1024*1024) /* 16 MB size */ - -#define CFG_NIOS_CPU_FLASH_BASE 0x00000000 /* board Flash addr */ -#define CFG_NIOS_CPU_FLASH_SIZE (8*1024*1024) /* 8 MB size */ - -/* LAN */ -#define CFG_NIOS_CPU_LAN_NUMS 1 /* number of LAN i/f */ - -#define CFG_NIOS_CPU_LAN0_BASE 0x00910000 /* LAN0 addr */ -#define CFG_NIOS_CPU_LAN0_OFFS 0x0300 /* offset */ -#define CFG_NIOS_CPU_LAN0_IRQ 30 /* IRQ */ -#define CFG_NIOS_CPU_LAN0_BUSW 32 /* buswidth*/ -#define CFG_NIOS_CPU_LAN0_TYPE 0 /* smc91111(0) */ - /* cs8900(1) */ - /* ex: alteramac(2) */ - -/* symbolic redefinition (undef, if not present) */ -#define CFG_NIOS_CPU_USER_TIMER 0 /* TIMER0: users choice */ -#define CFG_NIOS_CPU_TICK_TIMER 1 /* TIMER1: tick (needed)*/ - -#define CFG_NIOS_CPU_BUTTON_PIO 0 /* PIO0: buttons */ -#define CFG_NIOS_CPU_LCD_PIO 1 /* PIO1: ASCII LCD */ -#define CFG_NIOS_CPU_LED_PIO 2 /* PIO2: LED bar */ -#define CFG_NIOS_CPU_SEVENSEG_PIO 3 /* PIO3: 7-seg. display */ -#define CFG_NIOS_CPU_RECONF_PIO 4 /* PIO4: reconf pin */ -#define CFG_NIOS_CPU_CFPRESENT_PIO 5 /* PIO5: CF present IRQ */ -#define CFG_NIOS_CPU_CFPOWER_PIO 6 /* PIO6: CF power/sw. */ -#define CFG_NIOS_CPU_CFATASEL_PIO 7 /* PIO7: CF ATA select */ - +#include <configs/DK1C20_standard_32.h> #else #error *** CFG_ERROR: you have to setup right NIOS CPU configuration #endif @@ -419,9 +172,6 @@ #if (CFG_NIOS_CPU_LAN0_TYPE == 0) /* LAN91C111 */ - /****************************************************/ - /* !!! LAN91C111 works for NIOS with patch only !!! */ - /****************************************************/ #define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */ #undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */ #define CONFIG_SMC91111_BASE (CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS) @@ -558,15 +308,15 @@ #if (CFG_NIOS_CPU_SEVENSEG_PIO == 0) -#error *** CFG_ERROR: status LEDs at PIO0 not supported, expand your config.h +#error *** CFG_ERROR: seven segment display at PIO0 not supported, expand your config.h #elif (CFG_NIOS_CPU_SEVENSEG_PIO == 1) -#error *** CFG_ERROR: status LEDs at PIO1 not supported, expand your config.h +#error *** CFG_ERROR: seven segment display at PIO1 not supported, expand your config.h #elif (CFG_NIOS_CPU_SEVENSEG_PIO == 2) -#error *** CFG_ERROR: status LEDs at PIO2 not supported, expand your config.h +#error *** CFG_ERROR: seven segment display at PIO2 not supported, expand your config.h #elif (CFG_NIOS_CPU_SEVENSEG_PIO == 3) @@ -582,27 +332,27 @@ #elif (CFG_NIOS_CPU_SEVENSEG_PIO == 4) -#error *** CFG_ERROR: status LEDs at PIO4 not supported, expand your config.h +#error *** CFG_ERROR: seven segment display at PIO4 not supported, expand your config.h #elif (CFG_NIOS_CPU_SEVENSEG_PIO == 5) -#error *** CFG_ERROR: status LEDs at PIO5 not supported, expand your config.h +#error *** CFG_ERROR: seven segment display at PIO5 not supported, expand your config.h #elif (CFG_NIOS_CPU_SEVENSEG_PIO == 6) -#error *** CFG_ERROR: status LEDs at PIO6 not supported, expand your config.h +#error *** CFG_ERROR: seven segment display at PIO6 not supported, expand your config.h #elif (CFG_NIOS_CPU_SEVENSEG_PIO == 7) -#error *** CFG_ERROR: status LEDs at PIO7 not supported, expand your config.h +#error *** CFG_ERROR: seven segment display at PIO7 not supported, expand your config.h #elif (CFG_NIOS_CPU_SEVENSEG_PIO == 8) -#error *** CFG_ERROR: status LEDs at PIO8 not supported, expand your config.h +#error *** CFG_ERROR: seven segment display at PIO8 not supported, expand your config.h #elif (CFG_NIOS_CPU_SEVENSEG_PIO == 9) -#error *** CFG_ERROR: status LEDs at PIO9 not supported, expand your config.h +#error *** CFG_ERROR: seven segment display at PIO9 not supported, expand your config.h #else #error *** CFG_ERROR: you have to set CFG_NIOS_CPU_SEVENSEG_PIO in right case diff --git a/include/configs/DK1C20_safe_32.h b/include/configs/DK1C20_safe_32.h new file mode 100644 index 0000000000..a483e87664 --- /dev/null +++ b/include/configs/DK1C20_safe_32.h @@ -0,0 +1,34 @@ +/* + * (C) Copyright 2003, Li-Pro.Net <www.li-pro.net> + * Stephan Linz <linz@li-pro.net> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_DK1C20_SAFE_32_H +#define __CONFIG_DK1C20_SAFE_32_H + +/* + * NIOS CPU configuration. (PART OF configs/DK1C20.h) + * + * !!! TODO !!! TODO !!! + */ +#error *** CFG_ERROR: DK1C20_safe_32 have to be defined (use DK1C20_standard_32 as template) + +#endif /* __CONFIG_DK1C20_SAFE_32_H */ diff --git a/include/configs/DK1C20_standard_32.h b/include/configs/DK1C20_standard_32.h new file mode 100644 index 0000000000..ed08121cc2 --- /dev/null +++ b/include/configs/DK1C20_standard_32.h @@ -0,0 +1,279 @@ +/* + * (C) Copyright 2003, Li-Pro.Net <www.li-pro.net> + * Stephan Linz <linz@li-pro.net> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_DK1C20_STANDARD_32_H +#define __CONFIG_DK1C20_STANDARD_32_H + +/* + * NIOS CPU configuration. (PART OF configs/DK1C20.h) + * + * Here we must define CPU dependencies. Any unsupported option have to + * be defined with zero, example CPU without data cache / OCI: + * + * #define CFG_NIOS_CPU_ICACHE 4096 + * #define CFG_NIOS_CPU_DCACHE 0 + * #define CFG_NIOS_CPU_OCI_BASE 0 + * #define CFG_NIOS_CPU_OCI_SIZE 0 + */ + +/* CPU core */ +#define CFG_NIOS_CPU_CLK 50000000 /* NIOS CPU clock */ +#define CFG_NIOS_CPU_ICACHE (4 * 1024) /* instruction cache */ +#define CFG_NIOS_CPU_DCACHE (4 * 1024) /* data cache */ +#define CFG_NIOS_CPU_REG_NUMS 256 /* number of register */ +#define CFG_NIOS_CPU_MUL 0 /* 16x16 MUL: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_MSTEP 1 /* 16x16 MSTEP: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_STACK 0x008fff00 /* stack top addr */ +#define CFG_NIOS_CPU_VEC_BASE 0x008fff00 /* IRQ vectors addr */ +#define CFG_NIOS_CPU_VEC_SIZE 256 /* size */ +#define CFG_NIOS_CPU_VEC_NUMS 64 /* numbers */ +#define CFG_NIOS_CPU_RST_VECT 0x00920000 /* RESET vector addr */ +#define CFG_NIOS_CPU_DBG_CORE 0 /* CPU debug: no(0) */ + /* yes(1) */ + +/* on-chip extensions */ +#define CFG_NIOS_CPU_RAM_BASE 0 /* on chip RAM addr */ +#define CFG_NIOS_CPU_RAM_SIZE 0 /* size */ + +#define CFG_NIOS_CPU_ROM_BASE 0x00920000 /* on chip ROM addr */ +#define CFG_NIOS_CPU_ROM_SIZE (2 * 1024) /* 2 KB size */ + +#define CFG_NIOS_CPU_OCI_BASE 0x00920800 /* OCI core addr */ +#define CFG_NIOS_CPU_OCI_SIZE 256 /* size */ + +/* timer */ +#define CFG_NIOS_CPU_TIMER_NUMS 2 /* number of timer */ + +#define CFG_NIOS_CPU_TIMER0 0x00920940 /* TIMER0 addr */ +#define CFG_NIOS_CPU_TIMER0_IRQ 16 /* IRQ */ +#define CFG_NIOS_CPU_TIMER0_PER 1000 /* periode usec */ +#define CFG_NIOS_CPU_TIMER0_AR 0 /* always run: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_TIMER0_FP 0 /* fixed per: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_TIMER0_SS 1 /* snaphot: no(0) */ + /* yes(1) */ + +#define CFG_NIOS_CPU_TIMER1 0x009209e0 /* TIMER1 addr */ +#define CFG_NIOS_CPU_TIMER1_IRQ 50 /* IRQ */ +#define CFG_NIOS_CPU_TIMER1_PER 10000 /* periode usec */ +#define CFG_NIOS_CPU_TIMER1_AR 1 /* always run: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_TIMER1_FP 1 /* fixed per: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_TIMER1_SS 0 /* snaphot: no(0) */ + /* yes(1) */ + +/* serial i/o */ +#define CFG_NIOS_CPU_UART_NUMS 1 /* number of uarts */ + +#define CFG_NIOS_CPU_UART0 0x00920900 /* UART0 addr */ +#define CFG_NIOS_CPU_UART0_IRQ 25 /* IRQ */ +#define CFG_NIOS_CPU_UART0_BR 115200 /* baudrate var(0) */ +#define CFG_NIOS_CPU_UART0_DB 8 /* data bit */ +#define CFG_NIOS_CPU_UART0_SB 1 /* stop bit */ +#define CFG_NIOS_CPU_UART0_PA 0 /* parity none(0) */ + /* odd(1) */ + /* even(2) */ +#define CFG_NIOS_CPU_UART0_HS 0 /* handshake: no(0) */ + /* crts(1) */ +#define CFG_NIOS_CPU_UART0_EOP 0 /* eop reg: no(0) */ + /* yes(1) */ + +/* parallel i/o */ +#define CFG_NIOS_CPU_PIO_NUMS 8 /* number of parports */ + +#define CFG_NIOS_CPU_PIO0 0x00920960 /* PIO0 addr */ +#define CFG_NIOS_CPU_PIO0_IRQ 40 /* IRQ */ +#define CFG_NIOS_CPU_PIO0_BITS 4 /* number of bits */ +#define CFG_NIOS_CPU_PIO0_TYPE 2 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO0_CAP 1 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO0_EDGE 3 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO0_ITYPE 2 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +#define CFG_NIOS_CPU_PIO1 0x00920970 /* PIO1 addr */ +#undef CFG_NIOS_CPU_PIO1_IRQ /* w/o IRQ */ +#define CFG_NIOS_CPU_PIO1_BITS 11 /* number of bits */ +#define CFG_NIOS_CPU_PIO1_TYPE 0 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO1_CAP 0 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO1_EDGE 0 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO1_ITYPE 0 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +#define CFG_NIOS_CPU_PIO2 0x00920980 /* PIO2 addr */ +#undef CFG_NIOS_CPU_PIO2_IRQ /* w/o IRQ */ +#define CFG_NIOS_CPU_PIO2_BITS 8 /* number of bits */ +#define CFG_NIOS_CPU_PIO2_TYPE 1 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO2_CAP 0 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO2_EDGE 0 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO2_ITYPE 0 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +#define CFG_NIOS_CPU_PIO3 0x00920990 /* PIO3 addr */ +#undef CFG_NIOS_CPU_PIO3_IRQ /* w/o IRQ */ +#define CFG_NIOS_CPU_PIO3_BITS 16 /* number of bits */ +#define CFG_NIOS_CPU_PIO3_TYPE 1 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO3_CAP 0 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO3_EDGE 0 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO3_ITYPE 0 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +#define CFG_NIOS_CPU_PIO4 0x009209a0 /* PIO4 addr */ +#undef CFG_NIOS_CPU_PIO4_IRQ /* w/o IRQ */ +#define CFG_NIOS_CPU_PIO4_BITS 1 /* number of bits */ +#define CFG_NIOS_CPU_PIO4_TYPE 0 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO4_CAP 0 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO4_EDGE 0 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO4_ITYPE 0 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +#define CFG_NIOS_CPU_PIO5 0x009209b0 /* PIO5 addr */ +#define CFG_NIOS_CPU_PIO5_IRQ 35 /* IRQ */ +#define CFG_NIOS_CPU_PIO5_BITS 1 /* number of bits */ +#define CFG_NIOS_CPU_PIO5_TYPE 2 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO5_CAP 1 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO5_EDGE 3 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO5_ITYPE 2 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +#define CFG_NIOS_CPU_PIO6 0x009209c0 /* PIO6 addr */ +#undef CFG_NIOS_CPU_PIO6_IRQ /* w/o IRQ */ +#define CFG_NIOS_CPU_PIO6_BITS 1 /* number of bits */ +#define CFG_NIOS_CPU_PIO6_TYPE 1 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO6_CAP 0 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO6_EDGE 0 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO6_ITYPE 0 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +#define CFG_NIOS_CPU_PIO7 0x009209d0 /* PIO7 addr */ +#undef CFG_NIOS_CPU_PIO7_IRQ /* w/o IRQ */ +#define CFG_NIOS_CPU_PIO7_BITS 1 /* number of bits */ +#define CFG_NIOS_CPU_PIO7_TYPE 1 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO7_CAP 0 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO7_EDGE 0 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO7_ITYPE 0 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +/* IDE i/f */ +#define CFG_NIOS_CPU_IDE_NUMS 1 /* number of IDE contr. */ +#define CFG_NIOS_CPU_IDE0 0x00920a00 /* IDE0 addr */ + +/* active serial memory i/f */ +#define CFG_NIOS_CPU_ASMI_NUMS 1 /* number of ASMI */ +#define CFG_NIOS_CPU_ASMI0 0x00920b00 /* ASMI0 addr */ +#define CFG_NIOS_CPU_ASMI0_IRQ 45 /* IRQ */ + +/* memory accessibility */ +#define CFG_NIOS_CPU_SRAM_BASE 0x00800000 /* board SRAM addr */ +#define CFG_NIOS_CPU_SRAM_SIZE (1024 * 1024) /* 1 MB size */ + +#define CFG_NIOS_CPU_SDRAM_BASE 0x01000000 /* board SDRAM addr */ +#define CFG_NIOS_CPU_SDRAM_SIZE (16*1024*1024) /* 16 MB size */ + +#define CFG_NIOS_CPU_FLASH_BASE 0x00000000 /* board Flash addr */ +#define CFG_NIOS_CPU_FLASH_SIZE (8*1024*1024) /* 8 MB size */ + +/* LAN */ +#define CFG_NIOS_CPU_LAN_NUMS 1 /* number of LAN i/f */ + +#define CFG_NIOS_CPU_LAN0_BASE 0x00910000 /* LAN0 addr */ +#define CFG_NIOS_CPU_LAN0_OFFS 0x0300 /* offset */ +#define CFG_NIOS_CPU_LAN0_IRQ 30 /* IRQ */ +#define CFG_NIOS_CPU_LAN0_BUSW 32 /* buswidth*/ +#define CFG_NIOS_CPU_LAN0_TYPE 0 /* smc91111(0) */ + /* cs8900(1) */ + /* ex: alteramac(2) */ + +/* symbolic redefinition (undef, if not present) */ +#define CFG_NIOS_CPU_USER_TIMER 0 /* TIMER0: users choice */ +#define CFG_NIOS_CPU_TICK_TIMER 1 /* TIMER1: tick (needed)*/ + +#define CFG_NIOS_CPU_BUTTON_PIO 0 /* PIO0: buttons */ +#define CFG_NIOS_CPU_LCD_PIO 1 /* PIO1: ASCII LCD */ +#define CFG_NIOS_CPU_LED_PIO 2 /* PIO2: LED bar */ +#define CFG_NIOS_CPU_SEVENSEG_PIO 3 /* PIO3: 7-seg. display */ +#define CFG_NIOS_CPU_RECONF_PIO 4 /* PIO4: reconf pin */ +#define CFG_NIOS_CPU_CFPRESENT_PIO 5 /* PIO5: CF present IRQ */ +#define CFG_NIOS_CPU_CFPOWER_PIO 6 /* PIO6: CF power/sw. */ +#define CFG_NIOS_CPU_CFATASEL_PIO 7 /* PIO7: CF ATA select */ + +#endif /* __CONFIG_DK1C20_STANDARD_32_H */ diff --git a/include/configs/DK1S10.h b/include/configs/DK1S10.h index bd7ded52b9..835c7a23e1 100644 --- a/include/configs/DK1S10.h +++ b/include/configs/DK1S10.h @@ -24,264 +24,19 @@ #ifndef __CONFIG_H #define __CONFIG_H -/* - * NIOS CPU configuration. +/*********************************************************************** + * Include the whole NIOS CPU configuration. * - * Here we must define CPU dependencies. Any unsupported option have to - * be defined with zero, example CPU without data cache / OCI: + * !!! HAVE TO BE HERE !!! DON'T MOVE THIS PART !!! * - * #define CFG_NIOS_CPU_ICACHE 4096 - * #define CFG_NIOS_CPU_DCACHE 0 - * #define CFG_NIOS_CPU_OCI_BASE 0 - * #define CFG_NIOS_CPU_OCI_SIZE 0 - */ + ***********************************************************************/ #if defined(CONFIG_NIOS_SAFE_32) - -/* TODO */ - +#include <configs/DK1S10_safe_32.h> #elif defined(CONFIG_NIOS_STANDARD_32) - -/* CPU core */ -#define CFG_NIOS_CPU_CLK 50000000 /* NIOS CPU clock */ -#define CFG_NIOS_CPU_ICACHE (4 * 1024) /* instruction cache */ -#define CFG_NIOS_CPU_DCACHE (4 * 1024) /* data cache */ -#define CFG_NIOS_CPU_REG_NUMS 256 /* number of register */ -#define CFG_NIOS_CPU_MUL 0 /* 16x16 MUL: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_MSTEP 1 /* 16x16 MSTEP: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_STACK 0x008fff00 /* stack top addr */ -#define CFG_NIOS_CPU_VEC_BASE 0x008fff00 /* IRQ vectors addr */ -#define CFG_NIOS_CPU_VEC_SIZE 256 /* size */ -#define CFG_NIOS_CPU_VEC_NUMS 64 /* numbers */ -#define CFG_NIOS_CPU_RST_VECT 0x00920000 /* RESET vector addr */ -#define CFG_NIOS_CPU_DBG_CORE 0 /* CPU debug: no(0) */ - /* yes(1) */ - -/* on-chip extensions */ -#define CFG_NIOS_CPU_RAM_BASE 0x00900000 /* on chip RAM addr */ -#define CFG_NIOS_CPU_RAM_SIZE (64 * 1024) /* 64 KB size */ - -#define CFG_NIOS_CPU_ROM_BASE 0x00920000 /* on chip ROM addr */ -#define CFG_NIOS_CPU_ROM_SIZE (2 * 1024) /* 2 KB size */ - -#define CFG_NIOS_CPU_OCI_BASE 0x00920800 /* OCI core addr */ -#define CFG_NIOS_CPU_OCI_SIZE 256 /* size */ - -/* timer */ -#define CFG_NIOS_CPU_TIMER_NUMS 2 /* number of timer */ - -#define CFG_NIOS_CPU_TIMER0 0x00920940 /* TIMER0 addr */ -#define CFG_NIOS_CPU_TIMER0_IRQ 16 /* IRQ */ -#define CFG_NIOS_CPU_TIMER0_PER 1000 /* periode usec */ -#define CFG_NIOS_CPU_TIMER0_AR 0 /* always run: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_TIMER0_FP 0 /* fixed per: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_TIMER0_SS 1 /* snaphot: no(0) */ - /* yes(1) */ - -#define CFG_NIOS_CPU_TIMER1 0x009209e0 /* TIMER1 addr */ -#define CFG_NIOS_CPU_TIMER1_IRQ 50 /* IRQ */ -#define CFG_NIOS_CPU_TIMER1_PER 10000 /* periode usec */ -#define CFG_NIOS_CPU_TIMER1_AR 1 /* always run: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_TIMER1_FP 1 /* fixed per: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_TIMER1_SS 0 /* snaphot: no(0) */ - /* yes(1) */ - -/* serial i/o */ -#define CFG_NIOS_CPU_UART_NUMS 1 /* number of uarts */ - -#define CFG_NIOS_CPU_UART0 0x00920900 /* UART0 addr */ -#define CFG_NIOS_CPU_UART0_IRQ 25 /* IRQ */ -#define CFG_NIOS_CPU_UART0_BR 115200 /* baudrate var(0) */ -#define CFG_NIOS_CPU_UART0_DB 8 /* data bit */ -#define CFG_NIOS_CPU_UART0_SB 1 /* stop bit */ -#define CFG_NIOS_CPU_UART0_PA 0 /* parity none(0) */ - /* odd(1) */ - /* even(2) */ -#define CFG_NIOS_CPU_UART0_HS 0 /* handshake: no(0) */ - /* crts(1) */ -#define CFG_NIOS_CPU_UART0_EOP 0 /* eop reg: no(0) */ - /* yes(1) */ - -/* parallel i/o */ -#define CFG_NIOS_CPU_PIO_NUMS 8 /* number of parports */ - -#define CFG_NIOS_CPU_PIO0 0x00920960 /* PIO0 addr */ -#define CFG_NIOS_CPU_PIO0_IRQ 40 /* IRQ */ -#define CFG_NIOS_CPU_PIO0_BITS 4 /* number of bits */ -#define CFG_NIOS_CPU_PIO0_TYPE 2 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO0_CAP 1 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO0_EDGE 3 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO0_ITYPE 2 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CFG_NIOS_CPU_PIO1 0x00920970 /* PIO1 addr */ -#undef CFG_NIOS_CPU_PIO1_IRQ /* w/o IRQ */ -#define CFG_NIOS_CPU_PIO1_BITS 11 /* number of bits */ -#define CFG_NIOS_CPU_PIO1_TYPE 0 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO1_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO1_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO1_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CFG_NIOS_CPU_PIO2 0x00920980 /* PIO2 addr */ -#undef CFG_NIOS_CPU_PIO2_IRQ /* w/o IRQ */ -#define CFG_NIOS_CPU_PIO2_BITS 8 /* number of bits */ -#define CFG_NIOS_CPU_PIO2_TYPE 1 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO2_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO2_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO2_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CFG_NIOS_CPU_PIO3 0x00920990 /* PIO3 addr */ -#undef CFG_NIOS_CPU_PIO3_IRQ /* w/o IRQ */ -#define CFG_NIOS_CPU_PIO3_BITS 16 /* number of bits */ -#define CFG_NIOS_CPU_PIO3_TYPE 1 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO3_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO3_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO3_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CFG_NIOS_CPU_PIO4 0x009209a0 /* PIO4 addr */ -#undef CFG_NIOS_CPU_PIO4_IRQ /* w/o IRQ */ -#define CFG_NIOS_CPU_PIO4_BITS 1 /* number of bits */ -#define CFG_NIOS_CPU_PIO4_TYPE 0 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO4_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO4_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO4_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CFG_NIOS_CPU_PIO5 0x009209b0 /* PIO5 addr */ -#define CFG_NIOS_CPU_PIO5_IRQ 35 /* IRQ */ -#define CFG_NIOS_CPU_PIO5_BITS 1 /* number of bits */ -#define CFG_NIOS_CPU_PIO5_TYPE 2 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO5_CAP 1 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO5_EDGE 3 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO5_ITYPE 2 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CFG_NIOS_CPU_PIO6 0x009209c0 /* PIO6 addr */ -#undef CFG_NIOS_CPU_PIO6_IRQ /* w/o IRQ */ -#define CFG_NIOS_CPU_PIO6_BITS 1 /* number of bits */ -#define CFG_NIOS_CPU_PIO6_TYPE 1 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO6_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO6_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO6_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CFG_NIOS_CPU_PIO7 0x009209d0 /* PIO7 addr */ -#undef CFG_NIOS_CPU_PIO7_IRQ /* w/o IRQ */ -#define CFG_NIOS_CPU_PIO7_BITS 1 /* number of bits */ -#define CFG_NIOS_CPU_PIO7_TYPE 1 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO7_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO7_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO7_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -/* IDE i/f */ -#define CFG_NIOS_CPU_IDE_NUMS 1 /* number of IDE contr. */ -#define CFG_NIOS_CPU_IDE0 0x00920a00 /* IDE0 addr */ - -/* active serial memory i/f */ -#define CFG_NIOS_CPU_ASMI_NUMS 1 /* number of ASMI */ -#define CFG_NIOS_CPU_ASMI0 0x00920b00 /* ASMI0 addr */ -#define CFG_NIOS_CPU_ASMI0_IRQ 45 /* IRQ */ - -/* memory accessibility */ -#define CFG_NIOS_CPU_SRAM_BASE 0x00800000 /* board SRAM addr */ -#define CFG_NIOS_CPU_SRAM_SIZE (1024 * 1024) /* 1 MB size */ - -#define CFG_NIOS_CPU_SDRAM_BASE 0x01000000 /* board SDRAM addr */ -#define CFG_NIOS_CPU_SDRAM_SIZE (16*1024*1024) /* 16 MB size */ - -#define CFG_NIOS_CPU_FLASH_BASE 0x00000000 /* board Flash addr */ -#define CFG_NIOS_CPU_FLASH_SIZE (8*1024*1024) /* 8 MB size */ - -/* LAN */ -#define CFG_NIOS_CPU_LAN_NUMS 1 /* number of LAN i/f */ - -#define CFG_NIOS_CPU_LAN0_BASE 0x00910000 /* LAN0 addr */ -#define CFG_NIOS_CPU_LAN0_OFFS 0x0300 /* offset */ -#define CFG_NIOS_CPU_LAN0_IRQ 30 /* IRQ */ -#define CFG_NIOS_CPU_LAN0_BUSW 32 /* buswidth*/ -#define CFG_NIOS_CPU_LAN0_TYPE 0 /* smc91111(0) */ - /* cs8900(1) */ - /* ex: alteramac(2) */ - -/* symbolic redefinition (undef, if not present) */ -#define CFG_NIOS_CPU_USER_TIMER 0 /* TIMER0: users choice */ -#define CFG_NIOS_CPU_TICK_TIMER 1 /* TIMER1: tick (needed)*/ - -#define CFG_NIOS_CPU_BUTTON_PIO 0 /* PIO0: buttons */ -#define CFG_NIOS_CPU_LCD_PIO 1 /* PIO1: ASCII LCD */ -#define CFG_NIOS_CPU_LED_PIO 2 /* PIO2: LED bar */ -#define CFG_NIOS_CPU_SEVENSEG_PIO 3 /* PIO3: 7-seg. display */ -#define CFG_NIOS_CPU_RECONF_PIO 4 /* PIO4: reconf pin */ -#define CFG_NIOS_CPU_CFPRESENT_PIO 5 /* PIO5: CF present IRQ */ -#define CFG_NIOS_CPU_CFPOWER_PIO 6 /* PIO6: CF power/sw. */ -#define CFG_NIOS_CPU_CFATASEL_PIO 7 /* PIO7: CF ATA select */ - +#include <configs/DK1S10_standard_32.h> +#elif defined(CONFIG_NIOS_MTX_LDK_20) +#include <configs/DK1S10_mtx_ldk_20.h> #else #error *** CFG_ERROR: you have to setup right NIOS CPU configuration #endif @@ -308,8 +63,18 @@ #error *** CFG_ERROR: you have to setup any SDRAM in NIOS CPU config #endif -#define CFG_SRAM_BASE CFG_NIOS_CPU_SRAM_BASE -#define CFG_SRAM_SIZE CFG_NIOS_CPU_SRAM_SIZE +#if defined(CFG_NIOS_CPU_SRAM_BASE) && defined(CFG_NIOS_CPU_SRAM_SIZE) + +#define CFG_SRAM_BASE CFG_NIOS_CPU_SRAM_BASE +#define CFG_SRAM_SIZE CFG_NIOS_CPU_SRAM_SIZE + +#else + +#undef CFG_SRAM_BASE +#undef CFG_SRAM_SIZE + +#endif + #define CFG_VECT_BASE CFG_NIOS_CPU_VEC_BASE /*------------------------------------------------------------------------ @@ -355,7 +120,15 @@ #if (CFG_NIOS_CPU_FLASH_SIZE != 0) #define CFG_ENV_IS_IN_FLASH 1 /* Environment in flash */ + +#if defined(CONFIG_NIOS_STANDARD_32) #define CFG_ENV_ADDR CFG_FLASH_BASE /* Mem addr of env */ +#elif defined(CONFIG_NIOS_MTX_LDK_20) +#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN) +#else +#error *** CFG_ERROR: you have to setup the environment base address CFG_ENV_ADDR +#endif + #define CFG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */ #define CONFIG_ENV_OVERWRITE /* Serial/eth change Ok */ @@ -388,11 +161,18 @@ * TIMER FOR TIMEBASE -- Nios doesn't have the equivalent of ppc PIT, * so an avalon bus timer is required. *----------------------------------------------------------------------*/ -#if (CFG_NIOS_CPU_TIMER_NUMS != 0) +#if (CFG_NIOS_CPU_TIMER_NUMS != 0) && defined(CFG_NIOS_CPU_TICK_TIMER) #if (CFG_NIOS_CPU_TICK_TIMER == 0) -#error *** CFG_ERROR: tick timer at TIMER0 not supported, expand your config.h +#define CFG_NIOS_TMRBASE CFG_NIOS_CPU_TIMER0 /* TIMER0 as tick */ +#define CFG_NIOS_TMRIRQ CFG_NIOS_CPU_TIMER0_IRQ + +#if (CFG_NIOS_CPU_TIMER0_PER >= CFG_HZ) +#define CFG_NIOS_TMRMS (CFG_NIOS_CPU_TIMER0_PER / CFG_HZ) +#else +#error *** CFG_ERROR: you have to use a timer periode of more than CFG_HZ +#endif #elif (CFG_NIOS_CPU_TICK_TIMER == 1) @@ -418,9 +198,6 @@ #if (CFG_NIOS_CPU_LAN0_TYPE == 0) /* LAN91C111 */ - /****************************************************/ - /* !!! LAN91C111 works for NIOS with patch only !!! */ - /****************************************************/ #define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */ #undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */ #define CONFIG_SMC91111_BASE (CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS) @@ -463,7 +240,7 @@ /*------------------------------------------------------------------------ * STATUS LEDs *----------------------------------------------------------------------*/ -#if (CFG_NIOS_CPU_PIO_NUMS != 0) +#if (CFG_NIOS_CPU_PIO_NUMS != 0) && defined(CFG_NIOS_CPU_LED_PIO) #if (CFG_NIOS_CPU_LED_PIO == 0) @@ -553,19 +330,19 @@ /*------------------------------------------------------------------------ * SEVEN SEGMENT LED DISPLAY *----------------------------------------------------------------------*/ -#if (CFG_NIOS_CPU_PIO_NUMS != 0) +#if (CFG_NIOS_CPU_PIO_NUMS != 0) && defined(CFG_NIOS_CPU_SEVENSEG_PIO) #if (CFG_NIOS_CPU_SEVENSEG_PIO == 0) -#error *** CFG_ERROR: status LEDs at PIO0 not supported, expand your config.h +#error *** CFG_ERROR: seven segment display at PIO0 not supported, expand your config.h #elif (CFG_NIOS_CPU_SEVENSEG_PIO == 1) -#error *** CFG_ERROR: status LEDs at PIO1 not supported, expand your config.h +#error *** CFG_ERROR: seven segment display at PIO1 not supported, expand your config.h #elif (CFG_NIOS_CPU_SEVENSEG_PIO == 2) -#error *** CFG_ERROR: status LEDs at PIO2 not supported, expand your config.h +#error *** CFG_ERROR: seven segment display at PIO2 not supported, expand your config.h #elif (CFG_NIOS_CPU_SEVENSEG_PIO == 3) @@ -581,27 +358,27 @@ #elif (CFG_NIOS_CPU_SEVENSEG_PIO == 4) -#error *** CFG_ERROR: status LEDs at PIO4 not supported, expand your config.h +#error *** CFG_ERROR: seven segment display at PIO4 not supported, expand your config.h #elif (CFG_NIOS_CPU_SEVENSEG_PIO == 5) -#error *** CFG_ERROR: status LEDs at PIO5 not supported, expand your config.h +#error *** CFG_ERROR: seven segment display at PIO5 not supported, expand your config.h #elif (CFG_NIOS_CPU_SEVENSEG_PIO == 6) -#error *** CFG_ERROR: status LEDs at PIO6 not supported, expand your config.h +#error *** CFG_ERROR: seven segment display at PIO6 not supported, expand your config.h #elif (CFG_NIOS_CPU_SEVENSEG_PIO == 7) -#error *** CFG_ERROR: status LEDs at PIO7 not supported, expand your config.h +#error *** CFG_ERROR: seven segment display at PIO7 not supported, expand your config.h #elif (CFG_NIOS_CPU_SEVENSEG_PIO == 8) -#error *** CFG_ERROR: status LEDs at PIO8 not supported, expand your config.h +#error *** CFG_ERROR: seven segment display at PIO8 not supported, expand your config.h #elif (CFG_NIOS_CPU_SEVENSEG_PIO == 9) -#error *** CFG_ERROR: status LEDs at PIO9 not supported, expand your config.h +#error *** CFG_ERROR: seven segment display at PIO9 not supported, expand your config.h #else #error *** CFG_ERROR: you have to set CFG_NIOS_CPU_SEVENSEG_PIO in right case @@ -692,17 +469,40 @@ #define CFG_MAXARGS 16 /* max number of command args*/ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +/* Default load address */ #if (CFG_SRAM_SIZE != 0) -#define CFG_LOAD_ADDR CFG_SRAM_BASE /* Default load address */ + +/* default in SRAM */ +#define CFG_LOAD_ADDR CFG_SRAM_BASE + +#elif (CFG_SDRAM_SIZE != 0) + +/* default in SDRAM */ +#if (CFG_SDRAM_BASE == CFG_NIOS_CPU_VEC_BASE) +#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + CFG_NIOS_CPU_VEC_SIZE) +#else +#define CFG_LOAD_ADDR CFG_SDRAM_BASE +#endif + #else -#undef CFG_LOAD_ADDR +#undef CFG_LOAD_ADDR /* force error break */ #endif + +/* MEM test area */ #if (CFG_SDRAM_SIZE != 0) -#define CFG_MEMTEST_START CFG_SDRAM_BASE /* SDRAM til stack area */ -#define CFG_MEMTEST_END (CFG_INIT_SP - (1024 * 1024)) /* 1MB stack */ + +/* SDRAM begin to stack area (1MB stack) */ +#if (CFG_SDRAM_BASE == CFG_NIOS_CPU_VEC_BASE) +#define CFG_MEMTEST_START (CFG_SDRAM_BASE + CFG_NIOS_CPU_VEC_SIZE) +#define CFG_MEMTEST_END (CFG_INIT_SP - (1024 * 1024)) +#else +#define CFG_MEMTEST_START CFG_SDRAM_BASE +#define CFG_MEMTEST_END (CFG_INIT_SP - (1024 * 1024)) +#endif + #else -#undef CFG_MEMTEST_START +#undef CFG_MEMTEST_START /* force error break */ #undef CFG_MEMTEST_END #endif diff --git a/include/configs/DK1S10_mtx_ldk_20.h b/include/configs/DK1S10_mtx_ldk_20.h new file mode 100644 index 0000000000..4eb96290bb --- /dev/null +++ b/include/configs/DK1S10_mtx_ldk_20.h @@ -0,0 +1,187 @@ +/* + * (C) Copyright 2003, Li-Pro.Net <www.li-pro.net> + * Stephan Linz <linz@li-pro.net> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_DK1S10_MTX_LDK_20_H +#define __CONFIG_DK1S10_MTX_LDK_20_H + +/* + * NIOS CPU configuration. (PART OF configs/DK1S10.h) + * + * Here we must define CPU dependencies. Any unsupported option have to + * be defined with zero, example CPU without data cache / OCI: + * + * #define CFG_NIOS_CPU_ICACHE 4096 + * #define CFG_NIOS_CPU_DCACHE 0 + * #define CFG_NIOS_CPU_OCI_BASE 0 + * #define CFG_NIOS_CPU_OCI_SIZE 0 + */ + +/* CPU core */ +#define CFG_NIOS_CPU_CLK 75000000 /* NIOS CPU clock */ +#define CFG_NIOS_CPU_ICACHE (0) /* instruction cache */ +#define CFG_NIOS_CPU_DCACHE (0) /* data cache */ +#define CFG_NIOS_CPU_REG_NUMS 512 /* number of register */ +#define CFG_NIOS_CPU_MUL 0 /* 16x16 MUL: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_MSTEP 1 /* 16x16 MSTEP: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_STACK 0x02000000 /* stack top addr */ +#define CFG_NIOS_CPU_VEC_BASE 0x01000000 /* IRQ vectors addr */ +#define CFG_NIOS_CPU_VEC_SIZE 256 /* size */ +#define CFG_NIOS_CPU_VEC_NUMS 64 /* numbers */ +#define CFG_NIOS_CPU_RST_VECT 0x00000000 /* RESET vector addr */ +#define CFG_NIOS_CPU_DBG_CORE 0 /* CPU debug: no(0) */ + /* yes(1) */ + +/* The offset address in flash to check for the Nios signature "Ni". + * (see GM_FlashExec in germs_monitor.s) */ +#define CFG_NIOS_CPU_EXES_OFFS 0x0C + +/* on-chip extensions */ +#undef CFG_NIOS_CPU_RAM_BASE /* on chip RAM addr */ +#undef CFG_NIOS_CPU_RAM_SIZE /* 64 KB size */ + +#define CFG_NIOS_CPU_ROM_BASE 0x00000000 /* on chip ROM addr */ +#define CFG_NIOS_CPU_ROM_SIZE (2 * 1024) /* 2 KB size */ + +#undef CFG_NIOS_CPU_OCI_BASE /* OCI core addr */ +#undef CFG_NIOS_CPU_OCI_SIZE /* size */ + +/* timer */ +#define CFG_NIOS_CPU_TIMER_NUMS 1 /* number of timer */ + +#define CFG_NIOS_CPU_TIMER0 0x00000840 /* TIMER0 addr */ +#define CFG_NIOS_CPU_TIMER0_IRQ 16 /* IRQ */ +#define CFG_NIOS_CPU_TIMER0_PER 1000 /* periode usec */ +#define CFG_NIOS_CPU_TIMER0_AR 0 /* always run: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_TIMER0_FP 0 /* fixed per: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_TIMER0_SS 1 /* snaphot: no(0) */ + /* yes(1) */ + +/* serial i/o */ +#define CFG_NIOS_CPU_UART_NUMS 2 /* number of uarts */ + +#define CFG_NIOS_CPU_UART0 0x00000800 /* UART0 addr */ +#define CFG_NIOS_CPU_UART0_IRQ 17 /* IRQ */ +#define CFG_NIOS_CPU_UART0_BR 115200 /* baudrate var(0) */ +#define CFG_NIOS_CPU_UART0_DB 8 /* data bit */ +#define CFG_NIOS_CPU_UART0_SB 2 /* stop bit */ +#define CFG_NIOS_CPU_UART0_PA 0 /* parity none(0) */ + /* odd(1) */ + /* even(2) */ +#define CFG_NIOS_CPU_UART0_HS 0 /* handshake: no(0) */ + /* crts(1) */ +#define CFG_NIOS_CPU_UART0_EOP 0 /* eop reg: no(0) */ + /* yes(1) */ + +#define CFG_NIOS_CPU_UART1 0x000008a0 /* UART1 addr */ +#define CFG_NIOS_CPU_UART1_IRQ 18 /* IRQ */ +#define CFG_NIOS_CPU_UART1_BR 115200 /* baudrate var(0) */ +#define CFG_NIOS_CPU_UART1_DB 8 /* data bit */ +#define CFG_NIOS_CPU_UART1_SB 1 /* stop bit */ +#define CFG_NIOS_CPU_UART1_PA 0 /* parity none(0) */ + /* odd(1) */ + /* even(2) */ +#define CFG_NIOS_CPU_UART1_HS 0 /* handshake: no(0) */ + /* crts(1) */ +#define CFG_NIOS_CPU_UART1_EOP 0 /* eop reg: no(0) */ + /* yes(1) */ + +/* parallel i/o */ +#define CFG_NIOS_CPU_PIO_NUMS 2 /* number of parports */ + +#define CFG_NIOS_CPU_PIO0 0x00000860 /* PIO0 addr */ +#undef CFG_NIOS_CPU_PIO0_IRQ /* w/o IRQ */ +#define CFG_NIOS_CPU_PIO0_BITS 1 /* number of bits */ +#define CFG_NIOS_CPU_PIO0_TYPE 1 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO0_CAP 0 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO0_EDGE 0 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO0_ITYPE 0 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +#define CFG_NIOS_CPU_PIO1 0x00000870 /* PIO1 addr */ +#undef CFG_NIOS_CPU_PIO1_IRQ /* w/o IRQ */ +#define CFG_NIOS_CPU_PIO1_BITS 4 /* number of bits */ +#define CFG_NIOS_CPU_PIO1_TYPE 2 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO1_CAP 0 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO1_EDGE 0 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO1_ITYPE 0 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +/* IDE i/f */ +#define CFG_NIOS_CPU_IDE_NUMS 1 /* number of IDE contr. */ +#define CFG_NIOS_CPU_IDE0 0x00000900 /* IDE0 addr */ +#define CFG_NIOS_CPU_IDE0_IRQ 25 /* IRQ */ + +/* memory accessibility */ +#undef CFG_NIOS_CPU_SRAM_BASE /* board SRAM addr */ +#undef CFG_NIOS_CPU_SRAM_SIZE /* 1 MB size */ + +#define CFG_NIOS_CPU_SDRAM_BASE 0x01000000 /* board SDRAM addr */ +#define CFG_NIOS_CPU_SDRAM_SIZE (16*1024*1024) /* 16 MB size */ + +#define CFG_NIOS_CPU_FLASH_BASE 0x00800000 /* board Flash addr */ +#define CFG_NIOS_CPU_FLASH_SIZE (8*1024*1024) /* 8 MB size */ + +/* LAN */ +#define CFG_NIOS_CPU_LAN_NUMS 1 /* number of LAN i/f */ + +#define CFG_NIOS_CPU_LAN0_BASE 0x00010000 /* LAN0 addr */ +#define CFG_NIOS_CPU_LAN0_OFFS 0x0300 /* offset */ +#define CFG_NIOS_CPU_LAN0_IRQ 20 /* IRQ */ +#define CFG_NIOS_CPU_LAN0_BUSW 32 /* buswidth*/ +#define CFG_NIOS_CPU_LAN0_TYPE 0 /* smc91111(0) */ + /* cs8900(1) */ + /* ex: openmac(2) */ + /* ex: alteramac(3) */ + +/* symbolic redefinition (undef, if not present) */ +#define CFG_NIOS_CPU_TICK_TIMER 0 /* TIMER0: tick (needed)*/ +#undef CFG_NIOS_CPU_USER_TIMER /* TIMERx: users choice */ + +#define CFG_NIOS_CPU_CFPOWER_PIO 0 /* PIO0: CF power/sw. */ +#define CFG_NIOS_CPU_BUTTON_PIO 1 /* PIO1: buttons */ +#undef CFG_NIOS_CPU_LCD_PIO /* PIOx: ASCII LCD */ +#undef CFG_NIOS_CPU_LED_PIO /* PIOx: LED bar */ +#undef CFG_NIOS_CPU_SEVENSEG_PIO /* PIOx: 7-seg. display */ +#undef CFG_NIOS_CPU_RECONF_PIO /* PIOx: reconf pin */ +#undef CFG_NIOS_CPU_CFPRESENT_PIO /* PIOx: CF present IRQ */ +#undef CFG_NIOS_CPU_CFATASEL_PIO /* PIOx: CF ATA select */ + +#endif /* __CONFIG_DK1S10_MTX_LDK_20_H */ diff --git a/include/configs/DK1S10_safe_32.h b/include/configs/DK1S10_safe_32.h new file mode 100644 index 0000000000..8541a119f7 --- /dev/null +++ b/include/configs/DK1S10_safe_32.h @@ -0,0 +1,34 @@ +/* + * (C) Copyright 2003, Li-Pro.Net <www.li-pro.net> + * Stephan Linz <linz@li-pro.net> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_DK1S10_SAFE_32_H +#define __CONFIG_DK1S10_SAFE_32_H + +/* + * NIOS CPU configuration. (PART OF configs/DK1S10.h) + * + * !!! TODO !!! TODO !!! + */ +#error *** CFG_ERROR: DK1S10_safe_32 have to be defined (use DK1S10_standard_32 as template) + +#endif /* __CONFIG_DK1S10_SAFE_32_H */ diff --git a/include/configs/DK1S10_standard_32.h b/include/configs/DK1S10_standard_32.h new file mode 100644 index 0000000000..b83c31592a --- /dev/null +++ b/include/configs/DK1S10_standard_32.h @@ -0,0 +1,274 @@ +/* + * (C) Copyright 2003, Li-Pro.Net <www.li-pro.net> + * Stephan Linz <linz@li-pro.net> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_DK1S10_STANDARD_32_H +#define __CONFIG_DK1S10_STANDARD_32_H + +/* + * NIOS CPU configuration. (PART OF configs/DK1S10.h) + * + * Here we must define CPU dependencies. Any unsupported option have to + * be defined with zero, example CPU without data cache / OCI: + * + * #define CFG_NIOS_CPU_ICACHE 4096 + * #define CFG_NIOS_CPU_DCACHE 0 + * #define CFG_NIOS_CPU_OCI_BASE 0 + * #define CFG_NIOS_CPU_OCI_SIZE 0 + */ + +/* CPU core */ +#define CFG_NIOS_CPU_CLK 50000000 /* NIOS CPU clock */ +#define CFG_NIOS_CPU_ICACHE (4 * 1024) /* instruction cache */ +#define CFG_NIOS_CPU_DCACHE (4 * 1024) /* data cache */ +#define CFG_NIOS_CPU_REG_NUMS 256 /* number of register */ +#define CFG_NIOS_CPU_MUL 0 /* 16x16 MUL: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_MSTEP 1 /* 16x16 MSTEP: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_STACK 0x008fff00 /* stack top addr */ +#define CFG_NIOS_CPU_VEC_BASE 0x008fff00 /* IRQ vectors addr */ +#define CFG_NIOS_CPU_VEC_SIZE 256 /* size */ +#define CFG_NIOS_CPU_VEC_NUMS 64 /* numbers */ +#define CFG_NIOS_CPU_RST_VECT 0x00920000 /* RESET vector addr */ +#define CFG_NIOS_CPU_DBG_CORE 0 /* CPU debug: no(0) */ + /* yes(1) */ + +/* on-chip extensions */ +#define CFG_NIOS_CPU_RAM_BASE 0x00900000 /* on chip RAM addr */ +#define CFG_NIOS_CPU_RAM_SIZE (64 * 1024) /* 64 KB size */ + +#define CFG_NIOS_CPU_ROM_BASE 0x00920000 /* on chip ROM addr */ +#define CFG_NIOS_CPU_ROM_SIZE (2 * 1024) /* 2 KB size */ + +#define CFG_NIOS_CPU_OCI_BASE 0x00920800 /* OCI core addr */ +#define CFG_NIOS_CPU_OCI_SIZE 256 /* size */ + +/* timer */ +#define CFG_NIOS_CPU_TIMER_NUMS 2 /* number of timer */ + +#define CFG_NIOS_CPU_TIMER0 0x00920940 /* TIMER0 addr */ +#define CFG_NIOS_CPU_TIMER0_IRQ 16 /* IRQ */ +#define CFG_NIOS_CPU_TIMER0_PER 1000 /* periode usec */ +#define CFG_NIOS_CPU_TIMER0_AR 0 /* always run: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_TIMER0_FP 0 /* fixed per: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_TIMER0_SS 1 /* snaphot: no(0) */ + /* yes(1) */ + +#define CFG_NIOS_CPU_TIMER1 0x009209e0 /* TIMER1 addr */ +#define CFG_NIOS_CPU_TIMER1_IRQ 50 /* IRQ */ +#define CFG_NIOS_CPU_TIMER1_PER 10000 /* periode usec */ +#define CFG_NIOS_CPU_TIMER1_AR 1 /* always run: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_TIMER1_FP 1 /* fixed per: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_TIMER1_SS 0 /* snaphot: no(0) */ + /* yes(1) */ + +/* serial i/o */ +#define CFG_NIOS_CPU_UART_NUMS 1 /* number of uarts */ + +#define CFG_NIOS_CPU_UART0 0x00920900 /* UART0 addr */ +#define CFG_NIOS_CPU_UART0_IRQ 25 /* IRQ */ +#define CFG_NIOS_CPU_UART0_BR 115200 /* baudrate var(0) */ +#define CFG_NIOS_CPU_UART0_DB 8 /* data bit */ +#define CFG_NIOS_CPU_UART0_SB 1 /* stop bit */ +#define CFG_NIOS_CPU_UART0_PA 0 /* parity none(0) */ + /* odd(1) */ + /* even(2) */ +#define CFG_NIOS_CPU_UART0_HS 0 /* handshake: no(0) */ + /* crts(1) */ +#define CFG_NIOS_CPU_UART0_EOP 0 /* eop reg: no(0) */ + /* yes(1) */ + +/* parallel i/o */ +#define CFG_NIOS_CPU_PIO_NUMS 8 /* number of parports */ + +#define CFG_NIOS_CPU_PIO0 0x00920960 /* PIO0 addr */ +#define CFG_NIOS_CPU_PIO0_IRQ 40 /* IRQ */ +#define CFG_NIOS_CPU_PIO0_BITS 4 /* number of bits */ +#define CFG_NIOS_CPU_PIO0_TYPE 2 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO0_CAP 1 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO0_EDGE 3 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO0_ITYPE 2 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +#define CFG_NIOS_CPU_PIO1 0x00920970 /* PIO1 addr */ +#undef CFG_NIOS_CPU_PIO1_IRQ /* w/o IRQ */ +#define CFG_NIOS_CPU_PIO1_BITS 11 /* number of bits */ +#define CFG_NIOS_CPU_PIO1_TYPE 0 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO1_CAP 0 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO1_EDGE 0 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO1_ITYPE 0 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +#define CFG_NIOS_CPU_PIO2 0x00920980 /* PIO2 addr */ +#undef CFG_NIOS_CPU_PIO2_IRQ /* w/o IRQ */ +#define CFG_NIOS_CPU_PIO2_BITS 8 /* number of bits */ +#define CFG_NIOS_CPU_PIO2_TYPE 1 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO2_CAP 0 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO2_EDGE 0 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO2_ITYPE 0 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +#define CFG_NIOS_CPU_PIO3 0x00920990 /* PIO3 addr */ +#undef CFG_NIOS_CPU_PIO3_IRQ /* w/o IRQ */ +#define CFG_NIOS_CPU_PIO3_BITS 16 /* number of bits */ +#define CFG_NIOS_CPU_PIO3_TYPE 1 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO3_CAP 0 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO3_EDGE 0 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO3_ITYPE 0 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +#define CFG_NIOS_CPU_PIO4 0x009209a0 /* PIO4 addr */ +#undef CFG_NIOS_CPU_PIO4_IRQ /* w/o IRQ */ +#define CFG_NIOS_CPU_PIO4_BITS 1 /* number of bits */ +#define CFG_NIOS_CPU_PIO4_TYPE 0 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO4_CAP 0 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO4_EDGE 0 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO4_ITYPE 0 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +#define CFG_NIOS_CPU_PIO5 0x009209b0 /* PIO5 addr */ +#define CFG_NIOS_CPU_PIO5_IRQ 35 /* IRQ */ +#define CFG_NIOS_CPU_PIO5_BITS 1 /* number of bits */ +#define CFG_NIOS_CPU_PIO5_TYPE 2 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO5_CAP 1 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO5_EDGE 3 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO5_ITYPE 2 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +#define CFG_NIOS_CPU_PIO6 0x009209c0 /* PIO6 addr */ +#undef CFG_NIOS_CPU_PIO6_IRQ /* w/o IRQ */ +#define CFG_NIOS_CPU_PIO6_BITS 1 /* number of bits */ +#define CFG_NIOS_CPU_PIO6_TYPE 1 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO6_CAP 0 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO6_EDGE 0 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO6_ITYPE 0 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +#define CFG_NIOS_CPU_PIO7 0x009209d0 /* PIO7 addr */ +#undef CFG_NIOS_CPU_PIO7_IRQ /* w/o IRQ */ +#define CFG_NIOS_CPU_PIO7_BITS 1 /* number of bits */ +#define CFG_NIOS_CPU_PIO7_TYPE 1 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO7_CAP 0 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO7_EDGE 0 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO7_ITYPE 0 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +/* IDE i/f */ +#define CFG_NIOS_CPU_IDE_NUMS 1 /* number of IDE contr. */ +#define CFG_NIOS_CPU_IDE0 0x00920a00 /* IDE0 addr */ + +/* memory accessibility */ +#define CFG_NIOS_CPU_SRAM_BASE 0x00800000 /* board SRAM addr */ +#define CFG_NIOS_CPU_SRAM_SIZE (1024 * 1024) /* 1 MB size */ + +#define CFG_NIOS_CPU_SDRAM_BASE 0x01000000 /* board SDRAM addr */ +#define CFG_NIOS_CPU_SDRAM_SIZE (16*1024*1024) /* 16 MB size */ + +#define CFG_NIOS_CPU_FLASH_BASE 0x00000000 /* board Flash addr */ +#define CFG_NIOS_CPU_FLASH_SIZE (8*1024*1024) /* 8 MB size */ + +/* LAN */ +#define CFG_NIOS_CPU_LAN_NUMS 1 /* number of LAN i/f */ + +#define CFG_NIOS_CPU_LAN0_BASE 0x00910000 /* LAN0 addr */ +#define CFG_NIOS_CPU_LAN0_OFFS 0x0300 /* offset */ +#define CFG_NIOS_CPU_LAN0_IRQ 30 /* IRQ */ +#define CFG_NIOS_CPU_LAN0_BUSW 32 /* buswidth*/ +#define CFG_NIOS_CPU_LAN0_TYPE 0 /* smc91111(0) */ + /* cs8900(1) */ + /* ex: alteramac(2) */ + +/* symbolic redefinition (undef, if not present) */ +#define CFG_NIOS_CPU_USER_TIMER 0 /* TIMER0: users choice */ +#define CFG_NIOS_CPU_TICK_TIMER 1 /* TIMER1: tick (needed)*/ + +#define CFG_NIOS_CPU_BUTTON_PIO 0 /* PIO0: buttons */ +#define CFG_NIOS_CPU_LCD_PIO 1 /* PIO1: ASCII LCD */ +#define CFG_NIOS_CPU_LED_PIO 2 /* PIO2: LED bar */ +#define CFG_NIOS_CPU_SEVENSEG_PIO 3 /* PIO3: 7-seg. display */ +#define CFG_NIOS_CPU_RECONF_PIO 4 /* PIO4: reconf pin */ +#define CFG_NIOS_CPU_CFPRESENT_PIO 5 /* PIO5: CF present IRQ */ +#define CFG_NIOS_CPU_CFPOWER_PIO 6 /* PIO6: CF power/sw. */ +#define CFG_NIOS_CPU_CFATASEL_PIO 7 /* PIO7: CF ATA select */ + +#endif /* __CONFIG_DK1S10_STANDARD_32_H */ diff --git a/include/nios-io.h b/include/nios-io.h index 64da92abfe..08aa9f976c 100644 --- a/include/nios-io.h +++ b/include/nios-io.h @@ -117,7 +117,7 @@ typedef volatile struct nios_spi_t { unsigned status; /* Status reg */ unsigned control; /* Control reg */ unsigned reserved; /* (master only) */ - unsigned slaveselect; /* SPI slave selct mask (master only) */ + unsigned slaveselect; /* SPI slave select mask (master only) */ }nios_spi_t; /* status register */ diff --git a/lib_nios/board.c b/lib_nios/board.c index 08085c2bb0..fb477e94e0 100644 --- a/lib_nios/board.c +++ b/lib_nios/board.c @@ -132,8 +132,10 @@ void board_init (void) bd->bi_memstart = CFG_SDRAM_BASE; bd->bi_memsize = CFG_SDRAM_SIZE; bd->bi_flashstart = CFG_FLASH_BASE; +#if defined(CFG_SRAM_BASE) && defined(CFG_SRAM_SIZE) bd->bi_sramstart= CFG_SRAM_BASE; bd->bi_sramsize = CFG_SRAM_SIZE; +#endif bd->bi_baudrate = CONFIG_BAUDRATE; for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { diff --git a/rtc/ds1306.c b/rtc/ds1306.c index 9c11c600d6..20f1a50856 100644 --- a/rtc/ds1306.c +++ b/rtc/ds1306.c @@ -1,6 +1,9 @@ /* * (C) Copyright 2002 SIXNET, dge@sixnetio.com. * + * (C) Copyright 2004, Li-Pro.Net <www.li-pro.net> + * Stephan Linz <linz@li-pro.net> + * * See file CREDITS for list of people who contributed to this * project. * @@ -21,20 +24,66 @@ */ /* - * Date & Time support for DS1306 RTC using software SPI + * Date & Time support for DS1306 RTC using SPI: + * + * - SXNI855T: it uses its own soft SPI here in this file + * - all other: use the external spi_xfer() function + * (see include/spi.h) */ #include <common.h> #include <command.h> #include <rtc.h> +#include <spi.h> #if defined(CONFIG_RTC_DS1306) && (CONFIG_COMMANDS & CFG_CMD_DATE) -static unsigned int bin2bcd(unsigned int n); -static unsigned char bcd2bin(unsigned char c); -static void soft_spi_send(unsigned char n); -static unsigned char soft_spi_read(void); -static void init_spi(void); +#define RTC_SECONDS 0x00 +#define RTC_MINUTES 0x01 +#define RTC_HOURS 0x02 +#define RTC_DAY_OF_WEEK 0x03 +#define RTC_DATE_OF_MONTH 0x04 +#define RTC_MONTH 0x05 +#define RTC_YEAR 0x06 + +#define RTC_SECONDS_ALARM0 0x07 +#define RTC_MINUTES_ALARM0 0x08 +#define RTC_HOURS_ALARM0 0x09 +#define RTC_DAY_OF_WEEK_ALARM0 0x0a + +#define RTC_SECONDS_ALARM1 0x0b +#define RTC_MINUTES_ALARM1 0x0c +#define RTC_HOURS_ALARM1 0x0d +#define RTC_DAY_OF_WEEK_ALARM1 0x0e + +#define RTC_CONTROL 0x0f +#define RTC_STATUS 0x10 +#define RTC_TRICKLE_CHARGER 0x11 + +#define RTC_USER_RAM_BASE 0x20 + +/* + * External table of chip select functions (see the appropriate board + * support for the actual definition of the table). + */ +extern spi_chipsel_type spi_chipsel[]; +extern int spi_chipsel_cnt; + +static unsigned int bin2bcd (unsigned int n); +static unsigned char bcd2bin (unsigned char c); +static unsigned char rtc_read (unsigned char reg); +static void rtc_write (unsigned char reg, unsigned char val); + + + + + +/* ************************************************************************* */ +#ifdef CONFIG_SXNI855T /* !!! SHOULD BE CHANGED TO NEW CODE !!! */ + +static void soft_spi_send (unsigned char n); +static unsigned char soft_spi_read (void); +static void init_spi (void); /*----------------------------------------------------------------------- * Definitions @@ -48,227 +97,349 @@ static void init_spi(void); /* ------------------------------------------------------------------------- */ /* read clock time from DS1306 and return it in *tmp */ -void rtc_get(struct rtc_time *tmp) +void rtc_get (struct rtc_time *tmp) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - unsigned char spi_byte; /* Data Byte */ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + unsigned char spi_byte; /* Data Byte */ + + init_spi (); /* set port B for software SPI */ + + /* Now we can enable the DS1306 RTC */ + immap->im_cpm.cp_pbdat |= PB_SPI_CE; + udelay (10); + + /* Shift out the address (0) of the time in the Clock Chip */ + soft_spi_send (0); + + /* Put the clock readings into the rtc_time structure */ + tmp->tm_sec = bcd2bin (soft_spi_read ()); /* Read seconds */ + tmp->tm_min = bcd2bin (soft_spi_read ()); /* Read minutes */ + + /* Hours are trickier */ + spi_byte = soft_spi_read (); /* Read Hours into temporary value */ + if (spi_byte & 0x40) { + /* 12 hour mode bit is set (time is in 1-12 format) */ + if (spi_byte & 0x20) { + /* since PM we add 11 to get 0-23 for hours */ + tmp->tm_hour = (bcd2bin (spi_byte & 0x1F)) + 11; + } else { + /* since AM we subtract 1 to get 0-23 for hours */ + tmp->tm_hour = (bcd2bin (spi_byte & 0x1F)) - 1; + } + } else { + /* Otherwise, 0-23 hour format */ + tmp->tm_hour = (bcd2bin (spi_byte & 0x3F)); + } - init_spi(); /* set port B for software SPI */ + soft_spi_read (); /* Read and discard Day of week */ + tmp->tm_mday = bcd2bin (soft_spi_read ()); /* Read Day of the Month */ + tmp->tm_mon = bcd2bin (soft_spi_read ()); /* Read Month */ - /* Now we can enable the DS1306 RTC */ - immap->im_cpm.cp_pbdat |= PB_SPI_CE; - udelay(10); + /* Read Year and convert to this century */ + tmp->tm_year = bcd2bin (soft_spi_read ()) + 2000; - /* Shift out the address (0) of the time in the Clock Chip */ - soft_spi_send(0); + /* Now we can disable the DS1306 RTC */ + immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; /* Disable DS1306 Chip */ + udelay (10); - /* Put the clock readings into the rtc_time structure */ - tmp->tm_sec = bcd2bin(soft_spi_read()); /* Read seconds */ - tmp->tm_min = bcd2bin(soft_spi_read()); /* Read minutes */ + GregorianDay (tmp); /* Determine the day of week */ - /* Hours are trickier */ - spi_byte = soft_spi_read(); /* Read Hours into temporary value */ - if (spi_byte & 0x40) { - /* 12 hour mode bit is set (time is in 1-12 format) */ - if (spi_byte & 0x20) { - /* since PM we add 11 to get 0-23 for hours */ - tmp->tm_hour = (bcd2bin(spi_byte & 0x1F)) + 11; - } - else { - /* since AM we subtract 1 to get 0-23 for hours */ - tmp->tm_hour = (bcd2bin(spi_byte & 0x1F)) - 1; + debug ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); +} + +/* ------------------------------------------------------------------------- */ + +/* set clock time in DS1306 RTC and in MPC8xx RTC */ +void rtc_set (struct rtc_time *tmp) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + + init_spi (); /* set port B for software SPI */ + + /* Now we can enable the DS1306 RTC */ + immap->im_cpm.cp_pbdat |= PB_SPI_CE; /* Enable DS1306 Chip */ + udelay (10); + + /* First disable write protect in the clock chip control register */ + soft_spi_send (0x8F); /* send address of the control register */ + soft_spi_send (0x00); /* send control register contents */ + + /* Now disable the DS1306 to terminate the write */ + immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; + udelay (10); + + /* Now enable the DS1306 to initiate a new write */ + immap->im_cpm.cp_pbdat |= PB_SPI_CE; + udelay (10); + + /* Next, send the address of the clock time write registers */ + soft_spi_send (0x80); /* send address of the first time register */ + + /* Use Burst Mode to send all of the time data to the clock */ + bin2bcd (tmp->tm_sec); + soft_spi_send (bin2bcd (tmp->tm_sec)); /* Send Seconds */ + soft_spi_send (bin2bcd (tmp->tm_min)); /* Send Minutes */ + soft_spi_send (bin2bcd (tmp->tm_hour)); /* Send Hour */ + soft_spi_send (bin2bcd (tmp->tm_wday)); /* Send Day of the Week */ + soft_spi_send (bin2bcd (tmp->tm_mday)); /* Send Day of Month */ + soft_spi_send (bin2bcd (tmp->tm_mon)); /* Send Month */ + soft_spi_send (bin2bcd (tmp->tm_year - 2000)); /* Send Year */ + + /* Now we can disable the Clock chip to terminate the burst write */ + immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; /* Disable DS1306 Chip */ + udelay (10); + + /* Now we can enable the Clock chip to initiate a new write */ + immap->im_cpm.cp_pbdat |= PB_SPI_CE; /* Enable DS1306 Chip */ + udelay (10); + + /* First we Enable write protect in the clock chip control register */ + soft_spi_send (0x8F); /* send address of the control register */ + soft_spi_send (0x40); /* send out Control Register contents */ + + /* Now disable the DS1306 */ + immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; /* Disable DS1306 Chip */ + udelay (10); + + /* Set standard MPC8xx clock to the same time so Linux will + * see the time even if it doesn't have a DS1306 clock driver. + * This helps with experimenting with standard kernels. + */ + { + ulong tim; + + tim = mktime (tmp->tm_year, tmp->tm_mon, tmp->tm_mday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + + immap->im_sitk.sitk_rtck = KAPWR_KEY; + immap->im_sit.sit_rtc = tim; } - } - else { - /* Otherwise, 0-23 hour format */ - tmp->tm_hour = (bcd2bin(spi_byte & 0x3F)); - } - soft_spi_read(); /* Read and discard Day of week */ - tmp->tm_mday = bcd2bin(soft_spi_read()); /* Read Day of the Month */ - tmp->tm_mon = bcd2bin(soft_spi_read()); /* Read Month */ + debug ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); +} - /* Read Year and convert to this century */ - tmp->tm_year = bcd2bin(soft_spi_read()) + 2000; +/* ------------------------------------------------------------------------- */ - /* Now we can disable the DS1306 RTC */ - immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; /* Disable DS1306 Chip */ - udelay(10); +/* Initialize Port B for software SPI */ +static void init_spi (void) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; - GregorianDay(tmp); /* Determine the day of week */ + /* Force output pins to begin at logic 0 */ + immap->im_cpm.cp_pbdat &= ~(PB_SPI_CE | PB_SPIMOSI | PB_SPISCK); - debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + /* Set these 3 signals as outputs */ + immap->im_cpm.cp_pbdir |= (PB_SPIMOSI | PB_SPI_CE | PB_SPISCK); + + immap->im_cpm.cp_pbdir &= ~PB_SPIMISO; /* Make MISO pin an input */ + udelay (10); } /* ------------------------------------------------------------------------- */ -/* set clock time in DS1306 RTC and in MPC8xx RTC */ -void rtc_set(struct rtc_time *tmp) +/* NOTE: soft_spi_send() assumes that the I/O lines are configured already */ +static void soft_spi_send (unsigned char n) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - - init_spi(); /* set port B for software SPI */ - - /* Now we can enable the DS1306 RTC */ - immap->im_cpm.cp_pbdat |= PB_SPI_CE; /* Enable DS1306 Chip */ - udelay(10); - - /* First disable write protect in the clock chip control register */ - soft_spi_send(0x8F); /* send address of the control register */ - soft_spi_send(0x00); /* send control register contents */ - - /* Now disable the DS1306 to terminate the write */ - immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; - udelay(10); - - /* Now enable the DS1306 to initiate a new write */ - immap->im_cpm.cp_pbdat |= PB_SPI_CE; - udelay(10); - - /* Next, send the address of the clock time write registers */ - soft_spi_send(0x80); /* send address of the first time register */ - - /* Use Burst Mode to send all of the time data to the clock */ - bin2bcd(tmp->tm_sec); - soft_spi_send(bin2bcd(tmp->tm_sec)); /* Send Seconds */ - soft_spi_send(bin2bcd(tmp->tm_min)); /* Send Minutes */ - soft_spi_send(bin2bcd(tmp->tm_hour)); /* Send Hour */ - soft_spi_send(bin2bcd(tmp->tm_wday)); /* Send Day of the Week */ - soft_spi_send(bin2bcd(tmp->tm_mday)); /* Send Day of Month */ - soft_spi_send(bin2bcd(tmp->tm_mon)); /* Send Month */ - soft_spi_send(bin2bcd(tmp->tm_year - 2000)); /* Send Year */ - - /* Now we can disable the Clock chip to terminate the burst write */ - immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; /* Disable DS1306 Chip */ - udelay(10); - - /* Now we can enable the Clock chip to initiate a new write */ - immap->im_cpm.cp_pbdat |= PB_SPI_CE; /* Enable DS1306 Chip */ - udelay(10); - - /* First we Enable write protect in the clock chip control register */ - soft_spi_send(0x8F); /* send address of the control register */ - soft_spi_send(0x40); /* send out Control Register contents */ - - /* Now disable the DS1306 */ - immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; /* Disable DS1306 Chip */ - udelay(10); - - /* Set standard MPC8xx clock to the same time so Linux will - * see the time even if it doesn't have a DS1306 clock driver. - * This helps with experimenting with standard kernels. - */ - { - ulong tim; - - tim = mktime(tmp->tm_year, tmp->tm_mon, tmp->tm_mday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); - - immap->im_sitk.sitk_rtck = KAPWR_KEY; - immap->im_sit.sit_rtc = tim; - } - - debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + volatile immap_t *immap = (immap_t *) CFG_IMMR; + unsigned char bitpos; /* bit position to receive */ + unsigned char i; /* Loop Control */ + + /* bit position to send, start with most significant bit */ + bitpos = 0x80; + + /* Send 8 bits to software SPI */ + for (i = 0; i < 8; i++) { /* Loop for 8 bits */ + immap->im_cpm.cp_pbdat |= PB_SPISCK; /* Raise SCK */ + + if (n & bitpos) + immap->im_cpm.cp_pbdat |= PB_SPIMOSI; /* Set MOSI to 1 */ + else + immap->im_cpm.cp_pbdat &= ~PB_SPIMOSI; /* Set MOSI to 0 */ + udelay (10); + + immap->im_cpm.cp_pbdat &= ~PB_SPISCK; /* Lower SCK */ + udelay (10); + + bitpos >>= 1; /* Shift for next bit position */ + } } /* ------------------------------------------------------------------------- */ -void rtc_reset(void) +/* NOTE: soft_spi_read() assumes that the I/O lines are configured already */ +static unsigned char soft_spi_read (void) { - return; /* nothing to do */ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + + unsigned char spi_byte = 0; /* Return value, assume success */ + unsigned char bitpos; /* bit position to receive */ + unsigned char i; /* Loop Control */ + + /* bit position to receive, start with most significant bit */ + bitpos = 0x80; + + /* Read 8 bits here */ + for (i = 0; i < 8; i++) { /* Do 8 bits in loop */ + immap->im_cpm.cp_pbdat |= PB_SPISCK; /* Raise SCK */ + udelay (10); + if (immap->im_cpm.cp_pbdat & PB_SPIMISO) /* Get a bit of data */ + spi_byte |= bitpos; /* Set data accordingly */ + immap->im_cpm.cp_pbdat &= ~PB_SPISCK; /* Lower SCK */ + udelay (10); + bitpos >>= 1; /* Shift for next bit position */ + } + + return spi_byte; /* Return the byte read */ } /* ------------------------------------------------------------------------- */ -static unsigned char bcd2bin(unsigned char n) +void rtc_reset (void) { - return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F)); + return; /* nothing to do */ +} + +#else /* not CONFIG_SXNI855T */ +/* ************************************************************************* */ + + + + + +/* read clock time from DS1306 and return it in *tmp */ +void rtc_get (struct rtc_time *tmp) +{ + unsigned char sec, min, hour, mday, wday, mon, year; + + sec = rtc_read (RTC_SECONDS); + min = rtc_read (RTC_MINUTES); + hour = rtc_read (RTC_HOURS); + mday = rtc_read (RTC_DATE_OF_MONTH); + wday = rtc_read (RTC_DAY_OF_WEEK); + mon = rtc_read (RTC_MONTH); + year = rtc_read (RTC_YEAR); + + debug ("Get RTC year: %02x mon: %02x mday: %02x wday: %02x " + "hr: %02x min: %02x sec: %02x\n", + year, mon, mday, wday, hour, min, sec); + debug ("Alarms[0]: wday: %02x hour: %02x min: %02x sec: %02x\n", + rtc_read (RTC_DAY_OF_WEEK_ALARM0), + rtc_read (RTC_HOURS_ALARM0), + rtc_read (RTC_MINUTES_ALARM0), rtc_read (RTC_SECONDS_ALARM0)); + debug ("Alarms[1]: wday: %02x hour: %02x min: %02x sec: %02x\n", + rtc_read (RTC_DAY_OF_WEEK_ALARM1), + rtc_read (RTC_HOURS_ALARM1), + rtc_read (RTC_MINUTES_ALARM1), rtc_read (RTC_SECONDS_ALARM1)); + + tmp->tm_sec = bcd2bin (sec & 0x7F); /* convert Seconds */ + tmp->tm_min = bcd2bin (min & 0x7F); /* convert Minutes */ + + /* convert Hours */ + tmp->tm_hour = (hour & 0x40) + ? ((hour & 0x20) /* 12 hour mode */ + ? bcd2bin (hour & 0x1F) + 11 /* PM */ + : bcd2bin (hour & 0x1F) - 1 /* AM */ + ) + : bcd2bin (hour & 0x3F); /* 24 hour mode */ + + tmp->tm_mday = bcd2bin (mday & 0x3F); /* convert Day of the Month */ + tmp->tm_mon = bcd2bin (mon & 0x1F); /* convert Month */ + tmp->tm_year = bcd2bin (year) + 2000; /* convert Year */ + tmp->tm_wday = bcd2bin (wday & 0x07) - 1; /* convert Day of the Week */ + tmp->tm_yday = 0; + tmp->tm_isdst = 0; + + debug ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); } /* ------------------------------------------------------------------------- */ -static unsigned int bin2bcd(unsigned int n) +/* set clock time from *tmp in DS1306 RTC */ +void rtc_set (struct rtc_time *tmp) { - return (((n / 10) << 4) | (n % 10)); + debug ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + + rtc_write (RTC_YEAR, bin2bcd (tmp->tm_year - 2000)); + rtc_write (RTC_MONTH, bin2bcd (tmp->tm_mon)); + rtc_write (RTC_DATE_OF_MONTH, bin2bcd (tmp->tm_mday)); + rtc_write (RTC_DAY_OF_WEEK, bin2bcd (tmp->tm_wday + 1)); + rtc_write (RTC_HOURS, bin2bcd (tmp->tm_hour)); + rtc_write (RTC_MINUTES, bin2bcd (tmp->tm_min)); + rtc_write (RTC_SECONDS, bin2bcd (tmp->tm_sec)); } /* ------------------------------------------------------------------------- */ -/* Initialize Port B for software SPI */ -static void init_spi(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; +/* reset the DS1306 */ +void rtc_reset (void) +{ + /* clear the control register */ + rtc_write (RTC_CONTROL, 0x00); /* 1st step: reset WP */ + rtc_write (RTC_CONTROL, 0x00); /* 2nd step: reset 1Hz, AIE1, AIE0 */ + + /* reset all alarms */ + rtc_write (RTC_SECONDS_ALARM0, 0x00); + rtc_write (RTC_SECONDS_ALARM1, 0x00); + rtc_write (RTC_MINUTES_ALARM0, 0x00); + rtc_write (RTC_MINUTES_ALARM1, 0x00); + rtc_write (RTC_HOURS_ALARM0, 0x00); + rtc_write (RTC_HOURS_ALARM1, 0x00); + rtc_write (RTC_DAY_OF_WEEK_ALARM0, 0x00); + rtc_write (RTC_DAY_OF_WEEK_ALARM1, 0x00); +} + +/* ------------------------------------------------------------------------- */ - /* Force output pins to begin at logic 0 */ - immap->im_cpm.cp_pbdat &= ~(PB_SPI_CE | PB_SPIMOSI | PB_SPISCK); +static unsigned char rtc_read (unsigned char reg) +{ + unsigned char dout[2]; /* SPI Output Data Bytes */ + unsigned char din[2]; /* SPI Input Data Bytes */ - /* Set these 3 signals as outputs */ - immap->im_cpm.cp_pbdir |= (PB_SPIMOSI | PB_SPI_CE | PB_SPISCK); + dout[0] = reg; - immap->im_cpm.cp_pbdir &= ~PB_SPIMISO; /* Make MISO pin an input */ - udelay(10); + if (spi_xfer (spi_chipsel[CFG_SPI_RTC_DEVID], 16, dout, din) != 0) { + return 0; + } else { + return din[1]; + } } /* ------------------------------------------------------------------------- */ -/* NOTE: soft_spi_send() assumes that the I/O lines are configured already */ -static void soft_spi_send(unsigned char n) +static void rtc_write (unsigned char reg, unsigned char val) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - unsigned char bitpos; /* bit position to receive */ - unsigned char i; /* Loop Control */ + unsigned char dout[2]; /* SPI Output Data Bytes */ + unsigned char din[2]; /* SPI Input Data Bytes */ - /* bit position to send, start with most significant bit */ - bitpos = 0x80; + dout[0] = 0x80 | reg; + dout[1] = val; - /* Send 8 bits to software SPI */ - for (i = 0; i < 8; i++) { /* Loop for 8 bits */ - immap->im_cpm.cp_pbdat |= PB_SPISCK; /* Raise SCK */ + spi_xfer (spi_chipsel[CFG_SPI_RTC_DEVID], 16, dout, din); +} - if (n & bitpos) - immap->im_cpm.cp_pbdat |= PB_SPIMOSI; /* Set MOSI to 1 */ - else - immap->im_cpm.cp_pbdat &= ~PB_SPIMOSI; /* Set MOSI to 0 */ - udelay(10); +#endif /* end of code exclusion (see #ifdef CONFIG_SXNI855T above) */ - immap->im_cpm.cp_pbdat &= ~PB_SPISCK; /* Lower SCK */ - udelay(10); +/* ------------------------------------------------------------------------- */ - bitpos >>= 1; /* Shift for next bit position */ - } +static unsigned char bcd2bin (unsigned char n) +{ + return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F)); } /* ------------------------------------------------------------------------- */ -/* NOTE: soft_spi_read() assumes that the I/O lines are configured already */ -static unsigned char soft_spi_read(void) +static unsigned int bin2bcd (unsigned int n) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - - unsigned char spi_byte = 0; /* Return value, assume success */ - unsigned char bitpos; /* bit position to receive */ - unsigned char i; /* Loop Control */ - - /* bit position to receive, start with most significant bit */ - bitpos = 0x80; - - /* Read 8 bits here */ - for (i = 0; i < 8; i++) { /* Do 8 bits in loop */ - immap->im_cpm.cp_pbdat |= PB_SPISCK; /* Raise SCK */ - udelay(10); - if (immap->im_cpm.cp_pbdat & PB_SPIMISO) /* Get a bit of data */ - spi_byte |= bitpos; /* Set data accordingly */ - immap->im_cpm.cp_pbdat &= ~PB_SPISCK; /* Lower SCK */ - udelay(10); - bitpos >>= 1; /* Shift for next bit position */ - } - - return spi_byte; /* Return the byte read */ + return (((n / 10) << 4) | (n % 10)); } - /* ------------------------------------------------------------------------- */ #endif |