diff options
| -rw-r--r-- | arch/riscv/Kconfig | 8 | ||||
| -rw-r--r-- | arch/riscv/cpu/andesv5/Kconfig (renamed from arch/riscv/cpu/ax25/Kconfig) | 0 | ||||
| -rw-r--r-- | arch/riscv/cpu/andesv5/Makefile (renamed from arch/riscv/cpu/ax25/Makefile) | 0 | ||||
| -rw-r--r-- | arch/riscv/cpu/andesv5/cache.c (renamed from arch/riscv/cpu/ax25/cache.c) | 0 | ||||
| -rw-r--r-- | arch/riscv/cpu/andesv5/cpu.c (renamed from arch/riscv/cpu/ax25/cpu.c) | 0 | ||||
| -rw-r--r-- | arch/riscv/cpu/andesv5/spl.c (renamed from arch/riscv/cpu/ax25/spl.c) | 0 | ||||
| -rw-r--r-- | arch/riscv/dts/Makefile | 2 | ||||
| -rw-r--r-- | board/AndesTech/ae350/Kconfig (renamed from board/AndesTech/ax25-ae350/Kconfig) | 8 | ||||
| -rw-r--r-- | board/AndesTech/ae350/MAINTAINERS (renamed from board/AndesTech/ax25-ae350/MAINTAINERS) | 6 | ||||
| -rw-r--r-- | board/AndesTech/ae350/Makefile (renamed from board/AndesTech/ax25-ae350/Makefile) | 2 | ||||
| -rw-r--r-- | board/AndesTech/ae350/ae350.c (renamed from board/AndesTech/ax25-ae350/ax25-ae350.c) | 0 | ||||
| -rw-r--r-- | configs/ae350_rv32_defconfig | 2 | ||||
| -rw-r--r-- | configs/ae350_rv32_spl_defconfig | 2 | ||||
| -rw-r--r-- | configs/ae350_rv32_spl_xip_defconfig | 2 | ||||
| -rw-r--r-- | configs/ae350_rv32_xip_defconfig | 2 | ||||
| -rw-r--r-- | configs/ae350_rv64_defconfig | 2 | ||||
| -rw-r--r-- | configs/ae350_rv64_spl_defconfig | 2 | ||||
| -rw-r--r-- | configs/ae350_rv64_spl_xip_defconfig | 2 | ||||
| -rw-r--r-- | configs/ae350_rv64_xip_defconfig | 2 | ||||
| -rw-r--r-- | doc/board/AndesTech/ae350.rst (renamed from doc/board/AndesTech/ax25-ae350.rst) | 16 | ||||
| -rw-r--r-- | doc/board/AndesTech/index.rst | 2 | ||||
| -rw-r--r-- | include/configs/ae350.h (renamed from include/configs/ax25-ae350.h) | 0 |
22 files changed, 30 insertions, 30 deletions
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index ebc4bef220..48ca4ff4c4 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -8,8 +8,8 @@ choice prompt "Target select" optional -config TARGET_AX25_AE350 - bool "Support ax25-ae350" +config TARGET_AE350 + bool "Support ae350" config TARGET_MICROCHIP_ICICLE bool "Support Microchip PolarFire-SoC Icicle Board" @@ -58,7 +58,7 @@ config SPL_SYS_DCACHE_OFF Do not enable data cache in SPL. # board-specific options below -source "board/AndesTech/ax25-ae350/Kconfig" +source "board/AndesTech/ae350/Kconfig" source "board/emulation/qemu-riscv/Kconfig" source "board/microchip/mpfs_icicle/Kconfig" source "board/sifive/unleashed/Kconfig" @@ -67,7 +67,7 @@ source "board/openpiton/riscv64/Kconfig" source "board/sipeed/maix/Kconfig" # platform-specific options below -source "arch/riscv/cpu/ax25/Kconfig" +source "arch/riscv/cpu/andesv5/Kconfig" source "arch/riscv/cpu/fu540/Kconfig" source "arch/riscv/cpu/fu740/Kconfig" source "arch/riscv/cpu/generic/Kconfig" diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/andesv5/Kconfig index 82bb5a2a53..82bb5a2a53 100644 --- a/arch/riscv/cpu/ax25/Kconfig +++ b/arch/riscv/cpu/andesv5/Kconfig diff --git a/arch/riscv/cpu/ax25/Makefile b/arch/riscv/cpu/andesv5/Makefile index 35a1a2fb83..35a1a2fb83 100644 --- a/arch/riscv/cpu/ax25/Makefile +++ b/arch/riscv/cpu/andesv5/Makefile diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/andesv5/cache.c index 40d77f671c..40d77f671c 100644 --- a/arch/riscv/cpu/ax25/cache.c +++ b/arch/riscv/cpu/andesv5/cache.c diff --git a/arch/riscv/cpu/ax25/cpu.c b/arch/riscv/cpu/andesv5/cpu.c index 06e379bcb1..06e379bcb1 100644 --- a/arch/riscv/cpu/ax25/cpu.c +++ b/arch/riscv/cpu/andesv5/cpu.c diff --git a/arch/riscv/cpu/ax25/spl.c b/arch/riscv/cpu/andesv5/spl.c index 413849043b..413849043b 100644 --- a/arch/riscv/cpu/ax25/spl.c +++ b/arch/riscv/cpu/andesv5/spl.c diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 5c15a0f303..c576c55767 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ -dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb +dtb-$(CONFIG_TARGET_AE350) += ae350_32.dtb ae350_64.dtb dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-kit.dtb dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb diff --git a/board/AndesTech/ax25-ae350/Kconfig b/board/AndesTech/ae350/Kconfig index 4bb33b0793..75815bf99a 100644 --- a/board/AndesTech/ax25-ae350/Kconfig +++ b/board/AndesTech/ae350/Kconfig @@ -1,10 +1,10 @@ -if TARGET_AX25_AE350 +if TARGET_AE350 config SYS_CPU - default "ax25" + default "andesv5" config SYS_BOARD - default "ax25-ae350" + default "ae350" config SYS_VENDOR default "AndesTech" @@ -13,7 +13,7 @@ config SYS_SOC default "ae350" config SYS_CONFIG_NAME - default "ax25-ae350" + default "ae350" config ENV_SIZE default 0x2000 if ENV_IS_IN_SPI_FLASH diff --git a/board/AndesTech/ax25-ae350/MAINTAINERS b/board/AndesTech/ae350/MAINTAINERS index eebee167c3..ead8e0e2af 100644 --- a/board/AndesTech/ax25-ae350/MAINTAINERS +++ b/board/AndesTech/ae350/MAINTAINERS @@ -1,8 +1,8 @@ -AX25-AE350 BOARD +AE350 BOARD M: Rick Chen <rick@andestech.com> S: Maintained -F: board/AndesTech/ax25-ae350/ -F: include/configs/ax25-ae350.h +F: board/AndesTech/ae350/ +F: include/configs/ae350.h F: configs/ae350_rv32_defconfig F: configs/ae350_rv64_defconfig F: configs/ae350_rv32_xip_defconfig diff --git a/board/AndesTech/ax25-ae350/Makefile b/board/AndesTech/ae350/Makefile index 0e4ba8d702..705ae43af5 100644 --- a/board/AndesTech/ax25-ae350/Makefile +++ b/board/AndesTech/ae350/Makefile @@ -3,4 +3,4 @@ # Copyright (C) 2017 Andes Technology Corporation. # Rick Chen, Andes Technology Corporation <rick@andestech.com> -obj-y := ax25-ae350.o +obj-y := ae350.o diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c b/board/AndesTech/ae350/ae350.c index 1c2288b6ce..1c2288b6ce 100644 --- a/board/AndesTech/ax25-ae350/ax25-ae350.c +++ b/board/AndesTech/ae350/ae350.c diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig index fd1bf5fa4f..953cd0700b 100644 --- a/configs/ae350_rv32_defconfig +++ b/configs/ae350_rv32_defconfig @@ -6,7 +6,7 @@ CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_32" CONFIG_SYS_PROMPT="RISC-V # " CONFIG_SYS_LOAD_ADDR=0x100000 -CONFIG_TARGET_AX25_AE350=y +CONFIG_TARGET_AE350=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffe80 diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig index 4d3623a894..d61f7f5d1d 100644 --- a/configs/ae350_rv32_spl_defconfig +++ b/configs/ae350_rv32_spl_defconfig @@ -8,7 +8,7 @@ CONFIG_SYS_PROMPT="RISC-V # " CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x100000 -CONFIG_TARGET_AX25_AE350=y +CONFIG_TARGET_AE350=y CONFIG_RISCV_SMODE=y # CONFIG_AVAILABLE_HARTS is not set CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/ae350_rv32_spl_xip_defconfig b/configs/ae350_rv32_spl_xip_defconfig index a076b77834..e59ba0c38a 100644 --- a/configs/ae350_rv32_spl_xip_defconfig +++ b/configs/ae350_rv32_spl_xip_defconfig @@ -9,7 +9,7 @@ CONFIG_SYS_PROMPT="RISC-V # " CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x100000 -CONFIG_TARGET_AX25_AE350=y +CONFIG_TARGET_AE350=y CONFIG_RISCV_SMODE=y CONFIG_SPL_XIP=y CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/ae350_rv32_xip_defconfig b/configs/ae350_rv32_xip_defconfig index da1bd2b10b..926632137d 100644 --- a/configs/ae350_rv32_xip_defconfig +++ b/configs/ae350_rv32_xip_defconfig @@ -6,7 +6,7 @@ CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_32" CONFIG_SYS_PROMPT="RISC-V # " CONFIG_SYS_LOAD_ADDR=0x100000 -CONFIG_TARGET_AX25_AE350=y +CONFIG_TARGET_AE350=y CONFIG_XIP=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig index 959258176a..3c18562ad4 100644 --- a/configs/ae350_rv64_defconfig +++ b/configs/ae350_rv64_defconfig @@ -6,7 +6,7 @@ CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_64" CONFIG_SYS_PROMPT="RISC-V # " CONFIG_SYS_LOAD_ADDR=0x100000 -CONFIG_TARGET_AX25_AE350=y +CONFIG_TARGET_AE350=y CONFIG_ARCH_RV64I=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y diff --git a/configs/ae350_rv64_spl_defconfig b/configs/ae350_rv64_spl_defconfig index 0217027e6d..cb69514a7e 100644 --- a/configs/ae350_rv64_spl_defconfig +++ b/configs/ae350_rv64_spl_defconfig @@ -8,7 +8,7 @@ CONFIG_SYS_PROMPT="RISC-V # " CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x100000 -CONFIG_TARGET_AX25_AE350=y +CONFIG_TARGET_AE350=y CONFIG_ARCH_RV64I=y CONFIG_RISCV_SMODE=y # CONFIG_AVAILABLE_HARTS is not set diff --git a/configs/ae350_rv64_spl_xip_defconfig b/configs/ae350_rv64_spl_xip_defconfig index 5a1fa8b6a1..e0773fa0aa 100644 --- a/configs/ae350_rv64_spl_xip_defconfig +++ b/configs/ae350_rv64_spl_xip_defconfig @@ -9,7 +9,7 @@ CONFIG_SYS_PROMPT="RISC-V # " CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x100000 -CONFIG_TARGET_AX25_AE350=y +CONFIG_TARGET_AE350=y CONFIG_ARCH_RV64I=y CONFIG_RISCV_SMODE=y CONFIG_SPL_XIP=y diff --git a/configs/ae350_rv64_xip_defconfig b/configs/ae350_rv64_xip_defconfig index c3fcbf3d28..0d467b9836 100644 --- a/configs/ae350_rv64_xip_defconfig +++ b/configs/ae350_rv64_xip_defconfig @@ -6,7 +6,7 @@ CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_64" CONFIG_SYS_PROMPT="RISC-V # " CONFIG_SYS_LOAD_ADDR=0x100000 -CONFIG_TARGET_AX25_AE350=y +CONFIG_TARGET_AE350=y CONFIG_ARCH_RV64I=y CONFIG_XIP=y CONFIG_DISTRO_DEFAULTS=y diff --git a/doc/board/AndesTech/ax25-ae350.rst b/doc/board/AndesTech/ae350.rst index b46f427f4b..42a2b4d0b5 100644 --- a/doc/board/AndesTech/ax25-ae350.rst +++ b/doc/board/AndesTech/ae350.rst @@ -1,20 +1,20 @@ .. SPDX-License-Identifier: GPL-2.0+ -AX25-AE350 -========== +AE350 +====== -AE350 is the mainline SoC produced by Andes Technology using AX25 CPU core -base on RISC-V architecture. +AE350 is the mainline SoC produced by Andes Technology using AndesV5 CPU core +based on RISC-V architecture. AE350 has integrated both AHB and APB bus and many periphals for application and product development. -AX25-AE350 is the SoC with AE350 hardcore CPU. +AndesV5 is Andes CPU IP family that adopts RISC-V architecture. -AX25 is Andes CPU IP to adopt RISC-V architecture. +AndesV5 family includes 25, 27, 45 series. -AX25 Features -------------- +25-Series Features +------------------ CPU Core - 5-stage in-order execution pipeline diff --git a/doc/board/AndesTech/index.rst b/doc/board/AndesTech/index.rst index d8f7d155fc..cacc5791a9 100644 --- a/doc/board/AndesTech/index.rst +++ b/doc/board/AndesTech/index.rst @@ -7,4 +7,4 @@ Andes Tech :maxdepth: 2 adp-ag101p - ax25-ae350 + ae350 diff --git a/include/configs/ax25-ae350.h b/include/configs/ae350.h index b566ecf296..b566ecf296 100644 --- a/include/configs/ax25-ae350.h +++ b/include/configs/ae350.h |