diff options
| -rw-r--r-- | drivers/clk/clk_stm32mp1.c | 21 |
1 files changed, 4 insertions, 17 deletions
diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c index 5806d48696..359c2b98aa 100644 --- a/drivers/clk/clk_stm32mp1.c +++ b/drivers/clk/clk_stm32mp1.c @@ -759,9 +759,6 @@ static ulong stm32mp1_clk_get_fixed(struct stm32mp1_clk_priv *priv, int idx) return 0; } - debug("%s: clk id %d = %x : %ld kHz\n", __func__, idx, - (u32)priv->osc[idx], priv->osc[idx] / 1000); - return priv->osc[idx]; } @@ -863,8 +860,6 @@ static ulong pll_get_fref_ck(struct stm32mp1_clk_priv *priv, src = selr & RCC_SELR_SRC_MASK; refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]); - debug("PLL%d : selr=%x refclk = %d kHz\n", - pll_id, selr, (u32)(refclk / 1000)); return refclk; } @@ -889,9 +884,6 @@ static ulong pll_get_fvco(struct stm32mp1_clk_priv *priv, divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT; divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK; - debug("PLL%d : cfgr1=%x fracr=%x DIVN=%d DIVM=%d\n", - pll_id, cfgr1, fracr, divn, divm); - refclk = pll_get_fref_ck(priv, pll_id); /* with FRACV : @@ -908,7 +900,6 @@ static ulong pll_get_fvco(struct stm32mp1_clk_priv *priv, } else { fvco = (ulong)(refclk * (divn + 1) / (divm + 1)); } - debug("PLL%d : %s = %ld\n", pll_id, __func__, fvco); return fvco; } @@ -921,17 +912,13 @@ static ulong stm32mp1_read_pll_freq(struct stm32mp1_clk_priv *priv, ulong dfout; u32 cfgr2; - debug("%s(%d, %d)\n", __func__, pll_id, div_id); if (div_id >= _DIV_NB) return 0; cfgr2 = readl(priv->base + pll[pll_id].pllxcfgr2); divy = (cfgr2 >> RCC_PLLNCFGR2_SHIFT(div_id)) & RCC_PLLNCFGR2_DIVX_MASK; - debug("PLL%d : cfgr2=%x DIVY=%d\n", pll_id, cfgr2, divy); - dfout = pll_get_fvco(priv, pll_id) / (divy + 1); - debug(" => dfout = %d kHz\n", (u32)(dfout / 1000)); return dfout; } @@ -1574,9 +1561,6 @@ static void stgen_config(struct stm32mp1_clk_priv *priv) /* need to update gd->arch.timer_rate_hz with new frequency */ timer_init(); - pr_debug("gd->arch.timer_rate_hz = %x\n", - (u32)gd->arch.timer_rate_hz); - pr_debug("Tick = %x\n", (u32)(get_ticks())); } } @@ -1882,7 +1866,6 @@ static int pll_set_output_rate(struct udevice *dev, if (div > 128) div = 128; - debug("fvco = %ld, clk_rate = %ld, div=%d\n", fvco, clk_rate, div); /* stop the requested output */ clrbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT); /* change divider */ @@ -1915,6 +1898,9 @@ static ulong stm32mp1_clk_set_rate(struct clk *clk, unsigned long clk_rate) } p = stm32mp1_clk_get_parent(priv, clk->id); +#ifdef DEBUG + debug("%s: parent = %d:%s\n", __func__, p, stm32mp1_clk_parent_name[p]); +#endif if (p < 0) return -EINVAL; @@ -1932,6 +1918,7 @@ static ulong stm32mp1_clk_set_rate(struct clk *clk, unsigned long clk_rate) return result; } #endif + case _PLL4_Q: /* for LTDC_PX and DSI_PX case */ return pll_set_output_rate(clk->dev, _PLL4, _DIV_Q, clk_rate); |