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-rw-r--r--drivers/crypto/fsl/Kconfig6
-rw-r--r--drivers/crypto/fsl/desc.h48
-rw-r--r--drivers/crypto/fsl/desc_constr.h29
-rw-r--r--drivers/crypto/fsl/fsl_hash.c7
-rw-r--r--drivers/crypto/fsl/jobdesc.c13
-rw-r--r--drivers/crypto/fsl/jr.c36
-rw-r--r--drivers/crypto/fsl/jr.h10
-rw-r--r--drivers/crypto/fsl/type.h16
8 files changed, 93 insertions, 72 deletions
diff --git a/drivers/crypto/fsl/Kconfig b/drivers/crypto/fsl/Kconfig
index 5ed6140da3..1f5dfb94bb 100644
--- a/drivers/crypto/fsl/Kconfig
+++ b/drivers/crypto/fsl/Kconfig
@@ -7,6 +7,12 @@ config FSL_CAAM
Module (CAAM), also known as the SEC version 4 (SEC4). The driver uses
Job Ring as interface to communicate with CAAM.
+config CAAM_64BIT
+ bool
+ default y if PHYS_64BIT && !ARCH_IMX8M
+ help
+ Select Crypto driver for 64 bits CAAM version
+
config SYS_FSL_HAS_SEC
bool
help
diff --git a/drivers/crypto/fsl/desc.h b/drivers/crypto/fsl/desc.h
index 9d1ae059a7..5705c4f944 100644
--- a/drivers/crypto/fsl/desc.h
+++ b/drivers/crypto/fsl/desc.h
@@ -11,6 +11,8 @@
#ifndef DESC_H
#define DESC_H
+#include "type.h"
+
#define KEY_BLOB_SIZE 32
#define MAC_SIZE 16
@@ -693,29 +695,29 @@
/* Structures for Protocol Data Blocks */
struct __packed pdb_ecdsa_verify {
uint32_t pdb_hdr;
- dma_addr_t dma_q; /* Pointer to q (elliptic curve) */
- dma_addr_t dma_r; /* Pointer to r (elliptic curve) */
- dma_addr_t dma_g_xy; /* Pointer to Gx,y (elliptic curve) */
- dma_addr_t dma_pkey; /* Pointer to Wx,y (public key) */
- dma_addr_t dma_hash; /* Pointer to hash input */
- dma_addr_t dma_c; /* Pointer to C_signature */
- dma_addr_t dma_d; /* Pointer to D_signature */
- dma_addr_t dma_buf; /* Pointer to 64-byte temp buffer */
- dma_addr_t dma_ab; /* Pointer to a,b (elliptic curve ) */
+ caam_dma_addr_t dma_q; /* Pointer to q (elliptic curve) */
+ caam_dma_addr_t dma_r; /* Pointer to r (elliptic curve) */
+ caam_dma_addr_t dma_g_xy; /* Pointer to Gx,y (elliptic curve) */
+ caam_dma_addr_t dma_pkey; /* Pointer to Wx,y (public key) */
+ caam_dma_addr_t dma_hash; /* Pointer to hash input */
+ caam_dma_addr_t dma_c; /* Pointer to C_signature */
+ caam_dma_addr_t dma_d; /* Pointer to D_signature */
+ caam_dma_addr_t dma_buf; /* Pointer to 64-byte temp buffer */
+ caam_dma_addr_t dma_ab; /* Pointer to a,b (elliptic curve ) */
uint32_t img_size; /* Length of Message */
};
struct __packed pdb_ecdsa_sign {
uint32_t pdb_hdr;
- dma_addr_t dma_q; /* Pointer to q (elliptic curve) */
- dma_addr_t dma_r; /* Pointer to r (elliptic curve) */
- dma_addr_t dma_g_xy; /* Pointer to Gx,y (elliptic curve) */
- dma_addr_t dma_pri_key; /* Pointer to S (Private key) */
- dma_addr_t dma_hash; /* Pointer to hash input */
- dma_addr_t dma_c; /* Pointer to C_signature */
- dma_addr_t dma_d; /* Pointer to D_signature */
- dma_addr_t dma_ab; /* Pointer to a,b (elliptic curve ) */
- dma_addr_t dma_u; /* Pointer to Per Message Random */
+ caam_dma_addr_t dma_q; /* Pointer to q (elliptic curve) */
+ caam_dma_addr_t dma_r; /* Pointer to r (elliptic curve) */
+ caam_dma_addr_t dma_g_xy; /* Pointer to Gx,y (elliptic curve) */
+ caam_dma_addr_t dma_pri_key; /* Pointer to S (Private key) */
+ caam_dma_addr_t dma_hash; /* Pointer to hash input */
+ caam_dma_addr_t dma_c; /* Pointer to C_signature */
+ caam_dma_addr_t dma_d; /* Pointer to D_signature */
+ caam_dma_addr_t dma_ab; /* Pointer to a,b (elliptic curve ) */
+ caam_dma_addr_t dma_u; /* Pointer to Per Message Random */
uint32_t img_size; /* Length of Message */
};
@@ -726,16 +728,16 @@ struct __packed pdb_ecdsa_sign {
struct __packed pdb_mp_pub_k {
uint32_t pdb_hdr;
#define PDB_MP_PUB_K_SGF_SHIFT 31
- dma_addr_t dma_pkey; /* Pointer to Wx,y (public key) */
+ caam_dma_addr_t dma_pkey; /* Pointer to Wx,y (public key) */
};
struct __packed pdb_mp_sign {
uint32_t pdb_hdr;
#define PDB_MP_SIGN_SGF_SHIFT 28
- dma_addr_t dma_addr_msg; /* Pointer to Message */
- dma_addr_t dma_addr_hash; /* Pointer to hash output */
- dma_addr_t dma_addr_c_sig; /* Pointer to C_signature */
- dma_addr_t dma_addr_d_sig; /* Pointer to D_signature */
+ caam_dma_addr_t dma_addr_msg; /* Pointer to Message */
+ caam_dma_addr_t dma_addr_hash; /* Pointer to hash output */
+ caam_dma_addr_t dma_addr_c_sig; /* Pointer to C_signature */
+ caam_dma_addr_t dma_addr_d_sig; /* Pointer to D_signature */
uint32_t img_size; /* Length of Message */
};
diff --git a/drivers/crypto/fsl/desc_constr.h b/drivers/crypto/fsl/desc_constr.h
index 9edb8dc64a..209557c4ff 100644
--- a/drivers/crypto/fsl/desc_constr.h
+++ b/drivers/crypto/fsl/desc_constr.h
@@ -3,7 +3,6 @@
* caam descriptor construction helper functions
*
* Copyright 2008-2014 Freescale Semiconductor, Inc.
- * Copyright 2018 NXP
*
* Based on desc_constr.h file in linux drivers/crypto/caam
*/
@@ -13,7 +12,7 @@
#define IMMEDIATE (1 << 23)
#define CAAM_CMD_SZ sizeof(u32)
-#define CAAM_PTR_SZ sizeof(u32)
+#define CAAM_PTR_SZ sizeof(caam_dma_addr_t)
#define CAAM_DESC_BYTES_MAX (CAAM_CMD_SZ * MAX_CAAM_DESCSIZE)
#define DESC_JOB_IO_LEN (CAAM_CMD_SZ * 5 + CAAM_PTR_SZ * 3)
@@ -36,7 +35,7 @@
LDST_SRCDST_WORD_DECOCTRL | \
(LDOFF_ENABLE_AUTO_NFIFO << LDST_OFFSET_SHIFT))
-#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M)
+#ifdef CONFIG_CAAM_64BIT
struct ptr_addr_t {
#ifdef CONFIG_SYS_FSL_SEC_LE
u32 low;
@@ -50,9 +49,9 @@ struct ptr_addr_t {
};
#endif
-static inline void pdb_add_ptr(u32 *offset, u32 ptr)
+static inline void pdb_add_ptr(caam_dma_addr_t *offset, caam_dma_addr_t ptr)
{
-#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M)
+#ifdef CONFIG_CAAM_64BIT
/* The Position of low and high part of 64 bit address
* will depend on the endianness of CAAM Block */
struct ptr_addr_t *ptr_addr = (struct ptr_addr_t *)offset;
@@ -103,11 +102,11 @@ static inline void init_job_desc_pdb(u32 *desc, u32 options, size_t pdb_bytes)
options);
}
-static inline void append_ptr(u32 *desc, uint32_t ptr)
+static inline void append_ptr(u32 *desc, caam_dma_addr_t ptr)
{
- u32 *offset = (u32 *)desc_end(desc);
+ caam_dma_addr_t *offset = (caam_dma_addr_t *)desc_end(desc);
-#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M)
+#ifdef CONFIG_CAAM_64BIT
/* The Position of low and high part of 64 bit address
* will depend on the endianness of CAAM Block */
struct ptr_addr_t *ptr_addr = (struct ptr_addr_t *)offset;
@@ -160,7 +159,7 @@ static inline u32 *write_cmd(u32 *desc, u32 command)
return desc + 1;
}
-static inline void append_cmd_ptr(u32 *desc, uint32_t ptr, int len,
+static inline void append_cmd_ptr(u32 *desc, caam_dma_addr_t ptr, int len,
u32 command)
{
append_cmd(desc, command | len);
@@ -168,7 +167,7 @@ static inline void append_cmd_ptr(u32 *desc, uint32_t ptr, int len,
}
/* Write length after pointer, rather than inside command */
-static inline void append_cmd_ptr_extlen(u32 *desc, uint32_t ptr,
+static inline void append_cmd_ptr_extlen(u32 *desc, caam_dma_addr_t ptr,
unsigned int len, u32 command)
{
append_cmd(desc, command);
@@ -226,7 +225,7 @@ APPEND_CMD_LEN(seq_fifo_load, SEQ_FIFO_LOAD)
APPEND_CMD_LEN(seq_fifo_store, SEQ_FIFO_STORE)
#define APPEND_CMD_PTR(cmd, op) \
-static inline void append_##cmd(u32 *desc, uint32_t ptr, unsigned int len, \
+static inline void append_##cmd(u32 *desc, caam_dma_addr_t ptr, unsigned int len, \
u32 options) \
{ \
PRINT_POS; \
@@ -237,7 +236,7 @@ APPEND_CMD_PTR(load, LOAD)
APPEND_CMD_PTR(fifo_load, FIFO_LOAD)
APPEND_CMD_PTR(fifo_store, FIFO_STORE)
-static inline void append_store(u32 *desc, uint32_t ptr, unsigned int len,
+static inline void append_store(u32 *desc, caam_dma_addr_t ptr, unsigned int len,
u32 options)
{
u32 cmd_src;
@@ -255,7 +254,7 @@ static inline void append_store(u32 *desc, uint32_t ptr, unsigned int len,
}
#define APPEND_SEQ_PTR_INTLEN(cmd, op) \
-static inline void append_seq_##cmd##_ptr_intlen(u32 *desc, uint32_t ptr, \
+static inline void append_seq_##cmd##_ptr_intlen(u32 *desc, caam_dma_addr_t ptr, \
unsigned int len, \
u32 options) \
{ \
@@ -279,7 +278,7 @@ APPEND_CMD_PTR_TO_IMM(load, LOAD);
APPEND_CMD_PTR_TO_IMM(fifo_load, FIFO_LOAD);
#define APPEND_CMD_PTR_EXTLEN(cmd, op) \
-static inline void append_##cmd##_extlen(u32 *desc, uint32_t ptr, \
+static inline void append_##cmd##_extlen(u32 *desc, caam_dma_addr_t ptr, \
unsigned int len, u32 options) \
{ \
PRINT_POS; \
@@ -293,7 +292,7 @@ APPEND_CMD_PTR_EXTLEN(seq_out_ptr, SEQ_OUT_PTR)
* the size of its type
*/
#define APPEND_CMD_PTR_LEN(cmd, op, type) \
-static inline void append_##cmd(u32 *desc, uint32_t ptr, \
+static inline void append_##cmd(u32 *desc, caam_dma_addr_t ptr, \
type len, u32 options) \
{ \
PRINT_POS; \
diff --git a/drivers/crypto/fsl/fsl_hash.c b/drivers/crypto/fsl/fsl_hash.c
index 75500a621f..8b5c26db07 100644
--- a/drivers/crypto/fsl/fsl_hash.c
+++ b/drivers/crypto/fsl/fsl_hash.c
@@ -1,7 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2018 NXP
*
*/
@@ -88,7 +87,7 @@ static int caam_hash_update(void *hash_ctx, const void *buf,
enum caam_hash_algos caam_algo)
{
uint32_t final;
- phys_addr_t addr = virt_to_phys((void *)buf);
+ caam_dma_addr_t addr = virt_to_phys((void *)buf);
struct sha_ctx *ctx = hash_ctx;
if (ctx->sg_num >= MAX_SG_32) {
@@ -96,12 +95,12 @@ static int caam_hash_update(void *hash_ctx, const void *buf,
return -EINVAL;
}
-#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M)
+#ifdef CONFIG_CAAM_64BIT
sec_out32(&ctx->sg_tbl[ctx->sg_num].addr_hi, (uint32_t)(addr >> 32));
#else
sec_out32(&ctx->sg_tbl[ctx->sg_num].addr_hi, 0x0);
#endif
- sec_out32(&ctx->sg_tbl[ctx->sg_num].addr_lo, (uint32_t)addr);
+ sec_out32(&ctx->sg_tbl[ctx->sg_num].addr_lo, (caam_dma_addr_t)addr);
sec_out32(&ctx->sg_tbl[ctx->sg_num].len_flag,
(size & SG_ENTRY_LENGTH_MASK));
diff --git a/drivers/crypto/fsl/jobdesc.c b/drivers/crypto/fsl/jobdesc.c
index cd9d064657..d235415531 100644
--- a/drivers/crypto/fsl/jobdesc.c
+++ b/drivers/crypto/fsl/jobdesc.c
@@ -165,10 +165,9 @@ int inline_cnstr_jobdesc_blob_dek(uint32_t *desc, const uint8_t *plain_txt,
append_u32(desc, aad_w2);
- append_cmd_ptr(desc, (uint32_t)SEC_MEM_PAGE1, in_sz, CMD_SEQ_IN_PTR);
+ append_cmd_ptr(desc, (caam_dma_addr_t)SEC_MEM_PAGE1, in_sz, CMD_SEQ_IN_PTR);
- append_cmd_ptr(desc, (uint32_t)((ulong)dek_blob + 8),
- out_sz, CMD_SEQ_OUT_PTR);
+ append_cmd_ptr(desc, (caam_dma_addr_t)(ulong)(dek_blob + 8), out_sz, CMD_SEQ_OUT_PTR);
append_operation(desc, OP_TYPE_ENCAP_PROTOCOL | OP_PCLID_BLOB |
OP_PCLID_SECMEM);
@@ -184,7 +183,7 @@ void inline_cnstr_jobdesc_hash(uint32_t *desc,
/* SHA 256 , output is of length 32 words */
uint32_t storelen = alg_size;
u32 options;
- u32 dma_addr_in, dma_addr_out;
+ caam_dma_addr_t dma_addr_in, dma_addr_out;
dma_addr_in = virt_to_phys((void *)msg);
dma_addr_out = virt_to_phys((void *)digest);
@@ -213,7 +212,7 @@ void inline_cnstr_jobdesc_blob_encap(uint32_t *desc, uint8_t *key_idnfr,
uint8_t *plain_txt, uint8_t *enc_blob,
uint32_t in_sz)
{
- u32 dma_addr_key_idnfr, dma_addr_in, dma_addr_out;
+ caam_dma_addr_t dma_addr_key_idnfr, dma_addr_in, dma_addr_out;
uint32_t key_sz = KEY_IDNFR_SZ_BYTES;
/* output blob will have 32 bytes key blob in beginning and
* 16 byte HMAC identifier at end of data blob */
@@ -238,7 +237,7 @@ void inline_cnstr_jobdesc_blob_decap(uint32_t *desc, uint8_t *key_idnfr,
uint8_t *enc_blob, uint8_t *plain_txt,
uint32_t out_sz)
{
- u32 dma_addr_key_idnfr, dma_addr_in, dma_addr_out;
+ caam_dma_addr_t dma_addr_key_idnfr, dma_addr_in, dma_addr_out;
uint32_t key_sz = KEY_IDNFR_SZ_BYTES;
uint32_t in_sz = out_sz + KEY_BLOB_SIZE + MAC_SIZE;
@@ -314,7 +313,7 @@ void inline_cnstr_jobdesc_pkha_rsaexp(uint32_t *desc,
struct pk_in_params *pkin, uint8_t *out,
uint32_t out_siz)
{
- u32 dma_addr_e, dma_addr_a, dma_addr_n, dma_addr_out;
+ caam_dma_addr_t dma_addr_e, dma_addr_a, dma_addr_n, dma_addr_out;
dma_addr_e = virt_to_phys((void *)pkin->e);
dma_addr_a = virt_to_phys((void *)pkin->a);
diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
index 060a012eb2..22b649219e 100644
--- a/drivers/crypto/fsl/jr.c
+++ b/drivers/crypto/fsl/jr.c
@@ -84,16 +84,16 @@ static void jr_initregs(uint8_t sec_idx)
{
struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
struct jobring *jr = &jr0[sec_idx];
- phys_addr_t ip_base = virt_to_phys((void *)jr->input_ring);
- phys_addr_t op_base = virt_to_phys((void *)jr->output_ring);
+ caam_dma_addr_t ip_base = virt_to_phys((void *)jr->input_ring);
+ caam_dma_addr_t op_base = virt_to_phys((void *)jr->output_ring);
-#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M)
+#ifdef CONFIG_CAAM_64BIT
sec_out32(&regs->irba_h, ip_base >> 32);
#else
sec_out32(&regs->irba_h, 0x0);
#endif
sec_out32(&regs->irba_l, (uint32_t)ip_base);
-#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M)
+#ifdef CONFIG_CAAM_64BIT
sec_out32(&regs->orba_h, op_base >> 32);
#else
sec_out32(&regs->orba_h, 0x0);
@@ -119,8 +119,8 @@ static int jr_init(uint8_t sec_idx)
jr->liodn = DEFAULT_JR_LIODN;
#endif
jr->size = JR_SIZE;
- jr->input_ring = (uint32_t *)memalign(ARCH_DMA_MINALIGN,
- JR_SIZE * sizeof(dma_addr_t));
+ jr->input_ring = (caam_dma_addr_t *)memalign(ARCH_DMA_MINALIGN,
+ JR_SIZE * sizeof(caam_dma_addr_t));
if (!jr->input_ring)
return -1;
@@ -131,7 +131,7 @@ static int jr_init(uint8_t sec_idx)
if (!jr->output_ring)
return -1;
- memset(jr->input_ring, 0, JR_SIZE * sizeof(dma_addr_t));
+ memset(jr->input_ring, 0, JR_SIZE * sizeof(caam_dma_addr_t));
memset(jr->output_ring, 0, jr->op_size);
start_jr0(sec_idx);
@@ -150,7 +150,7 @@ static int jr_sw_cleanup(uint8_t sec_idx)
jr->read_idx = 0;
jr->write_idx = 0;
memset(jr->info, 0, sizeof(jr->info));
- memset(jr->input_ring, 0, jr->size * sizeof(dma_addr_t));
+ memset(jr->input_ring, 0, jr->size * sizeof(caam_dma_addr_t));
memset(jr->output_ring, 0, jr->size * sizeof(struct op_ring));
return 0;
@@ -196,7 +196,7 @@ static int jr_enqueue(uint32_t *desc_addr,
uint32_t desc_word;
int length = desc_len(desc_addr);
int i;
-#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M)
+#ifdef CONFIG_CAAM_64BIT
uint32_t *addr_hi, *addr_lo;
#endif
@@ -210,7 +210,7 @@ static int jr_enqueue(uint32_t *desc_addr,
sec_out32((uint32_t *)&desc_addr[i], desc_word);
}
- phys_addr_t desc_phys_addr = virt_to_phys(desc_addr);
+ caam_dma_addr_t desc_phys_addr = virt_to_phys(desc_addr);
jr->info[head].desc_phys_addr = desc_phys_addr;
jr->info[head].callback = (void *)callback;
@@ -223,7 +223,7 @@ static int jr_enqueue(uint32_t *desc_addr,
sizeof(struct jr_info), ARCH_DMA_MINALIGN);
flush_dcache_range(start, end);
-#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M)
+#ifdef CONFIG_CAAM_64BIT
/* Write the 64 bit Descriptor address on Input Ring.
* The 32 bit hign and low part of the address will
* depend on endianness of SEC block.
@@ -242,11 +242,11 @@ static int jr_enqueue(uint32_t *desc_addr,
#else
/* Write the 32 bit Descriptor address on Input Ring. */
sec_out32(&jr->input_ring[head], desc_phys_addr);
-#endif /* ifdef CONFIG_PHYS_64BIT */
+#endif /* ifdef CONFIG_CAAM_64BIT */
start = (unsigned long)&jr->input_ring[head] & ~(ARCH_DMA_MINALIGN - 1);
end = ALIGN((unsigned long)&jr->input_ring[head] +
- sizeof(dma_addr_t), ARCH_DMA_MINALIGN);
+ sizeof(caam_dma_addr_t), ARCH_DMA_MINALIGN);
flush_dcache_range(start, end);
jr->head = (head + 1) & (jr->size - 1);
@@ -272,7 +272,7 @@ static int jr_dequeue(int sec_idx)
int idx, i, found;
void (*callback)(uint32_t status, void *arg);
void *arg = NULL;
-#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M)
+#ifdef CONFIG_CAAM_64BIT
uint32_t *addr_hi, *addr_lo;
#else
uint32_t *addr;
@@ -283,8 +283,8 @@ static int jr_dequeue(int sec_idx)
found = 0;
- phys_addr_t op_desc;
- #if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M)
+ caam_dma_addr_t op_desc;
+ #ifdef CONFIG_CAAM_64BIT
/* Read the 64 bit Descriptor address from Output Ring.
* The 32 bit hign and low part of the address will
* depend on endianness of SEC block.
@@ -304,7 +304,7 @@ static int jr_dequeue(int sec_idx)
/* Read the 32 bit Descriptor address from Output Ring. */
addr = (uint32_t *)&jr->output_ring[jr->tail].desc;
op_desc = sec_in32(addr);
- #endif /* ifdef CONFIG_PHYS_64BIT */
+ #endif /* ifdef CONFIG_CAAM_64BIT */
uint32_t status = sec_in32(&jr->output_ring[jr->tail].status);
@@ -678,7 +678,7 @@ int sec_init_idx(uint8_t sec_idx)
mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0x2 << MCFGR_AWCACHE_SHIFT);
#endif
-#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M)
+#ifdef CONFIG_CAAM_64BIT
mcr |= (1 << MCFGR_PS_SHIFT);
#endif
sec_out32(&sec->mcfgr, mcr);
diff --git a/drivers/crypto/fsl/jr.h b/drivers/crypto/fsl/jr.h
index 92566dd2d6..1047aa772c 100644
--- a/drivers/crypto/fsl/jr.h
+++ b/drivers/crypto/fsl/jr.h
@@ -1,7 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2008-2014 Freescale Semiconductor, Inc.
- * Copyright 2018 NXP
*
*/
@@ -9,6 +8,7 @@
#define __JR_H
#include <linux/compiler.h>
+#include "type.h"
#define JR_SIZE 4
/* Timeout currently defined as 10 sec */
@@ -42,13 +42,13 @@
#define RNG4_MAX_HANDLES 2
struct op_ring {
- u32 desc;
- u32 status;
+ caam_dma_addr_t desc;
+ uint32_t status;
} __packed;
struct jr_info {
void (*callback)(uint32_t status, void *arg);
- phys_addr_t desc_phys_addr;
+ caam_dma_addr_t desc_phys_addr;
uint32_t desc_len;
uint32_t op_done;
void *arg;
@@ -84,7 +84,7 @@ struct jobring {
* by SEC
*/
/*Circular Ring of i/p descriptors */
- u32 *input_ring;
+ caam_dma_addr_t *input_ring;
/* Circular Ring of o/p descriptors */
/* Circula Ring containing info regarding descriptors in i/p
* and o/p ring
diff --git a/drivers/crypto/fsl/type.h b/drivers/crypto/fsl/type.h
new file mode 100644
index 0000000000..b7031a60fd
--- /dev/null
+++ b/drivers/crypto/fsl/type.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 NXP
+ *
+ */
+
+#ifndef CRYPTO_FSL_TYPE_H
+#define CRYPTO_FSL_TYPE_H
+
+#ifdef CONFIG_CAAM_64BIT
+typedef unsigned long long caam_dma_addr_t;
+#else
+typedef u32 caam_dma_addr_t;
+#endif
+
+#endif
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-24 05:47:07 +0000