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| author | Simon Glass <sjg@chromium.org> | 2015-07-06 12:54:31 -0600 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2015-07-21 17:39:32 -0600 |
| commit | 64ce0cad9e04aab19eb4c3f61333b203548281a7 (patch) | |
| tree | 34d947b79671ef3f7419d37dba7ea9c84093a66e /test | |
| parent | 201c29a2d6fe5d50bc731e51fd758b3ae1e028d6 (diff) | |
| download | u-boot-64ce0cad9e04aab19eb4c3f61333b203548281a7.tar.gz u-boot-64ce0cad9e04aab19eb4c3f61333b203548281a7.tar.bz2 u-boot-64ce0cad9e04aab19eb4c3f61333b203548281a7.zip | |
dm: test: Add a test for the ram uclass
Add a test to confirm that we can probe this device and get information on
the available RAM.
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'test')
| -rw-r--r-- | test/dm/Makefile | 1 | ||||
| -rw-r--r-- | test/dm/ram.c | 28 |
2 files changed, 29 insertions, 0 deletions
diff --git a/test/dm/Makefile b/test/dm/Makefile index d28a22f018..f6a955cfaf 100644 --- a/test/dm/Makefile +++ b/test/dm/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_DM_ETH) += eth.o obj-$(CONFIG_DM_GPIO) += gpio.o obj-$(CONFIG_DM_I2C) += i2c.o obj-$(CONFIG_DM_PCI) += pci.o +obj-$(CONFIG_RAM) += ram.o obj-$(CONFIG_RESET) += reset.o obj-$(CONFIG_DM_RTC) += rtc.o obj-$(CONFIG_DM_SPI_FLASH) += sf.o diff --git a/test/dm/ram.c b/test/dm/ram.c new file mode 100644 index 0000000000..3a7c5fffdd --- /dev/null +++ b/test/dm/ram.c @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <ram.h> +#include <dm/test.h> +#include <test/ut.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* Basic test of the ram uclass */ +static int dm_test_ram_base(struct unit_test_state *uts) +{ + struct udevice *dev; + struct ram_info info; + + ut_assertok(uclass_get_device(UCLASS_RAM, 0, &dev)); + ut_assertok(ram_get_info(dev, &info)); + ut_asserteq(0, info.base); + ut_asserteq(gd->ram_size, info.size); + + return 0; +} +DM_TEST(dm_test_ram_base, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); |