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| author | Marek Vasut <marek.vasut+renesas@mailbox.org> | 2024-10-05 19:45:02 +0200 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2024-10-05 13:15:22 -0600 |
| commit | dd4d130c8eb8fe3deb89dc6ec22bce4c641062b4 (patch) | |
| tree | 5aba573d6bbdf5dc1a874ee4e9e8d8228ffaf965 /scripts/dtc/update-dtc-source.sh | |
| parent | af69289d61876d8e62449ee2da2dc6683bcb8198 (diff) | |
| download | u-boot-dd4d130c8eb8fe3deb89dc6ec22bce4c641062b4.tar.gz u-boot-dd4d130c8eb8fe3deb89dc6ec22bce4c641062b4.tar.bz2 u-boot-dd4d130c8eb8fe3deb89dc6ec22bce4c641062b4.zip | |
clk: renesas: rcar-gen3: Fix SSCG caching replacement with MDSEL/PE caching
The SSCG is active with MDSEL[12] is not set. Previous commit
99c7e031196d ("clk: renesas: rcar-gen3: Replace SSCG caching
with MDSEL/PE caching") inverted the conditional assignment
of priv->sscg = !(cpg_mode & BIT(12)) during conversion from
(priv->sscg ? 16 : 0) to priv->cpg_mode & BIT(core->offset) ? 16 : 0;
Invert the assignment back to the correct state.
This fixes R8A77980, R8A77990, R8A77995 and R8A774C0.
Fixes: 99c7e031196d ("clk: renesas: rcar-gen3: Replace SSCG caching with MDSEL/PE caching")
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Diffstat (limited to 'scripts/dtc/update-dtc-source.sh')
0 files changed, 0 insertions, 0 deletions