powerpc: remove 4xx support

There was for long time no activity in the 4xx area.
We need to go further and convert to Kconfig, but it
turned out, nobody is interested anymore in 4xx,
so remove it.

Signed-off-by: Heiko Schocher <hs@denx.de>

41 files changed, 1 insertions, 11085 deletions

diff --git a/include/asm-generic/u-boot.h b/include/asm-generic/u-boot.h
index 95930ad20e..b8f9c7aedb 100644
--- a/include/asm-generic/u-boot.h
+++ b/include/asm-generic/u-boot.h
@@ -71,19 +71,6 @@ typedef struct bd_info {
 	unsigned long bi_vcofreq;	/* vco Freq in MHz */
 	unsigned long bi_flbfreq;	/* Flexbus Freq in MHz */
 #endif
-#if defined(CONFIG_405)   || \
-		defined(CONFIG_405GP) || \
-		defined(CONFIG_405EP) || \
-		defined(CONFIG_405EZ) || \
-		defined(CONFIG_405EX) || \
-		defined(CONFIG_440)
-	unsigned char	bi_s_version[4];	/* Version of this structure */
-	unsigned char	bi_r_version[32];	/* Version of the ROM (AMCC) */
-	unsigned int	bi_procfreq;	/* CPU (Internal) Freq, in Hz */
-	unsigned int	bi_plb_busfreq;	/* PLB Bus speed, in Hz */
-	unsigned int	bi_pci_busfreq;	/* PCI Bus speed, in Hz */
-	unsigned char	bi_pci_enetaddr[6];	/* PCI Ethernet MAC address */
-#endif
 
 #ifdef CONFIG_HAS_ETH1
 	unsigned char   bi_enet1addr[6];	/* OLD: see README.enetaddr */
@@ -101,27 +88,6 @@ typedef struct bd_info {
 	unsigned char   bi_enet5addr[6];	/* OLD: see README.enetaddr */
 #endif
 
-#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \
-		defined(CONFIG_405EZ) || defined(CONFIG_440GX) || \
-		defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
-		defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
-		defined(CONFIG_460EX) || defined(CONFIG_460GT)
-	unsigned int	bi_opbfreq;		/* OPB clock in Hz */
-	int		bi_iic_fast[2];		/* Use fast i2c mode */
-#endif
-#if defined(CONFIG_4xx)
-#if defined(CONFIG_440GX) || \
-		defined(CONFIG_460EX) || defined(CONFIG_460GT)
-	int		bi_phynum[4];           /* Determines phy mapping */
-	int		bi_phymode[4];          /* Determines phy mode */
-#elif defined(CONFIG_405EP) || defined(CONFIG_405EX) || defined(CONFIG_440)
-	int		bi_phynum[2];           /* Determines phy mapping */
-	int		bi_phymode[2];          /* Determines phy mode */
-#else
-	int		bi_phynum[1];           /* Determines phy mapping */
-	int		bi_phymode[1];          /* Determines phy mode */
-#endif
-#endif /* defined(CONFIG_4xx) */
 	ulong	        bi_arch_number;	/* unique id for this board */
 	ulong	        bi_boot_params;	/* where this board expects params */
 #ifdef CONFIG_NR_DRAM_BANKS
diff --git a/include/bedbug/regs.h b/include/bedbug/regs.h
index eb746912bf..304a336cc2 100644
--- a/include/bedbug/regs.h
+++ b/include/bedbug/regs.h
@@ -152,12 +152,10 @@
 #define DBSR_IA3	0x00200000	/* Instr Address Compare 3 Event */
 #define DBSR_IA4	0x00100000	/* Instr Address Compare 4 Event */
 #endif
-#ifndef CONFIG_440
 #define DBSR_IA1	0x04000000	/* Instr Address Compare 1 Event */
 #define DBSR_IA2	0x02000000	/* Instr Address Compare 2 Event */
 #define DBSR_IA3	0x00080000	/* Instr Address Compare 3 Event */
 #define DBSR_IA4	0x00040000	/* Instr Address Compare 4 Event */
-#endif
 
 struct spr_info {
   int  spr_val;
diff --git a/include/configs/CPCI2DP.h b/include/configs/CPCI2DP.h
deleted file mode 100644
index 6d2919ff55..0000000000
--- a/include/configs/CPCI2DP.h
+++ /dev/null
@@ -1,224 +0,0 @@
-/*
- * (C) Copyright 2005
- * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
-
-#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
-
-#define CONFIG_SYS_CLK_FREQ	33330000 /* external frequency to pll	*/
-
-#undef	CONFIG_BOOTARGS
-#undef	CONFIG_BOOTCOMMAND
-
-#define CONFIG_PREBOOT                  /* enable preboot variable      */
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_PHY_ADDR		0	/* PHY address			*/
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_PCI
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
-
-#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
-
-#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#define CONFIG_CONS_INDEX	2	/* Use UART1			*/
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
-
-#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
-#define CONFIG_SYS_BASE_BAUD	    691200
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE	\
-	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
-	 57600, 115200, 230400, 460800, 921600 }
-
-#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
-#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
-
-#define CONFIG_SYS_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
-#define PCI_HOST_FORCE  1               /* configure as pci host        */
-#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
-
-#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
-#define CONFIG_PCI_HOST	PCI_HOST_AUTO   /* select pci host function     */
-					/* resource configuration       */
-
-#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
-
-#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
-
-#define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x040b  /* PCI Device ID: CPCI-2DP      */
-#define CONFIG_SYS_PCI_CLASSCODE       0x0280	/* PCI Class Code: Network/Other*/
-
-#define CONFIG_SYS_PCI_PTM1LA  (bd->bi_memstart) /* point to sdram               */
-#define CONFIG_SYS_PCI_PTM1MS  (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
-#define CONFIG_SYS_PCI_PTM2LA	0xef000000	/* point to internal regs + PB0/1 */
-#define CONFIG_SYS_PCI_PTM2MS  0xff000001      /* 16MB, enable                  */
-#define CONFIG_SYS_PCI_PTM2PCI 0x00000000      /* Host: use this pci address   */
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_FLASH_BASE		0xFFFC0000
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
-#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
-#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
-#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
-
-#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
-#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
-#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-
-#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
-#define CONFIG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
-#define CONFIG_ENV_SIZE		0x400	/* 1024 bytes may be used for env vars */
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC16) for environment
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
-					/* 16 byte page write mode using*/
-					/* last 4 bits of the address	*/
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-
-#define CONFIG_SYS_EEPROM_WREN         1
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-#define FLASH_BASE0_PRELIM	0xFFE00000	/* FLASH bank #0	*/
-#define FLASH_BASE1_PRELIM	0               /* FLASH bank #1	*/
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (Flash Bank 0) initialization					*/
-#define CONFIG_SYS_EBC_PB0AP		0x92015480
-#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 2 (PB0) initialization					*/
-#define CONFIG_SYS_EBC_PB2AP		0x03004580  /* TWT=6,WBN=1,TH=2,RE=1,SOR=1 */
-#define CONFIG_SYS_EBC_PB2CR		0xEF018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
-
-/* Memory Bank 3 (PB1) initialization				*/
-#define CONFIG_SYS_EBC_PB3AP		0x03004580  /* TWT=6,WBN=1,TH=2,RE=1,SOR=1 */
-#define CONFIG_SYS_EBC_PB3CR		0xEF118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in data cache)
- */
-#define CONFIG_SYS_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */
-
-#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
-#define CONFIG_SYS_INIT_RAM_SIZE	0x2000	/* Size of used area in RAM	       */
-#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * GPIO definitions
- */
-#define CONFIG_SYS_EEPROM_WP		(0x80000000 >> 13)   /* GPIO13 */
-#define CONFIG_SYS_SELF_RST		(0x80000000 >> 14)   /* GPIO14 */
-#define CONFIG_SYS_PB_LED		(0x80000000 >> 16)   /* GPIO16 */
-#define CONFIG_SYS_INTA_FAKE		(0x80000000 >> 23)   /* GPIO23 */
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h
deleted file mode 100644
index c66b26ff82..0000000000
--- a/include/configs/CPCI4052.h
+++ /dev/null
@@ -1,332 +0,0 @@
-/*
- * (C) Copyright 2001-2004
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_CPCI405		1	/* ...on a CPCI405 board	*/
-#define CONFIG_CPCI405_VER2	1	/* ...version 2			*/
-#undef  CONFIG_CPCI405_6U               /* enable this for 6U boards    */
-
-#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
-
-#define CONFIG_MISC_INIT_R	 1	/* call misc_init_r()		*/
-
-#define CONFIG_SYS_CLK_FREQ	33330000 /* external frequency to pll	*/
-
-#undef	CONFIG_BOOTARGS
-#undef	CONFIG_BOOTCOMMAND
-
-#define CONFIG_PREBOOT                  /* enable preboot variable      */
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_PHY_ADDR		0	/* PHY address			*/
-#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
-#define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
-
-#undef  CONFIG_HAS_ETH1
-
-#define CONFIG_RTC_M48T35A	1		/* ST Electronics M48 timekeeper */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_PCI
-
-#define CONFIG_SUPPORT_VFAT
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
-
-/*
- * Miscellaneous configurable options
- */
-#undef CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
-
-#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
-
-#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
-
-#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
-#define CONFIG_SYS_BASE_BAUD	    691200
-
-#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
-#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
-
-#define CONFIG_CMDLINE_EDITING		/* add command line history	*/
-
-#define CONFIG_SYS_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
-#define PCI_HOST_FORCE  1               /* configure as pci host        */
-#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
-
-#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
-#define CONFIG_PCI_HOST	PCI_HOST_AUTO   /* select pci host function     */
-					/* resource configuration       */
-
-#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
-
-#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
-
-#define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A    */
-#define CONFIG_SYS_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
-#define CONFIG_SYS_PCI_PTM1LA  (bd->bi_memstart) /* point to sdram               */
-#define CONFIG_SYS_PCI_PTM1MS  (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
-#define CONFIG_SYS_PCI_PTM2LA  0xffc00000      /* point to flash               */
-#define CONFIG_SYS_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
-#define CONFIG_SYS_PCI_PTM2PCI (bd->bi_memsize) /* host use this pci address */
-
-#define CONFIG_PCI_4xx_PTM_OVERWRITE	1 /* overwrite PTMx settings by env */
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff
- *-----------------------------------------------------------------------
- */
-#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
-#define CONFIG_IDE_RESET	1	/* reset for ide supported	*/
-
-#define CONFIG_SYS_IDE_MAXBUS		1		/* max. 1 IDE busses	*/
-#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
-
-#define CONFIG_SYS_ATA_BASE_ADDR	0xF0100000
-#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
-
-#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
-#define CONFIG_SYS_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
-#define CONFIG_SYS_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_FLASH_BASE		0xFFFC0000
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
-#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
-
-#define CONFIG_PRAM		0	/* use pram variable to overwrite */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
-#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
-#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
-#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
-#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-
-#if 0 /* Use NVRAM for environment variables */
-/*-----------------------------------------------------------------------
- * NVRAM organization
- */
-#define CONFIG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
-#define CONFIG_ENV_SIZE		0x0ff8		/* Size of Environment vars	*/
-#define CONFIG_ENV_ADDR		\
-	(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-(CONFIG_ENV_SIZE+8))	/* Env	*/
-
-#else /* Use EEPROM for environment variables */
-
-#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
-#define CONFIG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
-#define CONFIG_ENV_SIZE		0x800	/* 2048 bytes may be used for env vars*/
-				   /* total size of a CAT24WC16 is 2048 bytes */
-#endif
-
-#define CONFIG_SYS_NVRAM_BASE_ADDR	0xf0200000		/* NVRAM base address	*/
-#define CONFIG_SYS_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
-#define CONFIG_SYS_VXWORKS_MAC_PTR     (CONFIG_SYS_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC16) for environment
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
-					/* 16 byte page write mode using*/
-					/* last 4 bits of the address	*/
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	0xFF800000	/* FLASH bank #0	*/
-#define FLASH_BASE1_PRELIM	0xFFC00000	/* FLASH bank #1	*/
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (Flash Bank 0) initialization					*/
-#define CONFIG_SYS_EBC_PB0AP		0x92015480
-#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 1 (Flash Bank 1) initialization					*/
-#define CONFIG_SYS_EBC_PB1AP		0x92015480
-#define CONFIG_SYS_EBC_PB1CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 2 (CAN0, 1) initialization					*/
-#define CONFIG_SYS_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CONFIG_SYS_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
-#define CONFIG_SYS_LED_ADDR		0xF0000380
-
-/* Memory Bank 3 (CompactFlash IDE) initialization				*/
-#define CONFIG_SYS_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CONFIG_SYS_EBC_PB3CR		0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 4 (NVRAM/RTC) initialization					*/
-/*#define CONFIG_SYS_EBC_PB4AP		  0x01805280  / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1	   */
-#define CONFIG_SYS_EBC_PB4AP		0x01805680  /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1	*/
-#define CONFIG_SYS_EBC_PB4CR		0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit	*/
-
-/* Memory Bank 5 (optional Quart) initialization				*/
-#define CONFIG_SYS_EBC_PB5AP		0x04005B80  /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
-#define CONFIG_SYS_EBC_PB5CR		0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit	*/
-
-/* Memory Bank 6 (FPGA internal) initialization					*/
-#define CONFIG_SYS_EBC_PB6AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CONFIG_SYS_EBC_PB6CR		0xF041A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
-#define CONFIG_SYS_FPGA_BASE_ADDR	0xF0400000
-
-/*-----------------------------------------------------------------------
- * FPGA stuff
- */
-/* FPGA internal regs */
-#define CONFIG_SYS_FPGA_MODE		0x00
-#define CONFIG_SYS_FPGA_STATUS		0x02
-#define CONFIG_SYS_FPGA_TS		0x04
-#define CONFIG_SYS_FPGA_TS_LOW		0x06
-#define CONFIG_SYS_FPGA_TS_CAP0	0x10
-#define CONFIG_SYS_FPGA_TS_CAP0_LOW	0x12
-#define CONFIG_SYS_FPGA_TS_CAP1	0x14
-#define CONFIG_SYS_FPGA_TS_CAP1_LOW	0x16
-#define CONFIG_SYS_FPGA_TS_CAP2	0x18
-#define CONFIG_SYS_FPGA_TS_CAP2_LOW	0x1a
-#define CONFIG_SYS_FPGA_TS_CAP3	0x1c
-#define CONFIG_SYS_FPGA_TS_CAP3_LOW	0x1e
-
-/* FPGA Mode Reg */
-#define CONFIG_SYS_FPGA_MODE_CF_RESET	    0x0001
-#define CONFIG_SYS_FPGA_MODE_DUART_RESET   0x0002
-#define CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT 0x0004     /* only set on CPCI-405 Ver 3 */
-#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
-#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR  0x1000
-#define CONFIG_SYS_FPGA_MODE_TS_CLEAR	    0x2000
-
-/* FPGA Status Reg */
-#define CONFIG_SYS_FPGA_STATUS_DIP0	0x0001
-#define CONFIG_SYS_FPGA_STATUS_DIP1	0x0002
-#define CONFIG_SYS_FPGA_STATUS_DIP2	0x0004
-#define CONFIG_SYS_FPGA_STATUS_FLASH	0x0008
-#define CONFIG_SYS_FPGA_STATUS_TS_IRQ	0x1000
-
-#define CONFIG_SYS_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
-#define CONFIG_SYS_FPGA_MAX_SIZE	32*1024	    /* 32kByte is enough for XC2S15  */
-
-/* FPGA program pin configuration */
-#define CONFIG_SYS_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
-#define CONFIG_SYS_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
-#define CONFIG_SYS_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
-#define CONFIG_SYS_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input)     */
-#define CONFIG_SYS_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input)     */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in data cache)
- */
-#define CONFIG_SYS_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */
-
-#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
-#define CONFIG_SYS_INIT_RAM_SIZE	0x2000	/* Size of used area in RAM	       */
-#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h
deleted file mode 100644
index 3a1d4d9388..0000000000
--- a/include/configs/MIP405.h
+++ /dev/null
@@ -1,347 +0,0 @@
-/*
- * (C) Copyright 2001, 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/***********************************************************
- * High Level Configuration Options
- * (easy to change)
- ***********************************************************/
-#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
-
-#define	CONFIG_SYS_TEXT_BASE	0xFFF80000
-
-/***********************************************************
- * Note that it may also be a MIP405T board which is a subset of the
- * MIP405
- ***********************************************************/
-/***********************************************************
- * WARNING:
- * CONFIG_BOOT_PCI is only used for first boot-up and should
- * NOT be enabled for production bootloader
- ***********************************************************/
-/*#define        CONFIG_BOOT_PCI         1*/
-/***********************************************************
- * Clock
- ***********************************************************/
-#define CONFIG_SYS_CLK_FREQ	33000000 /* external frequency to pll   */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SAVES
-
-/**************************************************************
- * I2C Stuff:
- * the MIP405 is equiped with an Atmel 24C128/256 EEPROM at address
- * 0x53.
- * The Atmel EEPROM uses 16Bit addressing.
- ***************************************************************/
-
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		50000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR	0x53	/* EEPROM 24C128/256		*/
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2	/* Bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"    */
-#undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6	/* The Atmel 24C128/256 has	*/
-					/* 64 byte page write mode using*/
-					/* last	6 bits of the address	*/
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
-
-#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
-#define CONFIG_ENV_OFFSET		0x00000	/* environment starts at the beginning of the EEPROM */
-#define CONFIG_ENV_SIZE		0x00800	/* 2k bytes may be used for env vars */
-
-/***************************************************************
- * Definitions for Serial Presence Detect EEPROM address
- * (to get SDRAM settings)
- ***************************************************************/
-/*#define SDRAM_EEPROM_WRITE_ADDRESS	0xA0
-#define SDRAM_EEPROM_READ_ADDRESS	0xA1
-*/
-/**************************************************************
- * Environment definitions
- **************************************************************/
-/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
-/* #define CONFIG_BOOT_RETRY_TIME	-10	/XXX* feature is available but not enabled */
-
-#define CONFIG_BOOTCOMMAND	"diskboot 400000 0:1; bootm" /* autoboot command		*/
-#define CONFIG_BOOTARGS		"console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
-
-#define CONFIG_IPADDR		10.0.0.100
-#define CONFIG_SERVERIP		10.0.0.1
-#define CONFIG_PREBOOT
-/***************************************************************
- * defines if an overwrite_console function exists
- *************************************************************/
-/***************************************************************
- * defines if the overwrite_console should be stored in the
- * environment
- **************************************************************/
-
-/**************************************************************
- * loads config
- *************************************************************/
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#define CONFIG_MISC_INIT_R
-/***********************************************************
- * Miscellaneous configurable options
- **********************************************************/
-#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x0100000	/* memtest works on	*/
-#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 1 ... 12 MB in DRAM	*/
-
-#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
-
-#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
-#define CONFIG_SYS_BASE_BAUD       916667
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE	\
-	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
-	 57600, 115200, 230400, 460800, 921600 }
-
-#define CONFIG_SYS_LOAD_ADDR	0x400000	/* default load address */
-#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
-#define PCI_HOST_FORCE  1               /* configure as pci host        */
-#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
-
-#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
-#define CONFIG_PCI_HOST PCI_HOST_FORCE	/* configure as pci-host	*/
-					/* resource configuration	*/
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000	/* PCI Vendor ID: to-do!!!	*/
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000	/* PCI Device ID: to-do!!!	*/
-#define CONFIG_SYS_PCI_PTM1LA	0x00000000	/* point to sdram		*/
-#define CONFIG_SYS_PCI_PTM1MS	0x80000001	/* 2GB, enable hard-wired to 1	*/
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
-#define CONFIG_SYS_PCI_PTM2LA	0x00000000	/* disabled			*/
-#define CONFIG_SYS_PCI_PTM2MS	0x00000000	/* disabled			*/
-#define CONFIG_SYS_PCI_PTM2PCI 0x00000000      /* Host: use this pci address   */
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_FLASH_BASE		0xFFF80000
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Monitor	*/
-#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserve 1024 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_UPDATE_FLASH_SIZE
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-
-#define CONFIG_FLASH_SHOW_PROGRESS	45
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	1
-#define CONFIG_SYS_MAX_FLASH_SECT	256
-
-/*
- * JFFS2 partitions
- *
- */
-/* No command line, one static partition, whole device */
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_JFFS2_DEV		"nor0"
-#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET	0x00000000
-
-/* mtdparts command line support */
-/* Note: fake mtd_id used, no linux mtd map file */
-/*
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT		"nor0=mip405-0"
-#define MTDPARTS_DEFAULT	"mtdparts=mip405-0:-(jffs2)"
-*/
-
-/*-----------------------------------------------------------------------
- * Logbuffer Configuration
- */
-#undef CONFIG_LOGBUFFER		/* supported but not enabled */
-/*-----------------------------------------------------------------------
- * Bootcountlimit Configuration
- */
-#undef CONFIG_BOOTCOUNT_LIMIT	/* supported but not enabled */
-
-/*-----------------------------------------------------------------------
- * POST Configuration
- */
-#if 0 /* enable this if POST is desired (is supported but not enabled) */
-#define CONFIG_POST		(CONFIG_SYS_POST_MEMORY	| \
-				 CONFIG_SYS_POST_CPU		| \
-				 CONFIG_SYS_POST_RTC		| \
-				 CONFIG_SYS_POST_I2C)
-
-#endif
-/*
- * Init Memory Controller:
- */
-#define FLASH_MAX_SIZE		0x00800000		/* 8MByte max */
-#define FLASH_BASE_PRELIM	0xFF800000  /* open the flash CS */
-/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
-#define FLASH_SIZE_PRELIM	 3  /* maximal flash FLASH size bank #0	*/
-
-#define CONFIG_BOARD_EARLY_INIT_R
-
-/* Peripheral Bus Mapping */
-#define PER_PLD_ADDR		0xF4000000 /* smallest window is 1MByte 0x10 0000*/
-#define PER_UART0_ADDR		0xF4100000 /* smallest window is 1MByte 0x10 0000*/
-#define PER_UART1_ADDR		0xF4200000 /* smallest window is 1MByte 0x10 0000*/
-
-#define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
-#define CONFIG_PORT_ADDR	PER_PLD_ADDR + 5
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in On Chip SRAM)
- */
-#define CONFIG_SYS_TEMP_STACK_OCM      1
-#define CONFIG_SYS_OCM_DATA_ADDR	0xF0000000
-#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR	/* inside of On Chip SRAM    */
-#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE	/* Size of On Chip SRAM	       */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-/* reserve some memory for POST and BOOT limit info */
-#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 32)
-
-#ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */
-#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 12)
-#endif
-
-/***********************************************************************
- * External peripheral base address
- ***********************************************************************/
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xE8000000
-
-/***********************************************************************
- * Last Stage Init
- ***********************************************************************/
-#define CONFIG_LAST_STAGE_INIT
-/************************************************************
- * Ethernet Stuff
- ***********************************************************/
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_PHY_ADDR		1	/* PHY address			*/
-#define CONFIG_PHY_RESET_DELAY	300	/* Intel LXT971A needs this */
-#define CONFIG_PHY_CMD_DELAY	40	/* Intel LXT971A needs this */
-/************************************************************
- * RTC
- ***********************************************************/
-#define CONFIG_RTC_MC146818
-#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-/************************************************************
- * IDE/ATA stuff
- ************************************************************/
-#if defined(CONFIG_TARGET_MIP405T)
-#define CONFIG_SYS_IDE_MAXBUS		1   /* MIP405T has only one IDE bus	*/
-#else
-#define CONFIG_SYS_IDE_MAXBUS		2   /* max. 2 IDE busses	*/
-#endif
-
-#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
-
-#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_ISA_IO_BASE_ADDRESS /* base address */
-#define CONFIG_SYS_ATA_IDE0_OFFSET	0x01F0		/* ide0 offste */
-#define CONFIG_SYS_ATA_IDE1_OFFSET	0x0170		/* ide1 offset */
-#define CONFIG_SYS_ATA_DATA_OFFSET	0		/* data reg offset	*/
-#define CONFIG_SYS_ATA_REG_OFFSET	0		/* reg offset */
-#define CONFIG_SYS_ATA_ALT_OFFSET	0x200		/* alternate register offset */
-
-#undef	CONFIG_IDE_LED	       /* no led for ide supported     */
-#define CONFIG_IDE_RESET       /* reset for ide supported...	*/
-#define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
-#define CONFIG_SUPPORT_VFAT
-/************************************************************
- * ATAPI support (experimental)
- ************************************************************/
-#define CONFIG_ATAPI			/* enable ATAPI Support */
-
-/************************************************************
- * DISK Partition support
- ************************************************************/
-
-/************************************************************
- * Video support
- ************************************************************/
-#define CONFIG_VIDEO_LOGO
-#undef CONFIG_VIDEO_ONBOARD
-/************************************************************
- * USB support EXPERIMENTAL
- ************************************************************/
-#if !defined(CONFIG_TARGET_MIP405T)
-#define CONFIG_USB_UHCI
-
-/* Enable needed helper functions */
-#endif
-/************************************************************
- * Debug support
- ************************************************************/
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#endif
-
-/************************************************************
- * support BZIP2 compression
- ************************************************************/
-#define CONFIG_BZIP2		1
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h
deleted file mode 100644
index 1f5b9f045f..0000000000
--- a/include/configs/PIP405.h
+++ /dev/null
@@ -1,305 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/***********************************************************
- * High Level Configuration Options
- * (easy to change)
- ***********************************************************/
-#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_PIP405		1	/* ...on a PIP405 board		*/
-
-#define	CONFIG_SYS_TEXT_BASE	0xFFF80000
-
-/***********************************************************
- * Clock
- ***********************************************************/
-#define CONFIG_SYS_CLK_FREQ	33000000 /* external frequency to pll	*/
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_REGINFO
-#define CONFIG_SCSI
-#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_SAVES
-
-/**************************************************************
- * I2C Stuff:
- * the PIP405 is equiped with an Atmel 24C128/256 EEPROM at address
- * 0x53.
- * Caution: on the same bus is the SPD (Serial Presens Detect
- * EEPROM of the SDRAM
- * The Atmel EEPROM uses 16Bit addressing.
- ***************************************************************/
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		50000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR	0x53
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
-#define CONFIG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
-#define CONFIG_ENV_OFFSET          0x000   /* environment starts at the beginning of the EEPROM */
-#define CONFIG_ENV_SIZE            0x800   /* 2 kBytes may be used for env vars */
-
-#undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6	/* The Atmel 24C128/256 has	*/
-					/* 64 byte page write mode using*/
-					/* last	6 bits of the address	*/
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
-
-/***************************************************************
- * Definitions for Serial Presence Detect EEPROM address
- * (to get SDRAM settings)
- ***************************************************************/
-#define SPD_EEPROM_ADDRESS      0x50
-
-#define CONFIG_BOARD_EARLY_INIT_R
-
-/**************************************************************
- * Environment definitions
- **************************************************************/
-
-/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
-/* #define CONFIG_BOOT_RETRY_TIME	-10	/XXX* feature is available but not enabled */
-
-#define CONFIG_BOOTCOMMAND	"diskboot 400000 0:1; bootm" /* autoboot command		*/
-#define CONFIG_BOOTARGS		"console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
-
-#define CONFIG_IPADDR		10.0.0.100
-#define CONFIG_SERVERIP		10.0.0.1
-#define CONFIG_PREBOOT
-/***************************************************************
- * defines if an overwrite_console function exists
- *************************************************************/
-/***************************************************************
- * defines if the overwrite_console should be stored in the
- * environment
- **************************************************************/
-
-/**************************************************************
- * loads config
- *************************************************************/
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#define CONFIG_MISC_INIT_R
-/***********************************************************
- * Miscellaneous configurable options
- **********************************************************/
-#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x0100000	/* memtest works on	*/
-#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 1 ... 12 MB in DRAM	*/
-
-#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
-
-#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
-#define CONFIG_SYS_BASE_BAUD       691200
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE	\
-	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
-	 57600, 115200, 230400, 460800, 921600 }
-
-#define CONFIG_SYS_LOAD_ADDR		0x400000	/* default load address */
-#define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0              /* configure ar pci adapter     */
-#define PCI_HOST_FORCE  1               /* configure as pci host        */
-#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
-
-#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
-#define CONFIG_PCI_HOST PCI_HOST_FORCE	/* configure as pci-host	*/
-					/* resource configuration	*/
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000	/* PCI Vendor ID: to-do!!!	*/
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000	/* PCI Device ID: to-do!!!	*/
-#define CONFIG_SYS_PCI_PTM1LA	0x00000000	/* point to sdram		*/
-#define CONFIG_SYS_PCI_PTM1MS	0x80000001	/* 2GB, enable hard-wired to 1	*/
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
-#define CONFIG_SYS_PCI_PTM2LA	0x00000000	/* disabled			*/
-#define CONFIG_SYS_PCI_PTM2MS	0x00000000	/* disabled			*/
-#define CONFIG_SYS_PCI_PTM2PCI 0x00000000      /* Host: use this pci address   */
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_FLASH_BASE		0xFFF80000
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Monitor	*/
-#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserve 1024 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_UPDATE_FLASH_SIZE
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-
-#define CONFIG_FLASH_SHOW_PROGRESS	45
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	1
-#define CONFIG_SYS_MAX_FLASH_SECT	256
-
-/*
- * Init Memory Controller:
- */
-#define FLASH_MAX_SIZE		0x00800000		/* 8MByte max */
-#define FLASH_BASE_PRELIM	0xFF800000  /* open the flash CS */
-/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
-#define FLASH_SIZE_PRELIM	 3  /* maximal flash FLASH size bank #0	*/
-
-/* Configuration Port location */
-#define CONFIG_PORT_ADDR	0xF4000000
-#define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in On Chip SRAM)
- */
-#define CONFIG_SYS_TEMP_STACK_OCM	1
-#define CONFIG_SYS_OCM_DATA_ADDR	0xF0000000
-#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR	/* inside of On Chip SRAM    */
-#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE	/* Size of On Chip SRAM	       */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/***********************************************************************
- * External peripheral base address
- ***********************************************************************/
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xE8000000
-
-/***********************************************************************
- * Last Stage Init
- ***********************************************************************/
-#define CONFIG_LAST_STAGE_INIT
-/************************************************************
- * Ethernet Stuff
- ***********************************************************/
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_PHY_ADDR		1	/* PHY address			*/
-/************************************************************
- * RTC
- ***********************************************************/
-#define CONFIG_RTC_MC146818
-#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-/************************************************************
- * IDE/ATA stuff
- ************************************************************/
-#define CONFIG_SYS_IDE_MAXBUS		2   /* max. 2 IDE busses	*/
-#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
-
-#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_ISA_IO_BASE_ADDRESS /* base address */
-#define CONFIG_SYS_ATA_IDE0_OFFSET	0x01F0	/* ide0 offste */
-#define CONFIG_SYS_ATA_IDE1_OFFSET	0x0170	/* ide1 offset */
-#define CONFIG_SYS_ATA_DATA_OFFSET	0	/* data reg offset	*/
-#define CONFIG_SYS_ATA_REG_OFFSET	0	/* reg offset */
-#define CONFIG_SYS_ATA_ALT_OFFSET	0x200	/* alternate register offset */
-
-#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
-#define CONFIG_IDE_RESET		/* reset for ide supported...	*/
-#define CONFIG_IDE_RESET_ROUTINE	/* with a special reset function */
-#define CONFIG_SUPPORT_VFAT
-
-/************************************************************
- * ATAPI support (experimental)
- ************************************************************/
-#define CONFIG_ATAPI			/* enable ATAPI Support */
-
-/************************************************************
- * SCSI support (experimental) only SYM53C8xx supported
- ************************************************************/
-#define CONFIG_SCSI_SYM53C8XX
-#define CONFIG_SYS_SCSI_MAX_LUN	8	/* number of supported LUNs */
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID	7	/* maximum SCSI ID (0..6) */
-#define CONFIG_SYS_SCSI_MAX_DEVICE	CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN /* maximum Target devices */
-#define CONFIG_SYS_SCSI_SPIN_UP_TIME	2
-
-/************************************************************
- * Disk-On-Chip configuration
- ************************************************************/
-#define CONFIG_SYS_MAX_DOC_DEVICE	1	/* Max number of DOC devices		*/
-#define CONFIG_SYS_DOC_SHORT_TIMEOUT
-#define CONFIG_SYS_DOC_SUPPORT_2000
-#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
-
-/************************************************************
- * DISK Partition support
- ************************************************************/
-
-/************************************************************
- * Video support
- ************************************************************/
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_VIDEO_ONBOARD		/* Video controller is on-board */
-
-/************************************************************
- * USB support
- ************************************************************/
-#define CONFIG_USB_UHCI
-
-/* Enable needed helper functions */
-
-/************************************************************
- * Debug support
- ************************************************************/
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#endif
-
-/************************************************************
- * support BZIP2 compression
- ************************************************************/
-#define CONFIG_BZIP2		1
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h
deleted file mode 100644
index b8f23d769c..0000000000
--- a/include/configs/PLU405.h
+++ /dev/null
@@ -1,367 +0,0 @@
-/*
- * (C) Copyright 2001-2003
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_PLU405		1	/* ...on a PLU405 board		*/
-
-#define	CONFIG_SYS_TEXT_BASE	0xFFF80000
-
-#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
-
-#define CONFIG_SYS_CLK_FREQ     33333400 /* external frequency to pll   */
-
-#undef	CONFIG_BOOTARGS
-#undef	CONFIG_BOOTCOMMAND
-
-#define CONFIG_PREBOOT                  /* enable preboot variable      */
-
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#undef  CONFIG_HAS_ETH1
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_PHY_ADDR		0	/* PHY address			*/
-#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
-#define CONFIG_RESET_PHY_R      1       /* use reset_phy()              */
-
-#define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_NAND
-
-#define CONFIG_SUPPORT_VFAT
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define CONFIG_RTC_MC146818		/* DS1685 is MC146818 compatible*/
-#define CONFIG_SYS_RTC_REG_BASE_ADDR	 0xF0000500 /* RTC Base Address		*/
-
-#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
-
-#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
-
-#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
-
-#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
-#define CONFIG_SYS_BASE_BAUD	    691200
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE	\
-	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
-	 57600, 115200, 230400, 460800, 921600 }
-
-#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
-#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
-
-#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-
-#define CONFIG_SYS_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
-
-/*
- * NAND-FLASH stuff
- */
-#define CONFIG_SYS_NAND_BASE_LIST	{CONFIG_SYS_NAND_BASE}
-#define CONFIG_SYS_MAX_NAND_DEVICE	1         /* Max number of NAND devices */
-#define NAND_BIG_DELAY_US	25
-
-#define CONFIG_SYS_NAND_CE             (0x80000000 >> 1)   /* our CE is GPIO1  */
-#define CONFIG_SYS_NAND_RDY            (0x80000000 >> 4)   /* our RDY is GPIO4 */
-#define CONFIG_SYS_NAND_CLE            (0x80000000 >> 2)   /* our CLE is GPIO2 */
-#define CONFIG_SYS_NAND_ALE            (0x80000000 >> 3)   /* our ALE is GPIO3 */
-
-#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1       /* ".i" read skips bad blocks   */
-#define CONFIG_SYS_NAND_QUIET          1
-
-/*
- * PCI stuff
- */
-#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
-#define PCI_HOST_FORCE  1               /* configure as pci host        */
-#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
-
-#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
-#define CONFIG_PCI_HOST	PCI_HOST_FORCE  /* select pci host function     */
-					/* resource configuration       */
-
-#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
-
-#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
-#define CONFIG_SYS_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
-#define CONFIG_SYS_PCI_PTM1LA  0x00000000      /* point to sdram               */
-#define CONFIG_SYS_PCI_PTM1MS  0xf8000001      /* 128MB, enable hard-wired to 1 */
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
-#define CONFIG_SYS_PCI_PTM2LA  0xffc00000      /* point to flash               */
-#define CONFIG_SYS_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
-#define CONFIG_SYS_PCI_PTM2PCI 0x08000000      /* Host: use this pci address   */
-
-/*
- * IDE/ATA stuff
- */
-#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
-#define CONFIG_IDE_RESET	1	/* reset for ide supported	*/
-
-#define CONFIG_SYS_IDE_MAXBUS		1		/* max. 1 IDE busses	*/
-/* max. 1 drives per IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*1)
-
-#define CONFIG_SYS_ATA_BASE_ADDR	0xF0100000
-#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
-
-#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O */
-#define CONFIG_SYS_ATA_REG_OFFSET	0x0000	/* Offset for normal register access */
-#define CONFIG_SYS_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
-
-/*
- * FLASH organization
- */
-#define FLASH_BASE0_PRELIM	0xFFC00000 /* FLASH bank #0 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width) */
-#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st addr for flash config cycles */
-#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd addr for flash config cycles */
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard */
-#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard */
-#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector */
-
-/*
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN		(~(CONFIG_SYS_TEXT_BASE) + 1)
-#define CONFIG_SYS_MALLOC_LEN		(1024 << 10)
-
-/*
- * Environment Variable setup
- */
-#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
-#define CONFIG_ENV_OFFSET		0x100	/* reseve 0x100 bytes for strapping */
-#define CONFIG_ENV_SIZE		0x700
-
-/*
- * I2C EEPROM (24WC16) for environment
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM 24WC16 */
-#define CONFIG_SYS_EEPROM_WREN         1
-
-/* 24WC16 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"    */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The 24WC16 has   */
-					/* 16 byte page write mode using */
-					/* last 4 bits of the address   */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-
-/*
- * External Bus Controller (EBC) Setup
- */
-#define CAN0_BA		0xF0000000	    /* CAN0 Base Address	*/
-#define CAN1_BA		0xF0000100	    /* CAN1 Base Address	*/
-#define DUART0_BA	0xF0000400	    /* DUART Base Address       */
-#define DUART1_BA	0xF0000408	    /* DUART Base Address       */
-#define RTC_BA		0xF0000500	    /* RTC Base Address         */
-#define VGA_BA		0xF1000000	    /* Epson VGA Base Address   */
-#define CONFIG_SYS_NAND_BASE	0xF4000000	    /* NAND FLASH Base Address  */
-
-/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
-/* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
-#define CONFIG_SYS_EBC_PB0AP		0x92015480
-/* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
-#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000
-
-/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB1AP		0x92015480
-/* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
-#define CONFIG_SYS_EBC_PB1CR		0xF4018000
-
-/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
-/* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CONFIG_SYS_EBC_PB2AP		0x010053C0
-/* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
-#define CONFIG_SYS_EBC_PB2CR		0xF0018000
-
-/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */
-/* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CONFIG_SYS_EBC_PB3AP		0x010053C0
-/* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
-#define CONFIG_SYS_EBC_PB3CR		0xF011A000
-
-/*
- * FPGA stuff
- */
-#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0100100	    /* FPGA internal Base Address */
-
-/* FPGA internal regs */
-#define CONFIG_SYS_FPGA_CTRL		0x000
-
-/* FPGA Control Reg */
-#define CONFIG_SYS_FPGA_CTRL_CF_RESET	0x0001
-#define CONFIG_SYS_FPGA_CTRL_WDI	0x0002
-#define CONFIG_SYS_FPGA_CTRL_PS2_RESET 0x0020
-
-#define CONFIG_SYS_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now */
-#define CONFIG_SYS_FPGA_MAX_SIZE	128*1024    /* 128kByte is enough for XC2S50E*/
-
-/* FPGA program pin configuration */
-#define CONFIG_SYS_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
-#define CONFIG_SYS_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output) */
-#define CONFIG_SYS_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output) */
-#define CONFIG_SYS_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input) */
-#define CONFIG_SYS_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input) */
-
-/*
- * Definitions for initial stack pointer and data area (in data cache)
- */
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CONFIG_SYS_TEMP_STACK_OCM	  1
-
-/* On Chip Memory location */
-#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
-#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM  */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/*
- * Definitions for GPIO setup (PPC405EP specific)
- *
- * GPIO0[0]	- External Bus Controller BLAST output
- * GPIO0[1-9]	- Instruction trace outputs -> GPIO
- * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
- * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
- * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
- * GPIO0[24-27] - UART0 control signal inputs/outputs
- * GPIO0[28-29] - UART1 data signal input/output
- * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
- */
-#define CONFIG_SYS_GPIO0_OSRL		0x00000550
-#define CONFIG_SYS_GPIO0_OSRH		0x00000110
-#define CONFIG_SYS_GPIO0_ISR1L		0x00000000
-#define CONFIG_SYS_GPIO0_ISR1H		0x15555445
-#define CONFIG_SYS_GPIO0_TSRL		0x00000000
-#define CONFIG_SYS_GPIO0_TSRH		0x00000000
-#define CONFIG_SYS_GPIO0_TCR		0x77FE0014
-
-#define CONFIG_SYS_DUART_RST		(0x80000000 >> 14)
-#define CONFIG_SYS_EEPROM_WP		(0x80000000 >> 0)
-
-/*
- * Default speed selection (cpu_plb_opb_ebc) in MHz.
- * This value will be set if iic boot eprom is disabled.
- */
-#if 1
-#define PLLMR0_DEFAULT	 PLLMR0_266_133_66_33
-#define PLLMR1_DEFAULT	 PLLMR1_266_133_66_33
-#endif
-#if 0
-#define PLLMR0_DEFAULT	 PLLMR0_200_100_50_33
-#define PLLMR1_DEFAULT	 PLLMR1_200_100_50_33
-#endif
-#if 0
-#define PLLMR0_DEFAULT	 PLLMR0_133_66_66_33
-#define PLLMR1_DEFAULT	 PLLMR1_133_66_66_33
-#endif
-
-/*
- * PCI OHCI controller
- */
-#define CONFIG_USB_OHCI_NEW	1
-#define CONFIG_PCI_OHCI		1
-#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"ohci_pci"
-
-/*
- * UBI
- */
-#define CONFIG_RBTREE
-#define CONFIG_MTD_DEVICE
-#define CONFIG_MTD_PARTITIONS
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_LZO
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/PMC405DE.h b/include/configs/PMC405DE.h
deleted file mode 100644
index a94e790b95..0000000000
--- a/include/configs/PMC405DE.h
+++ /dev/null
@@ -1,330 +0,0 @@
-/*
- * (C) Copyright 2009
- * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd.eu
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_PMC405DE		1	/* ...on a PMC405DE board	*/
-
-#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
-
-#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
-#define CONFIG_BOARD_TYPES	1	/* support board types		*/
-
-#define CONFIG_SYS_CLK_FREQ	33330000 /* external frequency to pll	*/
-
-#undef  CONFIG_BOOTARGS
-#undef  CONFIG_BOOTCOMMAND
-
-#define CONFIG_PREBOOT			/* enable preboot variable	*/
-
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change*/
-
-#define CONFIG_HAS_ETH1
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_PHY_ADDR		1	/* PHY address			*/
-#define CONFIG_PHY1_ADDR	2	/* 2nd PHY address		*/
-
-#define CONFIG_SYS_RX_ETH_BUFFER	16 /* use 16 rx buffer on 405 emac */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_PCI
-
-#undef  CONFIG_WATCHDOG			/* watchdog disabled */
-#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0 */
-#define CONFIG_PRAM		0
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP
-
-#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
-
-#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device */
-
-#define CONFIG_SYS_MEMTEST_START	0x0100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		0x3000000 /* 1 ... 48 MB in DRAM */
-
-#define CONFIG_CONS_INDEX	2	/* Use UART1			*/
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
-
-#undef  CONFIG_SYS_EXT_SERIAL_CLOCK
-#define CONFIG_SYS_BASE_BAUD		691200
-
-#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
-#define CONFIG_SYS_EXTBDINFO	1	/* To use extended board_into (bd_t) */
-
-#define CONFIG_CMDLINE_EDITING	1	/* add command line history     */
-#define CONFIG_MX_CYCLIC	1	/* enable mdc/mwc commands      */
-
-/*
- * PCI stuff
- */
-#define PCI_HOST_ADAPTER	0	/* configure as pci adapter	*/
-#define PCI_HOST_FORCE		1	/* configure as pci host	*/
-#define PCI_HOST_AUTO		2	/* detected via arbiter enable	*/
-
-#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
-#define CONFIG_PCI_HOST	PCI_HOST_AUTO  /* select pci host function	*/
-
-#define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup		*/
-
-/*
- * PCI identification
- */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID		PCI_VENDOR_ID_ESDGMBH
-#define CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH 0x040e /* Dev ID: Non-Monarch */
-#define CONFIG_SYS_PCI_SUBSYS_ID_MONARCH 0x040f	/* Dev ID: Monarch */
-#define CONFIG_SYS_PCI_CLASSCODE_NONMONARCH	PCI_CLASS_PROCESSOR_POWERPC
-#define CONFIG_SYS_PCI_CLASSCODE_MONARCH	PCI_CLASS_BRIDGE_HOST
-
-#define CONFIG_SYS_PCI_CLASSCODE CONFIG_SYS_PCI_CLASSCODE_MONARCH
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID CONFIG_SYS_PCI_SUBSYS_ID_MONARCH
-
-#define CONFIG_SYS_PCI_PTM1LA  0x00000000      /* point to sdram */
-#define CONFIG_SYS_PCI_PTM1MS  0xfc000001      /* 64MB, enable=1 */
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address */
-#define CONFIG_SYS_PCI_PTM2LA  0xef000000      /* point to CPLD, GPIO */
-#define CONFIG_SYS_PCI_PTM2MS  0xff000001      /* 16MB, enable=1 */
-#define CONFIG_SYS_PCI_PTM2PCI 0x04000000      /* Host: use this pci address */
-
-#define CONFIG_PCI_4xx_PTM_OVERWRITE	1 /* overwrite PTMx settings by env */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)
-/*
- * FLASH organization
- */
-#define CONFIG_SYS_FLASH_CFI		1	/* CFI compatible */
-#define CONFIG_FLASH_CFI_DRIVER		1	/* Use common CFI driver */
-
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max. no. memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max sectors per chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* erase timeout (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* write timeout (in ms) */
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* buffered writes (faster) */
-#define CONFIG_SYS_FLASH_PROTECTION	1	/* hardware flash protection */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO	1 /* 'E' for empty sector (flinfo) */
-#define CONFIG_SYS_FLASH_QUIET_TEST	1 /* don't warn upon unknown flash */
-
-/*
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_FLASH_BASE		0xfe000000
-#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN		(~(CONFIG_SYS_TEXT_BASE) + 1)
-#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)
-
-/*
- * Environment in EEPROM setup
- */
-#define CONFIG_ENV_IS_IN_EEPROM		1
-#define CONFIG_ENV_OFFSET		0x100
-#define CONFIG_ENV_SIZE			0x700
-
-/*
- * I2C EEPROM (24W16) for environment
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM 24W16	*/
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address" */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has */
-					/* 16 byte page write mode using*/
-					/* last 4 bits of the address */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10 /* and takes up to 10 msec */
-#define CONFIG_SYS_EEPROM_WREN		1
-
-#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR	0x50
-#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET	0x40
-#define CONFIG_4xx_CONFIG_BLOCKSIZE		0x20
-
-/*
- * RTC
- */
-#define CONFIG_RTC_RX8025
-
-/*
- * External Bus Controller (EBC) Setup
- * (max. 55MHZ EBC clock)
- */
-/* Memory Bank 0 (NOR flash) BAS=0xFE0,BS=32MB,BU=R/W,BW=16bit */
-#define CONFIG_SYS_EBC_PB0AP		0x03017200
-#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_FLASH_BASE | 0xba000)
-
-/* Memory Bank 1 (CPLD) BAS=0xEF0,BS=16MB,BU=R/W,BW=16bit */
-#define CONFIG_SYS_CPLD_BASE		0xef000000
-#define CONFIG_SYS_EBC_PB1AP		0x00800000
-#define CONFIG_SYS_EBC_PB1CR		(CONFIG_SYS_CPLD_BASE | 0x18000)
-
-/*
- * Definitions for initial stack pointer and data area (in data cache)
- */
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CONFIG_SYS_TEMP_STACK_OCM	  1
-
-/* On Chip Memory location */
-#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
-#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
-/* inside SDRAM */
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR
-/* End of used area in RAM */
-#define CONFIG_SYS_INIT_RAM_SIZE		CONFIG_SYS_OCM_DATA_SIZE
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
-					 GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/*
- * GPIO Configuration
- */
-#define CONFIG_SYS_4xx_GPIO_TABLE {                  /* GPIO    Alt1       */ \
-{                                                                             \
-/* GPIO Core 0 */                                                             \
-{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO0   PerBLast   */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO1   TS1E       */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO2   TS2E       */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO3   TS1O       */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO4   TS2O       */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1 },      /* GPIO5   TS3        */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1 },      /* GPIO6   TS4        */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1 },      /* GPIO7   TS5        */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO8   TS6        */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1 },      /* GPIO9   TrcClk     */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10  PerCS1     */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO11  PerCS2     */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO12  PerCS3     */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO13  PerCS4     */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO14  PerAddr03  */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO15  PerAddr04  */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16  PerAddr05  */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17  IRQ0       */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18  IRQ1       */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19  IRQ2       */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO20  IRQ3       */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO21  IRQ4       */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO22  IRQ5       */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO23  IRQ6       */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24  UART0_DCD  */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO25  UART0_DSR  */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO26  UART0_RI   */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO27  UART0_DTR  */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28  UART1_Rx   */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29  UART1_Tx   */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO30  RejectPkt0 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO31  RejectPkt1 */ \
-}                                                                             \
-}
-
-#define CONFIG_SYS_GPIO_HWREV_MASK	(0xf0000000 >> 1)	/* GPIO1..4 */
-#define CONFIG_SYS_GPIO_HWREV_SHIFT	27
-#define CONFIG_SYS_GPIO_LEDRUN_N	(0x80000000 >> 5)	/* GPIO5 */
-#define CONFIG_SYS_GPIO_LEDA_N		(0x80000000 >> 6)	/* GPIO6 */
-#define CONFIG_SYS_GPIO_LEDB_N		(0x80000000 >> 7)	/* GPIO7 */
-#define CONFIG_SYS_GPIO_SELFRST_N	(0x80000000 >> 8)	/* GPIO8 */
-#define CONFIG_SYS_GPIO_EEPROM_WP	(0x80000000 >> 9)	/* GPIO9 */
-#define CONFIG_SYS_GPIO_MONARCH_N	(0x80000000 >> 11)	/* GPIO11 */
-#define CONFIG_SYS_GPIO_EREADY		(0x80000000 >> 12)	/* GPIO12 */
-#define CONFIG_SYS_GPIO_M66EN		(0x80000000 >> 13)	/* GPIO13 */
-
-/*
- * Default speed selection (cpu_plb_opb_ebc) in mhz.
- * This value will be set if iic boot eprom is disabled.
- */
-#undef CONFIG_SYS_FCPU333MHZ
-#define CONFIG_SYS_FCPU266MHZ
-#undef CONFIG_SYS_FCPU133MHZ
-
-#if defined(CONFIG_SYS_FCPU333MHZ)
-/*
- * CPU: 333MHz
- * PLB/SDRAM/MAL: 111MHz
- * OPB: 55MHz
- * EBC: 55MHz
- * PCI: 55MHz (111MHz on M66EN=1)
- */
-#define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_3 |		\
-			PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 |	\
-			PLL_MALDIV_1 | PLL_PCIDIV_2)
-#define PLLMR1_DEFAULT (PLL_FBKDIV_10  |			\
-			PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |		\
-			PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
-#endif
-
-#if defined(CONFIG_SYS_FCPU266MHZ)
-/*
- * CPU: 266MHz
- * PLB/SDRAM/MAL: 133MHz
- * OPB: 66MHz
- * EBC: 44MHz
- * PCI: 44MHz (66MHz on M66EN=1)
- */
-#define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_2 |		\
-			PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |	\
-			PLL_MALDIV_1 | PLL_PCIDIV_3)
-#define PLLMR1_DEFAULT (PLL_FBKDIV_8  |  \
-			PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |		\
-			PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-#endif
-
-#if defined(CONFIG_SYS_FCPU133MHZ)
-/*
- * CPU: 133MHz
- * PLB/SDRAM/MAL: 133MHz
- * OPB: 66MHz
- * EBC: 44MHz
- * PCI: 44MHz (66MHz on M66EN=1)
- */
-#define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_1 |		\
-			PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |	\
-			PLL_MALDIV_1 | PLL_PCIDIV_3)
-#define PLLMR1_DEFAULT (PLL_FBKDIV_4  |  \
-			PLL_FWDDIVA_6 | PLL_FWDDIVB_6 |		\
-			PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-#endif
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h
deleted file mode 100644
index 54a1a2546f..0000000000
--- a/include/configs/PMC440.h
+++ /dev/null
@@ -1,363 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
- * Based on the sequoia configuration file.
- *
- * (C) Copyright 2006-2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2006
- * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
- * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/************************************************************************
- * PMC440.h - configuration for esd PMC440 boards
- ***********************************************************************/
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- *----------------------------------------------------------------------*/
-#define CONFIG_440EPX		1	/* Specific PPC440EPx   */
-#define CONFIG_440		1	/* ... PPC440 family    */
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE	0xFFF90000
-#endif
-
-#define CONFIG_SYS_CLK_FREQ	33333400
-
-#if 0 /* temporary disabled because OS/9 does not like dcache on startup */
-#define CONFIG_4xx_DCACHE		/* enable dcache        */
-#endif
-
-#define CONFIG_MISC_INIT_F	1
-#define CONFIG_MISC_INIT_R	1	/* Call misc_init_r     */
-#define CONFIG_BOARD_TYPES	1	/* support board types  */
-/*-----------------------------------------------------------------------
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MONITOR_LEN		(~(CONFIG_SYS_TEXT_BASE) + 1)
-#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserve 256 kB for malloc()  */
-
-#define CONFIG_PRAM		0	/* use pram variable to overwrite */
-
-#define CONFIG_SYS_BOOT_BASE_ADDR	0xf0000000
-#define CONFIG_SYS_SDRAM_BASE		0x00000000	/* _must_ be 0          */
-#define CONFIG_SYS_FLASH_BASE		0xfc000000	/* start of FLASH       */
-#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_NAND_ADDR		0xd0000000	/* NAND Flash           */
-#define CONFIG_SYS_OCM_BASE		0xe0010000	/* ocm                  */
-#define CONFIG_SYS_OCM_DATA_ADDR	CONFIG_SYS_OCM_BASE
-#define CONFIG_SYS_PCI_BASE		0xe0000000	/* Internal PCI regs    */
-#define CONFIG_SYS_PCI_MEMBASE		0x80000000	/* mapped pci memory    */
-#define CONFIG_SYS_PCI_MEMBASE1	CONFIG_SYS_PCI_MEMBASE  + 0x10000000
-#define CONFIG_SYS_PCI_MEMBASE2	CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
-#define CONFIG_SYS_PCI_MEMBASE3	CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
-#define CONFIG_SYS_PCI_MEMSIZE		0x80000000	/* 2GB! */
-
-#define CONFIG_SYS_USB2D0_BASE		0xe0000100
-#define CONFIG_SYS_USB_DEVICE		0xe0000000
-#define CONFIG_SYS_USB_HOST		0xe0000400
-#define CONFIG_SYS_FPGA_BASE0		0xef000000	/* 32 bit */
-#define CONFIG_SYS_FPGA_BASE1		0xef100000	/* 16 bit */
-#define CONFIG_SYS_RESET_BASE		0xef200000
-
-/*-----------------------------------------------------------------------
- * Initial RAM & stack pointer
- *----------------------------------------------------------------------*/
-/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache	*/
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_BASE	/* OCM                  */
-#define CONFIG_SYS_INIT_RAM_SIZE	(4 << 10)
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
-
-/*-----------------------------------------------------------------------
- * Serial Port
- *----------------------------------------------------------------------*/
-#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK
-
-#define CONFIG_SYS_BAUDRATE_TABLE						\
-	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-/*-----------------------------------------------------------------------
- * Environment
- *----------------------------------------------------------------------*/
-#define CONFIG_ENV_IS_IN_EEPROM	1	/* use FLASH for environment vars */
-
-/*-----------------------------------------------------------------------
- * RTC
- *----------------------------------------------------------------------*/
-#define CONFIG_RTC_RX8025
-
-/*-----------------------------------------------------------------------
- * FLASH related
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_FLASH_CFI		/* The flash is CFI compatible  */
-#define CONFIG_FLASH_CFI_DRIVER	/* Use common CFI driver        */
-
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks           */
-#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip    */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)      */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)      */
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)     */
-#define CONFIG_SYS_FLASH_PROTECTION	1	/* use hardware flash protection        */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO	/* print 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash        */
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE	0x20000	/* size of one complete sector          */
-#define CONFIG_ENV_ADDR		((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector     */
-
-/* Address and size of Redundant Environment Sector	*/
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_EEPROM
-#define CONFIG_I2C_ENV_EEPROM_BUS	0
-#define CONFIG_ENV_OFFSET		0	/* environment starts at the beginning of the EEPROM */
-#define CONFIG_ENV_SIZE		0x1000	/* 4096 bytes may be used for env vars */
-#endif
-
-/*-----------------------------------------------------------------------
- * DDR SDRAM
- *----------------------------------------------------------------------*/
-#define CONFIG_DDR_DATA_EYE	/* use DDR2 optimization        */
-#define CONFIG_SYS_MEM_TOP_HIDE	(4 << 10) /* don't use last 4kbytes */
-						  /* 440EPx errata CHIP 11 */
-
-/*-----------------------------------------------------------------------
- * I2C
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
-#define CONFIG_SYS_I2C_PPC4XX_CH1
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_1		400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_1		0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR		0x54
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x01
-
-#define CONFIG_SYS_EEPROM_WREN			1
-#define CONFIG_SYS_I2C_BOOT_EEPROM_ADDR	0x52
-
-#define CONFIG_PREBOOT		"echo Add \\\"run fpga\\\" and "	\
-				"\\\"painit\\\" to preboot command"
-
-#undef	CONFIG_BOOTARGS
-
-/* Setup some board specific values for the default environment variables */
-#define CONFIG_HOSTNAME		pmc440
-#define CONFIG_SYS_BOOTFILE	"bootfile=/tftpboot/pmc440/uImage\0"
-#define CONFIG_SYS_ROOTPATH	"rootpath=/opt/eldk/ppc_4xxFP\0"
-
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	CONFIG_SYS_BOOTFILE						\
-	CONFIG_SYS_ROOTPATH						\
-	"fdt_file=/tftpboot/pmc440/pmc440.dtb\0"			\
-	"netdev=eth0\0"							\
-	"ethrotate=no\0"						\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-	"nfsroot=${serverip}:${rootpath}\0"				\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
-	"addmisc=setenv bootargs ${bootargs} mem=${mem}\0"		\
-	"nandargs=setenv bootargs root=/dev/mtdblock6 rootfstype=jffs2 rw\0" \
-	"nand_boot_fdt=run nandargs addip addtty addmisc;"		\
-		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
-	"net_nfs_fdt=tftp ${kernel_addr_r} ${bootfile};"		\
-		"tftp  ${fdt_addr_r} ${fdt_file};"			\
-		"run nfsargs addip addtty addmisc;"			\
-		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
-	"kernel_addr=ffc00000\0"					\
-	"kernel_addr_r=200000\0"					\
-	"fpga_addr=fff00000\0"						\
-	"fdt_addr=fff80000\0"						\
-	"fdt_addr_r=800000\0"						\
-	"fpga=fpga loadb 0 ${fpga_addr}\0"				\
-	"load=tftp 200000 /tftpboot/pmc440/u-boot.bin\0"		\
-	"update=protect off fff90000 ffffffff;era fff90000 ffffffff;"	\
-		"cp.b 200000 fff90000 70000\0"				\
-	""
-
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download  */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change        */
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_IBM_EMAC4_V4	1
-#define CONFIG_MII		1	/* MII PHY management           */
-#define CONFIG_PHY_ADDR		0	/* PHY address, See schematics  */
-
-#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
-
-#define CONFIG_HAS_ETH0
-#define CONFIG_SYS_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
-
-#define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"   */
-#define CONFIG_PHY1_ADDR	1
-#define CONFIG_RESET_PHY_R	1
-
-/* USB */
-#define CONFIG_USB_OHCI_NEW
-#define CONFIG_SYS_OHCI_BE_CONTROLLER
-
-#define CONFIG_SYS_USB_OHCI_BOARD_INIT 1
-#define CONFIG_SYS_USB_OHCI_CPU_INIT	1
-#define CONFIG_SYS_USB_OHCI_REGS_BASE	CONFIG_SYS_USB_HOST
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"ppc440"
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
-
-/* Comment this out to enable USB 1.1 device */
-#define USB_2_0_DEVICE
-
-/* Partitions */
-
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_REGINFO
-
-/* POST support */
-#define CONFIG_POST		(CONFIG_SYS_POST_MEMORY |	\
-				 CONFIG_SYS_POST_CPU    |	\
-				 CONFIG_SYS_POST_UART   |	\
-				 CONFIG_SYS_POST_I2C    |	\
-				 CONFIG_SYS_POST_CACHE  |	\
-				 CONFIG_SYS_POST_FPU    |	\
-				 CONFIG_SYS_POST_ETHER  |	\
-				 CONFIG_SYS_POST_SPR)
-
-#define CONFIG_LOGBUFFER
-#define CONFIG_SYS_POST_CACHE_ADDR	0x7fff0000	/* free virtual address     */
-
-#define CONFIG_SUPPORT_VFAT
-
-/*-----------------------------------------------------------------------
- * Miscellaneous configurable options
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_LONGHELP			/* undef to save memory         */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size      */
-#else
-#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size      */
-#endif
-#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS		16	/* max number of command args   */
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on          */
-#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM       */
-
-#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address      */
-#define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */
-
-#define CONFIG_CMDLINE_EDITING	1	/* add command line history     */
-#define CONFIG_MX_CYCLIC	1	/* enable mdc/mwc commands      */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *----------------------------------------------------------------------*/
-/* General PCI */
-#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
-#define CONFIG_SYS_PCI_CACHE_LINE_SIZE	0	/* to avoid problems with PNP   */
-#define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup  */
-#define CONFIG_SYS_PCI_TARGBASE	0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
-
-/* Board-specific PCI */
-#define CONFIG_SYS_PCI_TARGET_INIT
-#define CONFIG_SYS_PCI_MASTER_INIT
-#define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
-
-#define CONFIG_PCI_BOOTDELAY 0
-
-/* PCI identification */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh      */
-#define CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH 0x0441	/* PCI Device ID: Non-Monarch */
-#define CONFIG_SYS_PCI_SUBSYS_ID_MONARCH 0x0440	/* PCI Device ID: Monarch */
-/* for weak __pci_target_init() */
-#define CONFIG_SYS_PCI_SUBSYS_ID	CONFIG_SYS_PCI_SUBSYS_ID_MONARCH
-#define CONFIG_SYS_PCI_CLASSCODE_NONMONARCH	PCI_CLASS_PROCESSOR_POWERPC
-#define CONFIG_SYS_PCI_CLASSCODE_MONARCH	PCI_CLASS_BRIDGE_HOST
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FPGA stuff
- *----------------------------------------------------------------------*/
-#define CONFIG_FPGA
-#define CONFIG_FPGA_XILINX
-#define CONFIG_FPGA_SPARTAN2
-#define CONFIG_FPGA_SPARTAN3
-
-#define CONFIG_FPGA_COUNT	2
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- *----------------------------------------------------------------------*/
-
-/*
- * On Sequoia CS0 and CS3 are switched when configuring for NAND booting
- */
-#define CONFIG_SYS_NAND_CS		2	/* NAND chip connected to CSx   */
-
-/* Memory Bank 0 (NOR-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB0AP		0x03017200
-#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_FLASH_BASE | 0xda000)
-
-/* Memory Bank 2 (NAND-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB2AP		0x018003c0
-#define CONFIG_SYS_EBC_PB2CR		(CONFIG_SYS_NAND_ADDR | 0x1c000)
-
-/* Memory Bank 1 (RESET) initialization */
-#define CONFIG_SYS_EBC_PB1AP		0x7f817200 /* 0x03017200 */
-#define CONFIG_SYS_EBC_PB1CR		(CONFIG_SYS_RESET_BASE | 0x1c000)
-
-/* Memory Bank 4 (FPGA / 32Bit) initialization */
-#define CONFIG_SYS_EBC_PB4AP		0x03840f40	/* BME=0,TWT=7,CSN=1,TH=7,RE=1,SOR=0,BEM=1 */
-#define CONFIG_SYS_EBC_PB4CR		(CONFIG_SYS_FPGA_BASE0 | 0x1c000)	/* BS=1M,BU=R/W,BW=32bit */
-
-/* Memory Bank 5 (FPGA / 16Bit) initialization */
-#define CONFIG_SYS_EBC_PB5AP		0x03840f40	/* BME=0,TWT=3,CSN=1,TH=0,RE=1,SOR=0,BEM=1 */
-#define CONFIG_SYS_EBC_PB5CR		(CONFIG_SYS_FPGA_BASE1 | 0x1a000)	/* BS=1M,BU=R/W,BW=16bit */
-
-/*-----------------------------------------------------------------------
- * NAND FLASH
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MAX_NAND_DEVICE	1
-#define CONFIG_SYS_NAND_BASE		(CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
-#define CONFIG_SYS_NAND_SELECT_DEVICE	1 /* nand driver supports mutipl. chips */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#endif
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/VOM405.h b/include/configs/VOM405.h
deleted file mode 100644
index a180b381cf..0000000000
--- a/include/configs/VOM405.h
+++ /dev/null
@@ -1,249 +0,0 @@
-/*
- * (C) Copyright 2001-2004
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_VOM405		1	/* ...on a VOM405 board		*/
-
-#define	CONFIG_SYS_TEXT_BASE	0xFFFC8000
-
-#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
-
-#define CONFIG_SYS_CLK_FREQ	33330000 /* external frequency to pll	*/
-
-#undef	CONFIG_BOOTARGS
-#undef  CONFIG_BOOTCOMMAND
-
-#define CONFIG_PREBOOT                  /* enable preboot variable      */
-
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#undef  CONFIG_HAS_ETH1
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_PHY_ADDR		0	/* PHY address			*/
-#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
-#define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-
-/*
- * Command line configuration.
- */
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
-
-#undef  CONFIG_PRAM			/* no "protected RAM"           */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
-
-#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
-#define CONFIG_SYS_BASE_BAUD	    691200
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE	\
-	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
-	 57600, 115200, 230400, 460800, 921600 }
-
-#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
-#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
-
-#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-
-#define CONFIG_SYS_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-/*
- * FLASH organization
- */
-#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
-
-#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
-#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
-#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
-#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
-#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-
-/*
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN		(~(CONFIG_SYS_TEXT_BASE) + 1)
-#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)
-
-#if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
-# define CONFIG_SYS_RAMBOOT		1
-#else
-# undef CONFIG_SYS_RAMBOOT
-#endif
-
-/*
- * Environment Variable setup
- */
-#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
-#define CONFIG_ENV_OFFSET		0x100	/* environment starts at the beginning of the EEPROM */
-#define CONFIG_ENV_SIZE		0x700	/* 2048 bytes may be used for env vars*/
-				   /* total size of a CAT24WC16 is 2048 bytes */
-
-#define CONFIG_SYS_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
-#define CONFIG_SYS_NVRAM_SIZE		242			/* NVRAM size		*/
-
-/*
- * I2C EEPROM (CAT24WC16) for environment
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
-					/* 16 byte page write mode using*/
-					/* last 4 bits of the address	*/
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-
-/*
- * External Bus Controller (EBC) Setup
- */
-#define CAN_BA		0xF0000000	    /* CAN Base Address			*/
-
-/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
-#define CONFIG_SYS_EBC_PB0AP		0x92015480
-#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization		*/
-#define CONFIG_SYS_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CONFIG_SYS_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
-
-/*
- * FPGA stuff
- */
-#define CONFIG_SYS_XSVF_DEFAULT_ADDR	0xfffc0000
-
-/* FPGA program pin configuration */
-#define CONFIG_SYS_FPGA_PRG		0x04000000  /* JTAG TMS pin (ppc output)     */
-#define CONFIG_SYS_FPGA_CLK		0x02000000  /* JTAG TCK pin (ppc output)     */
-#define CONFIG_SYS_FPGA_DATA		0x01000000  /* JTAG TDO->TDI data pin (ppc output) */
-#define CONFIG_SYS_FPGA_INIT		0x00010000  /* unused (ppc input)	     */
-#define CONFIG_SYS_FPGA_DONE		0x00008000  /* JTAG TDI->TDO pin (ppc input) */
-
-/*
- * Definitions for initial stack pointer and data area (in data cache)
- */
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CONFIG_SYS_TEMP_STACK_OCM	  1
-
-/* On Chip Memory location */
-#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
-#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
-
-#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/*
- * Definitions for GPIO setup (PPC405EP specific)
- *
- * GPIO0[0]	- External Bus Controller BLAST output
- * GPIO0[1-9]	- Instruction trace outputs -> GPIO
- * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
- * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
- * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
- * GPIO0[24-27] - UART0 control signal inputs/outputs
- * GPIO0[28-29] - UART1 data signal input/output
- * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
- */
-/* GPIO Input:		OSR=00, ISR=00, TSR=00, TCR=0 */
-/* GPIO Output:		OSR=00, ISR=00, TSR=00, TCR=1 */
-/* Alt. Funtion Input:	OSR=00, ISR=01, TSR=00, TCR=0 */
-/* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */
-#define CONFIG_SYS_GPIO0_OSRL		0x40000500  /*	0 ... 15 */
-#define CONFIG_SYS_GPIO0_OSRH		0x00000110  /* 16 ... 31 */
-#define CONFIG_SYS_GPIO0_ISR1L		0x00000000  /*	0 ... 15 */
-#define CONFIG_SYS_GPIO0_ISR1H		0x14000045  /* 16 ... 31 */
-#define CONFIG_SYS_GPIO0_TSRL		0x00000000  /*	0 ... 15 */
-#define CONFIG_SYS_GPIO0_TSRH		0x00000000  /* 16 ... 31 */
-#define CONFIG_SYS_GPIO0_TCR		0xF7FE0014  /*	0 ... 31 */
-
-/*
- * Default speed selection (cpu_plb_opb_ebc) in mhz.
- * This value will be set if iic boot eprom is disabled.
- */
-#define PLLMR0_DEFAULT	 PLLMR0_133_66_66_33
-#define PLLMR1_DEFAULT	 PLLMR1_133_66_66_33
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/acadia.h b/include/configs/acadia.h
deleted file mode 100644
index 0be310d4a3..0000000000
--- a/include/configs/acadia.h
+++ /dev/null
@@ -1,249 +0,0 @@
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/************************************************************************
- * acadia.h - configuration for AMCC Acadia (405EZ)
- ***********************************************************************/
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- *----------------------------------------------------------------------*/
-#define CONFIG_ACADIA		1		/* Board is Acadia	*/
-#define CONFIG_405EZ		1		/* Specifc 405EZ support*/
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE	0xFFF80000
-#endif
-
-/*
- * Include common defines/options for all AMCC eval boards
- */
-#define CONFIG_HOSTNAME		acadia
-#include "amcc-common.h"
-
-/* Detect Acadia PLL input clock automatically via CPLD bit		*/
-#define CONFIG_SYS_CLK_FREQ    ((in8(CONFIG_SYS_CPLD_BASE + 0) == 0x0c) ? \
-				66666666 : 33333000)
-
-#define CONFIG_MISC_INIT_F	1		/* Call misc_init_f	*/
-
-#define CONFIG_NO_SERIAL_EEPROM
-/*#undef CONFIG_NO_SERIAL_EEPROM*/
-
-#ifdef CONFIG_NO_SERIAL_EEPROM
-/*----------------------------------------------------------------------------
- * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
- * assuming a 66MHz input clock to the 405EZ.
- *---------------------------------------------------------------------------*/
-/* #define PLLMR0_100_100_12 */
-#define PLLMR0_200_133_66
-/* #define PLLMR0_266_160_80 */
-/* #define PLLMR0_333_166_83 */
-#endif
-
-/*-----------------------------------------------------------------------
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_FLASH_BASE		0xfe000000
-#define CONFIG_SYS_CPLD_BASE		0x80000000
-#define CONFIG_SYS_NAND_ADDR		0xd0000000
-#define CONFIG_SYS_USB_HOST		0xef603000	/* USB OHCI 1.1 controller	*/
-
-/*-----------------------------------------------------------------------
- * Initial RAM & stack pointer
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_TEMP_STACK_OCM	1		/* OCM as init ram	*/
-
-/* On Chip Memory location */
-#define CONFIG_SYS_OCM_DATA_ADDR	0xf8000000
-#define CONFIG_SYS_OCM_DATA_SIZE	0x4000			/* 16K of onchip SRAM		*/
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR	/* inside of SRAM		*/
-#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE	/* Size of used area in RAM	*/
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Serial Port
- *----------------------------------------------------------------------*/
-#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
-#undef	CONFIG_SYS_EXT_SERIAL_CLOCK			/* external serial clock */
-#define CONFIG_SYS_BASE_BAUD		691200
-
-/*-----------------------------------------------------------------------
- * Environment
- *----------------------------------------------------------------------*/
-#define CONFIG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
-
-/*-----------------------------------------------------------------------
- * FLASH related
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_FLASH_CFI			/* The flash is CFI compatible	*/
-#define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/
-
-#define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE}
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
-#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE	0x40000 /* size of one complete sector	*/
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
-#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
-
-/* Address and size of Redundant Environment Sector	*/
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
-#endif
-
-/*-----------------------------------------------------------------------
- * RAM (CRAM)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MBYTES_RAM		64		/* 64MB			*/
-
-/*-----------------------------------------------------------------------
- * I2C
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR	(0xa8>>1)
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-/*-----------------------------------------------------------------------
- * Ethernet
- *----------------------------------------------------------------------*/
-#define	CONFIG_PHY_ADDR		0	/* PHY address			*/
-#define CONFIG_HAS_ETH0		1
-
-/*
- * Default environment variables
- */
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	CONFIG_AMCC_DEF_ENV						\
-	CONFIG_AMCC_DEF_ENV_POWERPC					\
-	CONFIG_AMCC_DEF_ENV_PPC_OLD					\
-	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
-	"kernel_addr=fff10000\0"					\
-	"ramdisk_addr=fff20000\0"					\
-	"kozio=bootm ffc60000\0"					\
-	""
-
-#define CONFIG_USB_OHCI
-
-/* Partitions */
-
-#define CONFIG_SUPPORT_VFAT
-
-/*
- * Commands additional to the ones defined in amcc-common.h
- */
-#define CONFIG_CMD_NAND
-
-/*-----------------------------------------------------------------------
- * NAND FLASH
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MAX_NAND_DEVICE	1
-#define CONFIG_SYS_NAND_BASE		(CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
-#define CONFIG_SYS_NAND_SELECT_DEVICE  1	/* nand driver supports mutipl. chips	*/
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_NAND_CS		3
-/* Memory Bank 0 (Flash) initialization						*/
-#define CONFIG_SYS_EBC_PB0AP		0x03337200
-#define CONFIG_SYS_EBC_PB0CR		0xfe0bc000
-
-/* Memory Bank 3 (NAND-FLASH) initialization					*/
-#define CONFIG_SYS_EBC_PB3AP		0x018003c0
-#define CONFIG_SYS_EBC_PB3CR		(CONFIG_SYS_NAND_ADDR | 0x1c000)
-
-/* Just initial configuration for CRAM. Will be changed in memory.c to sync mode*/
-/* Memory Bank 1 (CRAM) initialization						*/
-#define CONFIG_SYS_EBC_PB1AP		0x030400c0
-#define CONFIG_SYS_EBC_PB1CR		0x000bc000
-
-/* Memory Bank 2 (CRAM) initialization						*/
-#define CONFIG_SYS_EBC_PB2AP		0x030400c0
-#define CONFIG_SYS_EBC_PB2CR		0x020bc000
-
-/* Memory Bank 4 (CPLD) initialization						*/
-#define CONFIG_SYS_EBC_PB4AP		0x04006000
-#define CONFIG_SYS_EBC_PB4CR		(CONFIG_SYS_CPLD_BASE | 0x18000)
-
-#define CONFIG_SYS_EBC_CFG		0xf8400000
-
-/*-----------------------------------------------------------------------
- * GPIO Setup
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_GPIO_CRAM_CLK	8
-#define CONFIG_SYS_GPIO_CRAM_WAIT	9		/* GPIO-In		*/
-#define CONFIG_SYS_GPIO_CRAM_ADV	10
-#define CONFIG_SYS_GPIO_CRAM_CRE	(32 + 21)	/* GPIO-Out		*/
-
-/*-----------------------------------------------------------------------
- * Definitions for GPIO_0 setup (PPC405EZ specific)
- *
- * GPIO0[0-2]	- External Bus Controller CS_4 - CS_6 Outputs
- * GPIO0[3]	- NAND FLASH Controller CE3 (NFCE3) Output
- * GPIO0[4]	- External Bus Controller Hold Input
- * GPIO0[5]	- External Bus Controller Priority Input
- * GPIO0[6]	- External Bus Controller HLDA Output
- * GPIO0[7]	- External Bus Controller Bus Request Output
- * GPIO0[8]	- CRAM Clk Output
- * GPIO0[9]	- External Bus Controller Ready Input
- * GPIO0[10]	- CRAM Adv Output
- * GPIO0[11-24]	- NAND Flash Control Data -> Bypasses GPIO when enabled
- * GPIO0[25]	- External DMA Request Input
- * GPIO0[26]	- External DMA EOT I/O
- * GPIO0[25]	- External DMA Ack_n Output
- * GPIO0[17-23]	- External Interrupts IRQ0 - IRQ6 inputs
- * GPIO0[28-30]	- Trace Outputs / PWM Inputs
- * GPIO0[31]	- PWM_8 I/O
- */
-#define CONFIG_SYS_GPIO0_TCR		0xC0A00000
-#define CONFIG_SYS_GPIO0_OSRL		0x50004400
-#define CONFIG_SYS_GPIO0_OSRH		0x02000055
-#define CONFIG_SYS_GPIO0_ISR1L		0x00001000
-#define CONFIG_SYS_GPIO0_ISR1H		0x00000055
-#define CONFIG_SYS_GPIO0_TSRL		0x02000000
-#define CONFIG_SYS_GPIO0_TSRH		0x00000055
-
-/*-----------------------------------------------------------------------
- * Definitions for GPIO_1 setup (PPC405EZ specific)
- *
- * GPIO1[0-6]	- PWM_9 to PWM_15 I/O
- * GPIO1[7]	- PWM_DIV_CLK (Out) / IRQ4 Input
- * GPIO1[8]	- TS5 Output / DAC_IP_TRIG Input
- * GPIO1[9]	- TS6 Output / ADC_IP_TRIG Input
- * GPIO1[10-12]	- UART0 Control Inputs
- * GPIO1[13]	- UART0_DTR_N Output/IEEE_1588_TS Output/TMRCLK Input
- * GPIO1[14]	- UART0_RTS_N Output/SPI_SS_2_N Output
- * GPIO1[15]	- SPI_SS_3_N Output/UART0_RI_N Input
- * GPIO1[16]	- SPI_SS_1_N Output
- * GPIO1[17-20]	- Trace Output/External Interrupts IRQ0 - IRQ3 inputs
- */
-#define CONFIG_SYS_GPIO1_TCR		0xFFFF8414
-#define CONFIG_SYS_GPIO1_OSRL		0x40000110
-#define CONFIG_SYS_GPIO1_OSRH		0x55455555
-#define CONFIG_SYS_GPIO1_ISR1L		0x15555445
-#define CONFIG_SYS_GPIO1_ISR1H		0x00000000
-#define CONFIG_SYS_GPIO1_TSRL		0x00000000
-#define CONFIG_SYS_GPIO1_TSRH		0x00000000
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h
deleted file mode 100644
index 450a2ebc11..0000000000
--- a/include/configs/amcc-common.h
+++ /dev/null
@@ -1,226 +0,0 @@
-/*
- * (C) Copyright 2008, 2009
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * Common configuration options for all AMCC boards
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __AMCC_COMMON_H
-#define __AMCC_COMMON_H
-
-#define CONFIG_SYS_SDRAM_BASE		0x00000000	/* _must_ be 0		*/
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* Start of U-Boot	*/
-#define CONFIG_SYS_MONITOR_LEN		(0xFFFFFFFF - CONFIG_SYS_MONITOR_BASE + 1)
-#define CONFIG_SYS_MALLOC_LEN		(1 << 20)	/* Reserved for malloc	*/
-
-/*
- * UART
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#ifndef CONFIG_DM_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
-#endif
-#define CONFIG_SYS_BAUDRATE_TABLE  \
-    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
-
-/*
- * Ethernet/EMAC/PHY
- */
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII			/* MII PHY management		*/
-#define CONFIG_NETCONSOLE		/* include NetConsole support	*/
-#if defined(CONFIG_440)
-#define CONFIG_SYS_RX_ETH_BUFFER	32	/* number of eth rx buffers	*/
-#else
-#define CONFIG_SYS_RX_ETH_BUFFER	16	/* number of eth rx buffers	*/
-#endif
-
-/*
- * Commands
- */
-#if defined(CONFIG_440)
-#endif
-#define CONFIG_CMD_REGINFO
-
-/*
- * Miscellaneous configurable options
- */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
-#else
-#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size	*/
-#endif
-#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x0400000 /* memtest works on		*/
-#define CONFIG_SYS_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
-
-#define CONFIG_SYS_LOAD_ADDR		0x100000  /* default load address	*/
-#define CONFIG_SYS_EXTBDINFO			/* To use extended board_into (bd_t) */
-
-#define CONFIG_CMDLINE_EDITING		/* add command line history	*/
-#define CONFIG_AUTO_COMPLETE		/* add autocompletion support	*/
-#define CONFIG_MX_CYCLIC		/* enable mdc/mwc commands      */
-
-#define CONFIG_LOADS_ECHO		/* echo on for serial download	*/
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change	*/
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_SUBNETMASK
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 16 MB of memory, since this is
- * the maximum mapped by the 40x Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ		(16 << 20) /* Initial Memory map for Linux */
-#define CONFIG_SYS_BOOTM_LEN		(16 << 20) /* Increase max gunzip size */
-
-/*
- * Internal Definitions
- */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port*/
-#endif
-
-/* Update size in "reg" property of NOR FLASH device tree nodes */
-#define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
-
-/*
- * Booting and default environment
- */
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
-	"echo"
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-/*
- * Only very few boards have default console not on ttyS0 (like Taishan)
- */
-#if !defined(CONFIG_USE_TTY)
-#define CONFIG_USE_TTY	ttyS0
-#endif
-
-/*
- * Only very few boards have default netdev not set to eth0 (like Arches)
- */
-#if !defined(CONFIG_USE_NETDEV)
-#define CONFIG_USE_NETDEV	eth0
-#endif
-
-/*
- * Only some 4xx PPC's are equipped with an FPU
- */
-#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
-    defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define CONFIG_AMCC_DEF_ENV_ROOTPATH	"rootpath=/opt/eldk/ppc_4xxFP\0"
-#else
-#define CONFIG_AMCC_DEF_ENV_ROOTPATH	"rootpath=/opt/eldk/ppc_4xx\0"
-#endif
-
-/*
- * Only some boards need to extend the bootargs by some additional
- * parameters (like Makalu)
- */
-#if !defined(CONFIG_ADDMISC)
-#define CONFIG_ADDMISC	"addmisc=setenv bootargs ${bootargs}\0"
-#endif
-
-/*
- * General common environment variables shared on all AMCC eval boards
- */
-#define CONFIG_AMCC_DEF_ENV						\
-	"netdev=" __stringify(CONFIG_USE_NETDEV) "\0"				\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addtty=setenv bootargs ${bootargs}"				\
-		" console=" __stringify(CONFIG_USE_TTY) ",${baudrate}\0"	\
-	CONFIG_ADDMISC							\
-	"initrd_high=30000000\0"					\
-	"kernel_addr_r=1000000\0"					\
-	"fdt_addr_r=1800000\0"						\
-	"ramdisk_addr_r=1900000\0"					\
-	"hostname=" __stringify(CONFIG_HOSTNAME) "\0"				\
-	"bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0"			\
-	"ramdisk_file=" __stringify(CONFIG_HOSTNAME) "/uRamdisk\0"		\
-	CONFIG_AMCC_DEF_ENV_ROOTPATH
-
-/*
- * Default environment for arch/powerpc booting
- * for boards that are ported to arch/powerpc
- */
-#define CONFIG_AMCC_DEF_ENV_POWERPC					\
-	"flash_self=run ramargs addip addtty addmisc;"			\
-		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
-	"flash_nfs=run nfsargs addip addtty addmisc;"			\
-		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
-	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
-		"tftp ${fdt_addr_r} ${fdt_file}; "			\
-		"run nfsargs addip addtty addmisc;"			\
-		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
-	"net_self_load=tftp ${kernel_addr_r} ${bootfile};"		\
-		"tftp ${fdt_addr_r} ${fdt_file};"			\
-		"tftp ${ramdisk_addr_r} ${ramdisk_file};\0"		\
-	"net_self=run net_self_load;"					\
-		"run ramargs addip addtty addmisc;"			\
-		"bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0" \
-	"fdt_file=" __stringify(CONFIG_HOSTNAME) "/" __stringify(CONFIG_HOSTNAME) ".dtb\0"
-
-/*
- * Default environment for arch/ppc booting,
- * for boards that are not ported to arch/powerpc yet
- */
-#define CONFIG_AMCC_DEF_ENV_PPC						\
-	"flash_self=run ramargs addip addtty addmisc;"			\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"flash_nfs=run nfsargs addip addtty addmisc;"			\
-		"bootm ${kernel_addr}\0"				\
-	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
-		"run nfsargs addip addtty addmisc;"			\
-		"bootm ${kernel_addr_r}\0"
-
-/*
- * Default environment for arch/ppc booting (old version),
- * for boards that are ported to arch/ppc and arch/powerpc
- */
-#define CONFIG_AMCC_DEF_ENV_PPC_OLD					\
-	"flash_self_old=run ramargs addip addtty addmisc;"		\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"flash_nfs_old=run nfsargs addip addtty addmisc;"		\
-		"bootm ${kernel_addr}\0"				\
-	"net_nfs_old=tftp ${kernel_addr_r} ${bootfile};"		\
-		"run nfsargs addip addtty addmisc;"			\
-		"bootm ${kernel_addr_r}\0"
-
-#define CONFIG_AMCC_DEF_ENV_NOR_UPD					\
-	"u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0"		\
-	"load=tftp 200000 ${u-boot}\0"					\
-	"update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) " FFFFFFFF;"	\
-		"era " __stringify(CONFIG_SYS_MONITOR_BASE) " FFFFFFFF;"	\
-		"cp.b ${fileaddr} " __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
-	"upd=run load update\0"						\
-
-#endif /* __AMCC_COMMON_H */
diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h
deleted file mode 100644
index 8868deb1c1..0000000000
--- a/include/configs/bamboo.h
+++ /dev/null
@@ -1,211 +0,0 @@
-/*
- * (C) Copyright 2005-2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/************************************************************************
- * bamboo.h - configuration for BAMBOO board
- ***********************************************************************/
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- *----------------------------------------------------------------------*/
-#define CONFIG_BAMBOO		1	/* Board is BAMBOO              */
-#define CONFIG_440EP		1	/* Specific PPC440EP support    */
-#define CONFIG_440		1	/* ... PPC440 family	        */
-#define CONFIG_SYS_CLK_FREQ	33333333    /* external freq to pll	*/
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE	0xFFFA0000
-#endif
-
-/*
- * Include common defines/options for all AMCC eval boards
- */
-#define CONFIG_HOSTNAME		bamboo
-#include "amcc-common.h"
-
-/* Reclaim some space. */
-#undef CONFIG_SYS_LONGHELP
-
-/*
- * Please note that, if NAND support is enabled, the 2nd ethernet port
- * can't be used because of pin multiplexing. So, if you want to use the
- * 2nd ethernet port you have to "undef" the following define.
- */
-#define CONFIG_BAMBOO_NAND      1       /* enable nand flash support    */
-
-/*-----------------------------------------------------------------------
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_FLASH_BASE	        0xfff00000	    /* start of FLASH	*/
-#define CONFIG_SYS_PCI_MEMBASE	        0xa0000000	    /* mapped pci memory*/
-#define CONFIG_SYS_PCI_MEMBASE1        CONFIG_SYS_PCI_MEMBASE  + 0x10000000
-#define CONFIG_SYS_PCI_MEMBASE2        CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
-#define CONFIG_SYS_PCI_MEMBASE3        CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
-
-/*Don't change either of these*/
-#define CONFIG_SYS_PCI_BASE		0xe0000000	    /* internal PCI regs*/
-/*Don't change either of these*/
-
-#define CONFIG_SYS_USB_DEVICE          0x50000000
-#define CONFIG_SYS_NVRAM_BASE_ADDR     0x80000000
-#define CONFIG_SYS_BOOT_BASE_ADDR      0xf0000000
-#define CONFIG_SYS_NAND_ADDR           0x90000000
-#define CONFIG_SYS_NAND2_ADDR          0x94000000
-
-/*-----------------------------------------------------------------------
- * Initial RAM & stack pointer (placed in SDRAM)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_INIT_RAM_DCACHE	1		/* d-cache as init ram	*/
-#define CONFIG_SYS_INIT_RAM_ADDR	0x70000000	/* DCache       */
-#define CONFIG_SYS_INIT_RAM_SIZE	(4 << 10)
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Serial Port
- *----------------------------------------------------------------------*/
-#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
-#define CONFIG_SYS_EXT_SERIAL_CLOCK	11059200 /* use external 11.059MHz clk	*/
-
-/*-----------------------------------------------------------------------
- * NVRAM/RTC
- *
- * NOTE: The RTC registers are located at 0x7FFF0 - 0x7FFFF
- * The DS1558 code assumes this condition
- *
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_NVRAM_SIZE	        (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs     */
-#define CONFIG_RTC_DS1556	1		         /* DS1556 RTC		*/
-
-/*-----------------------------------------------------------------------
- * Environment
- *----------------------------------------------------------------------*/
-#define CONFIG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
-
-/*-----------------------------------------------------------------------
- * FLASH related
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MAX_FLASH_BANKS	3	/* number of banks			*/
-#define CONFIG_SYS_MAX_FLASH_SECT	256	/* sectors per device			*/
-
-#undef	CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define CONFIG_SYS_FLASH_ADDR0         0x555
-#define CONFIG_SYS_FLASH_ADDR1         0x2aa
-#define CONFIG_SYS_FLASH_WORD_SIZE     unsigned char
-
-#define CONFIG_SYS_FLASH_2ND_16BIT_DEV 1	/* bamboo has 8 and 16bit device	*/
-#define CONFIG_SYS_FLASH_2ND_ADDR      0x87800000  /* bamboo has 8 and 16bit device	*/
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE	0x10000	/* size of one complete sector		*/
-#define CONFIG_ENV_ADDR		((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
-#define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
-
-/* Address and size of Redundant Environment Sector	*/
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
-#endif /* CONFIG_ENV_IS_IN_FLASH */
-
-/*-----------------------------------------------------------------------
- * NAND FLASH
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MAX_NAND_DEVICE	2
-#define CONFIG_SYS_NAND_BASE		(CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
-#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_ADDR + 2 }
-#define CONFIG_SYS_NAND_SELECT_DEVICE  1	/* nand driver supports mutipl. chips	*/
-#define CONFIG_SYS_NAND_CS		1
-
-/*-----------------------------------------------------------------------
- * DDR SDRAM
- *----------------------------------------------------------------------------- */
-#define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for setup             */
-#undef CONFIG_DDR_ECC			/* don't use ECC			*/
-#define CONFIG_SYS_SIMULATE_SPD_EEPROM	0xff	/* simulate spd eeprom on this address	*/
-#define SPD_EEPROM_ADDRESS	{CONFIG_SYS_SIMULATE_SPD_EEPROM, 0x50, 0x51}
-#define CONFIG_SYS_MBYTES_SDRAM	(64)	/* 64MB fixed size for early-sdram-init */
-#define CONFIG_PROG_SDRAM_TLB
-
-/*-----------------------------------------------------------------------
- * I2C
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR	(0xa8>>1)
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-#ifdef CONFIG_ENV_IS_IN_EEPROM
-#define CONFIG_ENV_SIZE		0x200	    /* Size of Environment vars */
-#define CONFIG_ENV_OFFSET		0x0
-#endif /* CONFIG_ENV_IS_IN_EEPROM */
-
-/*
- * Default environment variables
- */
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	CONFIG_AMCC_DEF_ENV						\
-	CONFIG_AMCC_DEF_ENV_POWERPC					\
-	CONFIG_AMCC_DEF_ENV_PPC_OLD					\
-	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
-	"kernel_addr=fff00000\0"					\
-	"ramdisk_addr=fff10000\0"					\
-	""
-
-#define CONFIG_HAS_ETH0
-#define CONFIG_PHY_ADDR		0	/* PHY address, See schematics	*/
-#define CONFIG_PHY1_ADDR        1
-
-#ifndef CONFIG_BAMBOO_NAND
-#define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"	*/
-#endif /* CONFIG_BAMBOO_NAND */
-
-#ifdef CONFIG_440EP
-/* USB */
-#define CONFIG_USB_OHCI
-
-/*Comment this out to enable USB 1.1 device*/
-#define USB_2_0_DEVICE
-#endif /*CONFIG_440EP*/
-
-/*
- * Commands additional to the ones defined in amcc-common.h
- */
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_SDRAM
-
-#ifdef CONFIG_BAMBOO_NAND
-#define CONFIG_CMD_NAND
-#endif
-
-#define CONFIG_SUPPORT_VFAT
-
-/* Partitions */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-/* General PCI */
-#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
-#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
-#define CONFIG_SYS_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/
-
-/* Board-specific PCI */
-#define CONFIG_SYS_PCI_TARGET_INIT
-#define CONFIG_SYS_PCI_MASTER_INIT
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
-#define CONFIG_SYS_PCI_SUBSYS_ID       0xcafe	/* Whatever */
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/bubinga.h b/include/configs/bubinga.h
deleted file mode 100644
index 7274b2d4fe..0000000000
--- a/include/configs/bubinga.h
+++ /dev/null
@@ -1,299 +0,0 @@
-/*
- * (C) Copyright 2000-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_BUBINGA	        1	/* ...on a BUBINGA board	*/
-
-#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
-
-/*
- * Include common defines/options for all AMCC eval boards
- */
-#define CONFIG_HOSTNAME		bubinga
-#include "amcc-common.h"
-
-#define CONFIG_SYS_CLK_FREQ     33333333 /* external frequency to pll   */
-
-#define CONFIG_NO_SERIAL_EEPROM
-/*#undef CONFIG_NO_SERIAL_EEPROM*/
-/*----------------------------------------------------------------------------*/
-#ifdef CONFIG_NO_SERIAL_EEPROM
-
-/*
-!-------------------------------------------------------------------------------
-! Defines for entry options.
-! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
-!       are plugged in the board will be utilized as non-ECC DIMMs.
-!-------------------------------------------------------------------------------
-*/
-#define        AUTO_MEMORY_CONFIG
-#define        DIMM_READ_ADDR 0xAB
-#define        DIMM_WRITE_ADDR 0xAA
-
-/*
-!-------------------------------------------------------------------------------
-! PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
-! assuming a 33MHz input clock to the 405EP from the C9531.
-!-------------------------------------------------------------------------------
-*/
-#define PLLMR0_DEFAULT   PLLMR0_266_133_66
-#define PLLMR1_DEFAULT   PLLMR1_266_133_66
-
-#endif
-/*----------------------------------------------------------------------------*/
-
-/*
- * Define here the location of the environment variables (FLASH or NVRAM).
- * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
- *       supported for backward compatibility.
- */
-#if 1
-#define CONFIG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
-#else
-#define CONFIG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
-#endif
-
-/*
- * Default environment variables
- */
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	CONFIG_AMCC_DEF_ENV						\
-	CONFIG_AMCC_DEF_ENV_PPC						\
-	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
-	"kernel_addr=fff80000\0"					\
-	"ramdisk_addr=fff90000\0"					\
-	""
-
-#define	CONFIG_PHY_ADDR		1	/* PHY address			*/
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#define CONFIG_PHY1_ADDR	2	/* EMAC1 PHY address		*/
-
-#define CONFIG_RTC_DS174x	1	/* use DS1743 RTC in Bubinga	*/
-
-/*
- * Commands additional to the ones defined in amcc-common.h
- */
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_SDRAM
-
-#define CONFIG_SPD_EEPROM      1       /* use SPD EEPROM for setup    */
-
-/*
- * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
- * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
- * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
- * The Linux BASE_BAUD define should match this configuration.
- *    baseBaud = cpuClock/(uartDivisor*16)
- * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
- * set Linux BASE_BAUD to 403200.
- */
-#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
-#undef  CONFIG_SYS_EXT_SERIAL_CLOCK           /* external serial clock */
-#undef  CONFIG_SYS_405_UART_ERRATA_59         /* 405GP/CR Rev. D silicon */
-#define CONFIG_SYS_BASE_BAUD       691200
-
-/*-----------------------------------------------------------------------
- * I2C stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
-
-#define CONFIG_SYS_I2C_NOPROBES	{ {0, 0x69} }	/* avoid i2c probe hangup (?) */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	6	/* 24C02 requires 5ms delay */
-
-#if defined(CONFIG_CMD_EEPROM)
-#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* I2C boot EEPROM (24C02W)	*/
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address		*/
-#endif
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0              /* configure ar pci adapter     */
-#define PCI_HOST_FORCE  1               /* configure as pci host        */
-#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
-
-#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
-#define CONFIG_PCI_HOST	PCI_HOST_FORCE  /* select pci host function     */
-					/* resource configuration       */
-#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */
-#define CONFIG_SYS_PCI_CLASSCODE       0x0600  /* PCI Class Code: bridge/host  */
-#define CONFIG_SYS_PCI_PTM1LA  0x00000000      /* point to sdram               */
-#define CONFIG_SYS_PCI_PTM1MS  0x80000001      /* 2GB, enable hard-wired to 1  */
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
-#define CONFIG_SYS_PCI_PTM2LA  0x00000000      /* disabled                     */
-#define CONFIG_SYS_PCI_PTM2MS  0x00000000      /* disabled                     */
-#define CONFIG_SYS_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
-
-/*-----------------------------------------------------------------------
- * External peripheral base address
- *-----------------------------------------------------------------------
- */
-#define	CONFIG_SYS_KEY_REG_BASE_ADDR	0xF0100000
-#define	CONFIG_SYS_IR_REG_BASE_ADDR	0xF0200000
-#define	CONFIG_SYS_FPGA_REG_BASE_ADDR	0xF0300000
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- */
-#define CONFIG_SYS_SRAM_BASE		0xFFF00000
-#define CONFIG_SYS_SRAM_SIZE		(256 << 10)
-#define CONFIG_SYS_FLASH_BASE		0xFFF80000
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define CONFIG_SYS_FLASH_ADDR0         0x5555
-#define CONFIG_SYS_FLASH_ADDR1         0x2aaa
-#define CONFIG_SYS_FLASH_WORD_SIZE     unsigned char
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE	0x10000	/* size of one complete sector	*/
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
-#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
-
-/* Address and size of Redundant Environment Sector	*/
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
-#endif /* CONFIG_ENV_IS_IN_FLASH */
-
-/*-----------------------------------------------------------------------
- * NVRAM organization
- */
-#define CONFIG_SYS_NVRAM_BASE_ADDR	0xf0000000	/* NVRAM base address	*/
-#define CONFIG_SYS_NVRAM_SIZE		0x1ff8		/* NVRAM size	*/
-
-#ifdef CONFIG_ENV_IS_IN_NVRAM
-#define CONFIG_ENV_SIZE		0x0ff8		/* Size of Environment vars	*/
-#define CONFIG_ENV_ADDR		\
-	(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE)	/* Env	*/
-#endif
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	CONFIG_SYS_FLASH_BASE	/* FLASH bank #0	*/
-#define FLASH_BASE1_PRELIM	0		/* FLASH bank #1	*/
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in data cache)
- */
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CONFIG_SYS_TEMP_STACK_OCM        1
-
-/* On Chip Memory location */
-#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
-#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
-
-#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (Flash/SRAM) initialization                                    */
-#define CONFIG_SYS_EBC_PB0AP           0x04006000
-#define CONFIG_SYS_EBC_PB0CR           0xFFF18000  /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit  */
-
-/* Memory Bank 1 (NVRAM/RTC) initialization                                     */
-#define CONFIG_SYS_EBC_PB1AP           0x04041000
-#define CONFIG_SYS_EBC_PB1CR           0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
-
-/* Memory Bank 2 (not used) initialization                                      */
-#define CONFIG_SYS_EBC_PB2AP           0x00000000
-#define CONFIG_SYS_EBC_PB2CR           0x00000000
-
-/* Memory Bank 2 (not used) initialization                                      */
-#define CONFIG_SYS_EBC_PB3AP           0x00000000
-#define CONFIG_SYS_EBC_PB3CR           0x00000000
-
-/* Memory Bank 4 (FPGA regs) initialization                                     */
-#define CONFIG_SYS_EBC_PB4AP           0x01815000
-#define CONFIG_SYS_EBC_PB4CR           0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit  */
-
-/*-----------------------------------------------------------------------
- * Definitions for Serial Presence Detect EEPROM address
- * (to get SDRAM settings)
- */
-#define SPD_EEPROM_ADDRESS      0x55
-
-/*-----------------------------------------------------------------------
- * Definitions for GPIO setup (PPC405EP specific)
- *
- * GPIO0[0]     - External Bus Controller BLAST output
- * GPIO0[1-9]   - Instruction trace outputs
- * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
- * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
- * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
- * GPIO0[24-27] - UART0 control signal inputs/outputs
- * GPIO0[28-29] - UART1 data signal input/output
- * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
- */
-#define CONFIG_SYS_GPIO0_OSRL          0x55555555
-#define CONFIG_SYS_GPIO0_OSRH          0x40000110
-#define CONFIG_SYS_GPIO0_ISR1L         0x00000000
-#define CONFIG_SYS_GPIO0_ISR1H         0x15555445
-#define CONFIG_SYS_GPIO0_TSRL          0x00000000
-#define CONFIG_SYS_GPIO0_TSRH          0x00000000
-#define CONFIG_SYS_GPIO0_TCR           0xFFFF8014
-
-/*-----------------------------------------------------------------------
- * Some BUBINGA stuff...
- */
-#define NVRAM_BASE      0xF0000000
-#define FPGA_REG0       0xF0300000    /* FPGA Reg 0              */
-#define FPGA_REG1       0xF0300001    /* FPGA Reg 1              */
-#define NVRVFY1     0x4f532d4f    /* used to determine if state data in */
-#define NVRVFY2     0x50454e00    /* NVRAM initialized (ascii for OS-OPEN)*/
-
-#define FPGA_REG0_F_RANGE     0x80       /* SDRAM PLL freq range              */
-#define FPGA_REG0_EXT_INT_DIS 0x20       /* External interface disable        */
-#define FPGA_REG0_LED_MASK    0x07       /* Board LEDs DS9, DS10, and DS11    */
-#define FPGA_REG0_LED0        0x04       /* Turn on LED0                      */
-#define FPGA_REG0_LED1        0x02       /* Turn on LED1                      */
-#define FPGA_REG0_LED2        0x01       /* Turn on LED2                      */
-
-#define FPGA_REG1_SSPEC_DIS   0x80       /* C9531 Spread Spectrum disabled    */
-#define FPGA_REG1_OFFBD_PCICLK 0x40      /* Onboard PCI clock selected       */
-#define FPGA_REG1_CLOCK_MASK  0x30       /* Mask for C9531 output freq select */
-#define FPGA_REG1_CLOCK_BIT_SHIFT  4
-#define FPGA_REG1_PCI_INT_ARB 0x08       /* PCI Internal arbiter selected     */
-#define FPGA_REG1_PCI_FREQ    0x04       /* PCI Frequency select              */
-#define FPGA_REG1_OFFB_FLASH  0x02       /* Off board flash                   */
-#define FPGA_REG1_SRAM_BOOT   0x01       /* SRAM at 0xFFF80000 not Flash      */
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h
deleted file mode 100644
index b495d0645b..0000000000
--- a/include/configs/canyonlands.h
+++ /dev/null
@@ -1,645 +0,0 @@
-/*
- * (C) Copyright 2008
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/************************************************************************
- * canyonlands.h - configuration for Canyonlands (460EX)
- ***********************************************************************/
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/kconfig.h>
-
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- *----------------------------------------------------------------------*/
-/*
- * This config file is used for Canyonlands (460EX) Glacier (460GT)
- * and Arches dual (460GT)
- */
-#ifdef CONFIG_CANYONLANDS
-#define CONFIG_460EX			/* Specific PPC460EX		*/
-#define CONFIG_HOSTNAME		canyonlands
-#else
-#define CONFIG_460GT			/* Specific PPC460GT		*/
-#ifdef CONFIG_GLACIER
-#define CONFIG_HOSTNAME		glacier
-#else
-#define CONFIG_HOSTNAME		arches
-#define CONFIG_USE_NETDEV	eth1
-#define CONFIG_BD_NUM_CPUS	2
-#endif
-#endif
-
-#define CONFIG_440
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE	0xFFF80000
-#endif
-
-/*
- * Include common defines/options for all AMCC eval boards
- */
-#include "amcc-common.h"
-
-#define CONFIG_SYS_CLK_FREQ	66666667	/* external freq to pll	*/
-
-#define CONFIG_BOARD_EARLY_INIT_R		/* Call board_early_init_r */
-#define CONFIG_MISC_INIT_R			/* Call misc_init_r */
-#define CONFIG_BOARD_TYPES			/* support board types */
-
-/*-----------------------------------------------------------------------
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_PCI_MEMBASE		0x80000000	/* mapped PCI memory	*/
-#define CONFIG_SYS_PCI_BASE		0xd0000000	/* internal PCI regs	*/
-#define CONFIG_SYS_PCI_TARGBASE	CONFIG_SYS_PCI_MEMBASE
-
-#define CONFIG_SYS_PCIE_MEMBASE	0xb0000000	/* mapped PCIe memory	*/
-#define CONFIG_SYS_PCIE_MEMSIZE	0x08000000	/* smallest incr for PCIe port */
-#define CONFIG_SYS_PCIE_BASE		0xc4000000	/* PCIe UTL regs */
-
-#define CONFIG_SYS_PCIE0_CFGBASE	0xc0000000
-#define CONFIG_SYS_PCIE1_CFGBASE	0xc1000000
-#define CONFIG_SYS_PCIE0_XCFGBASE	0xc3000000
-#define CONFIG_SYS_PCIE1_XCFGBASE	0xc3001000
-
-/*
- * BCSR bits as defined in the Canyonlands board user manual.
- */
-#define BCSR_USBCTRL_OTG_RST	0x32
-#define BCSR_USBCTRL_HOST_RST	0x01
-#define BCSR_SELECT_PCIE	0x10
-
-#define	CONFIG_SYS_PCIE0_UTLBASE	0xc08010000ULL	/* 36bit physical addr	*/
-
-/* base address of inbound PCIe window */
-#define CONFIG_SYS_PCIE_INBOUND_BASE	0x000000000ULL	/* 36bit physical addr	*/
-
-/* EBC stuff */
-#if !defined(CONFIG_ARCHES)
-#define CONFIG_SYS_BCSR_BASE		0xE1000000
-#define CONFIG_SYS_FLASH_BASE		0xFC000000	/* later mapped to this addr */
-#define CONFIG_SYS_FLASH_SIZE		(64 << 20)
-#else
-#define CONFIG_SYS_FPGA_BASE		0xE1000000
-#define CONFIG_SYS_CPLD_ADDR		(CONFIG_SYS_FPGA_BASE + 0x00080000)
-#define CONFIG_SYS_CPLD_DATA		(CONFIG_SYS_FPGA_BASE + 0x00080002)
-#define CONFIG_SYS_FLASH_BASE		0xFE000000	/* later mapped to this addr  */
-#define CONFIG_SYS_FLASH_SIZE		(32 << 20)
-#endif
-
-#define CONFIG_SYS_NAND_ADDR		0xE0000000
-#define CONFIG_SYS_BOOT_BASE_ADDR	0xFF000000	/* EBC Boot Space: 0xFF000000 */
-#define CONFIG_SYS_FLASH_BASE_PHYS_H	0x4
-#define CONFIG_SYS_FLASH_BASE_PHYS_L	0xCC000000
-#define CONFIG_SYS_FLASH_BASE_PHYS	(((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) |	\
-					 (u64)CONFIG_SYS_FLASH_BASE_PHYS_L)
-
-#define CONFIG_SYS_OCM_BASE		0xE3000000	/* OCM: 64k		*/
-#define CONFIG_SYS_SRAM_BASE		0xE8000000	/* SRAM: 256k		*/
-#define CONFIG_SYS_SRAM_SIZE		(256 << 10)
-#define CONFIG_SYS_LOCAL_CONF_REGS	0xEF000000
-
-#define CONFIG_SYS_AHB_BASE		0xE2000000	/* internal AHB peripherals	*/
-
-/*-----------------------------------------------------------------------
- * Initial RAM & stack pointer (placed in OCM)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_BASE	/* OCM			*/
-#define CONFIG_SYS_INIT_RAM_SIZE	(4 << 10)
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Serial Port
- *----------------------------------------------------------------------*/
-#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
-
-/*-----------------------------------------------------------------------
- * Environment
- *----------------------------------------------------------------------*/
-/*
- * Define here the location of the environment variables (FLASH).
- */
-#define	CONFIG_ENV_IS_IN_FLASH	1	/* use FLASH for environment vars */
-#define CONFIG_SYS_NOR_CS		0	/* NOR chip connected to CSx */
-#define CONFIG_SYS_NAND_CS		3	/* NAND chip connected to CSx */
-
-/*-----------------------------------------------------------------------
- * FLASH related
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_FLASH_CFI			/* The flash is CFI compatible	*/
-#define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/
-#define CONFIG_SYS_FLASH_CFI_AMD_RESET	/* Use AMD (Spansion) reset cmd */
-
-#define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE}
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
-#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE	0x20000		/* size of one complete sector	*/
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
-#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
-
-/* Address and size of Redundant Environment Sector	*/
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
-#endif /* CONFIG_ENV_IS_IN_FLASH */
-
-/*-----------------------------------------------------------------------
- * NAND-FLASH related
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MAX_NAND_DEVICE	1
-#define CONFIG_SYS_NAND_BASE		(CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
-#define CONFIG_SYS_NAND_SELECT_DEVICE  1	/* nand driver supports mutipl. chips	*/
-
-/*------------------------------------------------------------------------------
- * DDR SDRAM
- *----------------------------------------------------------------------------*/
-#if !defined(CONFIG_ARCHES)
-/*
- * NAND booting U-Boot version uses a fixed initialization, since the whole
- * I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot
- * code.
- */
-#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for setup	*/
-#define SPD_EEPROM_ADDRESS	{0x50, 0x51}	/* SPD i2c spd addresses*/
-#define CONFIG_DDR_ECC			/* with ECC support		*/
-#define CONFIG_DDR_RQDC_FIXED	0x80000038 /* fixed value for RQDC	*/
-
-#else /* defined(CONFIG_ARCHES) */
-
-#define CONFIG_AUTOCALIB	"silent\0"	/* default is non-verbose    */
-
-#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION	/* IBM DDR autocalibration   */
-#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION	/* dynamic DDR autocal debug */
-#undef CONFIG_PPC4xx_DDR_METHOD_A
-
-/* DDR1/2 SDRAM Device Control Register Data Values */
-/* Memory Queue */
-#define CONFIG_SYS_SDRAM_R0BAS		0x0000f000
-#define CONFIG_SYS_SDRAM_R1BAS		0x00000000
-#define CONFIG_SYS_SDRAM_R2BAS		0x00000000
-#define CONFIG_SYS_SDRAM_R3BAS		0x00000000
-#define CONFIG_SYS_SDRAM_PLBADDULL	0x00000000
-#define CONFIG_SYS_SDRAM_PLBADDUHB	0x00000008
-#define CONFIG_SYS_SDRAM_CONF1LL	0x00001080
-#define CONFIG_SYS_SDRAM_CONF1HB	0x00001080
-#define CONFIG_SYS_SDRAM_CONFPATHB	0x10a68000
-
-/* SDRAM Controller */
-#define CONFIG_SYS_SDRAM0_MB0CF		0x00000701
-#define CONFIG_SYS_SDRAM0_MB1CF		0x00000000
-#define CONFIG_SYS_SDRAM0_MB2CF		0x00000000
-#define CONFIG_SYS_SDRAM0_MB3CF		0x00000000
-#define CONFIG_SYS_SDRAM0_MCOPT1	0x05322000
-#define CONFIG_SYS_SDRAM0_MCOPT2	0x00000000
-#define CONFIG_SYS_SDRAM0_MODT0		0x01000000
-#define CONFIG_SYS_SDRAM0_MODT1		0x00000000
-#define CONFIG_SYS_SDRAM0_MODT2		0x00000000
-#define CONFIG_SYS_SDRAM0_MODT3		0x00000000
-#define CONFIG_SYS_SDRAM0_CODT		0x00800021
-#define CONFIG_SYS_SDRAM0_RTR		0x06180000
-#define CONFIG_SYS_SDRAM0_INITPLR0	0xb5380000
-#define CONFIG_SYS_SDRAM0_INITPLR1	0x82100400
-#define CONFIG_SYS_SDRAM0_INITPLR2	0x80820000
-#define CONFIG_SYS_SDRAM0_INITPLR3	0x80830000
-#define CONFIG_SYS_SDRAM0_INITPLR4	0x80810040
-#define CONFIG_SYS_SDRAM0_INITPLR5	0x80800532
-#define CONFIG_SYS_SDRAM0_INITPLR6	0x82100400
-#define CONFIG_SYS_SDRAM0_INITPLR7	0x8a080000
-#define CONFIG_SYS_SDRAM0_INITPLR8	0x8a080000
-#define CONFIG_SYS_SDRAM0_INITPLR9	0x8a080000
-#define CONFIG_SYS_SDRAM0_INITPLR10	0x8a080000
-#define CONFIG_SYS_SDRAM0_INITPLR11	0x80000432
-#define CONFIG_SYS_SDRAM0_INITPLR12	0x808103c0
-#define CONFIG_SYS_SDRAM0_INITPLR13	0x80810040
-#define CONFIG_SYS_SDRAM0_INITPLR14	0x00000000
-#define CONFIG_SYS_SDRAM0_INITPLR15	0x00000000
-#define CONFIG_SYS_SDRAM0_RQDC		0x80000038
-#define CONFIG_SYS_SDRAM0_RFDC		0x00000257
-#define CONFIG_SYS_SDRAM0_RDCC		0x40000000
-#define CONFIG_SYS_SDRAM0_DLCR		0x03000091
-#define CONFIG_SYS_SDRAM0_CLKTR		0x40000000
-#define CONFIG_SYS_SDRAM0_WRDTR		0x82000823
-#define CONFIG_SYS_SDRAM0_SDTR1		0x80201000
-#define CONFIG_SYS_SDRAM0_SDTR2		0x42204243
-#define CONFIG_SYS_SDRAM0_SDTR3		0x090c0d1a
-#define CONFIG_SYS_SDRAM0_MMODE		0x00000432
-#define CONFIG_SYS_SDRAM0_MEMODE	0x00000004
-#endif	/* !defined(CONFIG_ARCHES) */
-
-#define CONFIG_SYS_MBYTES_SDRAM	512	/* 512MB			*/
-
-/*-----------------------------------------------------------------------
- * I2C
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR		(0xa8>>1)
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
-
-/* I2C bootstrap EEPROM */
-#if defined(CONFIG_ARCHES)
-#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR	0x54
-#else
-#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR	0x52
-#endif
-#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET	0
-#define CONFIG_4xx_CONFIG_BLOCKSIZE		16
-
-#if !defined(CONFIG_ARCHES)
-/* RTC configuration */
-#define CONFIG_RTC_M41T62
-#define CONFIG_SYS_I2C_RTC_ADDR	0x68
-#endif
-
-/*-----------------------------------------------------------------------
- * Ethernet
- *----------------------------------------------------------------------*/
-#define CONFIG_IBM_EMAC4_V4
-
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-
-#if !defined(CONFIG_ARCHES)
-#define CONFIG_PHY_ADDR		0	/* PHY address, See schematics	*/
-#define CONFIG_PHY1_ADDR	1
-/* Only Glacier (460GT) has 4 EMAC interfaces */
-#ifdef CONFIG_460GT
-#define CONFIG_PHY2_ADDR	2
-#define CONFIG_PHY3_ADDR	3
-#define CONFIG_HAS_ETH2
-#define CONFIG_HAS_ETH3
-#endif
-
-#else /* defined(CONFIG_ARCHES) */
-
-#define CONFIG_FIXED_PHY	0xFFFFFFFF
-#define CONFIG_PHY_ADDR		CONFIG_FIXED_PHY
-#define CONFIG_PHY1_ADDR	0
-#define CONFIG_PHY2_ADDR	1
-#define CONFIG_HAS_ETH2
-
-#define CONFIG_SYS_FIXED_PHY_PORT(devnum, speed, duplex) \
-		{devnum, speed, duplex}
-#define CONFIG_SYS_FIXED_PHY_PORTS \
-		CONFIG_SYS_FIXED_PHY_PORT(0, 1000, FULL)
-
-#define CONFIG_M88E1112_PHY
-
-/*
- * For the GPCS_PHYx_ADDR PHY address, choose some PHY address not
- * used by CONFIG_PHYx_ADDR
- */
-#define CONFIG_GPCS_PHY_ADDR    0xA
-#define CONFIG_GPCS_PHY1_ADDR   0xB
-#define CONFIG_GPCS_PHY2_ADDR   0xC
-#endif	/* !defined(CONFIG_ARCHES) */
-
-#define CONFIG_PHY_RESET		/* reset phy upon startup	*/
-#define CONFIG_PHY_GIGE			/* Include GbE speed/duplex detection */
-#define CONFIG_PHY_DYNAMIC_ANEG
-
-/*-----------------------------------------------------------------------
- * USB-OHCI
- *----------------------------------------------------------------------*/
-/* Only Canyonlands (460EX) has USB */
-#ifdef CONFIG_460EX
-#define CONFIG_USB_OHCI_NEW
-#undef CONFIG_SYS_OHCI_BE_CONTROLLER		/* 460EX has little endian descriptors	*/
-#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS	/* 460EX has little endian register	*/
-#define CONFIG_SYS_OHCI_USE_NPS		/* force NoPowerSwitching mode		*/
-#define CONFIG_SYS_USB_OHCI_REGS_BASE	(CONFIG_SYS_AHB_BASE | 0xd0000)
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"ppc440"
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
-#define CONFIG_SYS_USB_OHCI_BOARD_INIT
-#endif
-
-/*
- * Default environment variables
- */
-#if !defined(CONFIG_ARCHES)
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	CONFIG_AMCC_DEF_ENV						\
-	CONFIG_AMCC_DEF_ENV_POWERPC					\
-	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
-	"kernel_addr=fc000000\0"					\
-	"fdt_addr=fc1e0000\0"						\
-	"ramdisk_addr=fc200000\0"					\
-	"pciconfighost=1\0"						\
-	"pcie_mode=RP:RP\0"						\
-	""
-#else /* defined(CONFIG_ARCHES) */
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	CONFIG_AMCC_DEF_ENV						\
-	CONFIG_AMCC_DEF_ENV_POWERPC					\
-	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
-	"kernel_addr=fe000000\0"					\
-	"fdt_addr=fe1e0000\0"						\
-	"ramdisk_addr=fe200000\0"					\
-	"pciconfighost=1\0"						\
-	"pcie_mode=RP:RP\0"						\
-	"ethprime=ppc_4xx_eth1\0"					\
-	""
-#endif	/* !defined(CONFIG_ARCHES) */
-
-/*
- * Commands additional to the ones defined in amcc-common.h
- */
-#if defined(CONFIG_ARCHES)
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_SDRAM
-#elif defined(CONFIG_CANYONLANDS)
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_SATA
-#define CONFIG_CMD_SDRAM
-#elif defined(CONFIG_GLACIER)
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_SDRAM
-#else
-#error "board type not defined"
-#endif
-
-/* Partitions */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *----------------------------------------------------------------------*/
-/* General PCI */
-#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
-#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup  */
-#define CONFIG_PCI_CONFIG_HOST_BRIDGE
-
-/* Board-specific PCI */
-#define CONFIG_SYS_PCI_TARGET_INIT		/* let board init pci target    */
-#undef	CONFIG_SYS_PCI_MASTER_INIT
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014	/* IBM				*/
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever			*/
-
-#ifdef CONFIG_460GT
-#if defined(CONFIG_ARCHES)
-/*-----------------------------------------------------------------------
- * RapidIO I/O and Registers
- *----------------------------------------------------------------------*/
-#define CONFIG_RAPIDIO
-#define CONFIG_SYS_460GT_SRIO_ERRATA_1
-
-#define SRGPL0_REG_BAR		0x0000000DAA000000ull	/*  16MB */
-#define SRGPL0_CFG_BAR		0x0000000DAB000000ull	/*  16MB */
-#define SRGPL0_MNT_BAR		0x0000000DAC000000ull	/*  16MB */
-#define SRGPL0_MSG_BAR		0x0000000DAD000000ull	/*  16MB */
-#define SRGPL0_OUT_BAR		0x0000000DB0000000ull	/* 256MB */
-
-#define CONFIG_SYS_SRGPL0_REG_BAR	0xAA000000		/*  16MB */
-#define CONFIG_SYS_SRGPL0_CFG_BAR	0xAB000000		/*  16MB */
-#define CONFIG_SYS_SRGPL0_MNT_BAR	0xAC000000		/*  16MB */
-#define CONFIG_SYS_SRGPL0_MSG_BAR	0xAD000000		/*  16MB */
-
-#define CONFIG_SYS_I2ODMA_BASE		0xCF000000
-#define CONFIG_SYS_I2ODMA_PHYS_ADDR	0x0000000400100000ull
-
-#define CONFIG_PPC4XX_RAPIDIO_PROMISCUOUS_MODE
-#undef CONFIG_PPC4XX_RAPIDIO_DEBUG
-#undef CONFIG_PPC4XX_RAPIDIO_IN_BAR_USE_OCM
-#define CONFIG_PPC4XX_RAPIDIO_USE_HB_PLB
-#undef CONFIG_PPC4XX_RAPIDIO_LOOPBACK
-#endif /* CONFIG_ARCHES */
-#endif /* CONFIG_460GT */
-
-/*
- * SATA driver setup
- */
-#ifdef CONFIG_CMD_SATA
-#define CONFIG_SATA_DWC
-#define CONFIG_LIBATA
-#define SATA_BASE_ADDR		0xe20d1000	/* PPC460EX SATA Base Address */
-#define SATA_DMA_REG_ADDR	0xe20d0800	/* PPC460EX SATA Base Address */
-#define CONFIG_SYS_SATA_MAX_DEVICE	1	/* SATA MAX DEVICE */
-/* Convert sectorsize to wordsize */
-#define ATA_SECTOR_WORDS (ATA_SECT_SIZE/2)
-#endif
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- *----------------------------------------------------------------------*/
-
-/*
- * Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the
- * boot EBC mapping only supports a maximum of 16MBytes
- * (4.ff00.0000 - 4.ffff.ffff).
- * To solve this problem, the FLASH has to get remapped to another
- * EBC address which accepts bigger regions:
- *
- * 0xfc00.0000 -> 4.cc00.0000
- *
- * Arches has 32MBytes of NOR FLASH (Spansion 29GL256), it will be
- * remapped to:
- *
- * 0xfe00.0000 -> 4.ce00.0000
- */
-
-/* Memory Bank 0 (NOR-FLASH) initialization					*/
-#define CONFIG_SYS_EBC_PB0AP		0x10055e00
-#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_BOOT_BASE_ADDR | 0x9a000)
-
-#if !defined(CONFIG_ARCHES)
-/* Memory Bank 3 (NAND-FLASH) initialization						*/
-#define CONFIG_SYS_EBC_PB3AP		0x018003c0
-#define CONFIG_SYS_EBC_PB3CR		(CONFIG_SYS_NAND_ADDR | 0x1E000) /* BAS=NAND,BS=1MB,BU=R/W,BW=32bit*/
-#endif
-
-#if !defined(CONFIG_ARCHES)
-/* Memory Bank 2 (CPLD) initialization						*/
-#define CONFIG_SYS_EBC_PB2AP		0x00804240
-#define CONFIG_SYS_EBC_PB2CR		(CONFIG_SYS_BCSR_BASE | 0x18000) /* BAS=CPLD,BS=1M,BU=RW,BW=32bit */
-
-#else /* defined(CONFIG_ARCHES) */
-
-/* Memory Bank 1 (FPGA) initialization  */
-#define CONFIG_SYS_EBC_PB1AP		0x7f8ffe80
-#define CONFIG_SYS_EBC_PB1CR		(CONFIG_SYS_FPGA_BASE | 0x3a000) /* BAS=FPGA,BS=2MB,BU=R/W,BW=16bit*/
-#endif	/* !defined(CONFIG_ARCHES) */
-
-#define CONFIG_SYS_EBC_CFG		0xbfc00000
-
-/*
- * Arches doesn't use PerCS3 but GPIO43, so let's configure the GPIO
- * pin multiplexing correctly
- */
-#if defined(CONFIG_ARCHES)
-#define GPIO43_USE		GPIO_SEL	/* On Arches this pin is used as GPIO */
-#else
-#define GPIO43_USE		GPIO_ALT1	/* On Glacier this pin is used as ALT1 -> PerCS3 */
-#endif
-
-/*
- * PPC4xx GPIO Configuration
- */
-#ifdef CONFIG_460EX
-/* 460EX: Use USB configuration */
-#define CONFIG_SYS_4xx_GPIO_TABLE { /*	  Out		  GPIO	Alternate1	Alternate2	Alternate3 */ \
-{											\
-/* GPIO Core 0 */									\
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0	GMC1TxD(0)	USB2HostD(0)	*/	\
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1	GMC1TxD(1)	USB2HostD(1)	*/	\
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO2	GMC1TxD(2)	USB2HostD(2)	*/	\
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO3	GMC1TxD(3)	USB2HostD(3)	*/	\
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO4	GMC1TxD(4)	USB2HostD(4)	*/	\
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO5	GMC1TxD(5)	USB2HostD(5)	*/	\
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO6	GMC1TxD(6)	USB2HostD(6)	*/	\
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO7	GMC1TxD(7)	USB2HostD(7)	*/	\
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8	GMC1RxD(0)	USB2OTGD(0)	*/	\
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9	GMC1RxD(1)	USB2OTGD(1)	*/	\
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2)	USB2OTGD(2)	*/	\
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3)	USB2OTGD(3)	*/	\
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4)	USB2OTGD(4)	*/	\
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5)	USB2OTGD(5)	*/	\
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6)	USB2OTGD(6)	*/	\
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7)	USB2OTGD(7)	*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_SEL,  GPIO_OUT_0}, /* GPIO16 GMC1TxER	USB2HostStop	*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD		USB2HostNext	*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER	USB2HostDir	*/	\
-{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO19 GMC1TxEN	USB2OTGStop	*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS	USB2OTGNext	*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV	USB2OTGDir	*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY				*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN				*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN				*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE				*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE				*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0)				*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1)				*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2)				*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0	DMAReq2		IRQ(7)*/ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1	DMAAck2		IRQ(8)*/ \
-},											\
-{											\
-/* GPIO Core 1 */									\
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2	EOT2/TC2	IRQ(9)*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3	DMAReq3		IRQ(4)*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N	UART1_DSR_CTS_N	UART2_SOUT*/ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3	UART3_SIN*/ \
-{GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N	EOT3/TC3	UART3_SOUT*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N	UART1_SOUT	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N	UART1_SIN	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3)				*/	\
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1)				*/	\
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2)				*/	\
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3)		DMAReq1		IRQ(10)*/ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4)		DMAAck1		IRQ(11)*/ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5)		EOT/TC1		IRQ(12)*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5)	DMAReq0		IRQ(13)*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6)	DMAAck0		IRQ(14)*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7)	EOT/TC0		IRQ(15)*/ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63  Unselect via TraceSelect Bit	*/	\
-}											\
-}
-#else
-/* 460GT: Use EMAC2+3 configuration */
-#define CONFIG_SYS_4xx_GPIO_TABLE { /*	  Out		  GPIO	Alternate1	Alternate2	Alternate3 */ \
-{											\
-/* GPIO Core 0 */									\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0	GMC1TxD(0)	USB2HostD(0)	*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1	GMC1TxD(1)	USB2HostD(1)	*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2	GMC1TxD(2)	USB2HostD(2)	*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3	GMC1TxD(3)	USB2HostD(3)	*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4	GMC1TxD(4)	USB2HostD(4)	*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5	GMC1TxD(5)	USB2HostD(5)	*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6	GMC1TxD(6)	USB2HostD(6)	*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7	GMC1TxD(7)	USB2HostD(7)	*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8	GMC1RxD(0)	USB2OTGD(0)	*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9	GMC1RxD(1)	USB2OTGD(1)	*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2)	USB2OTGD(2)	*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3)	USB2OTGD(3)	*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4)	USB2OTGD(4)	*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5)	USB2OTGD(5)	*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6)	USB2OTGD(6)	*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7)	USB2OTGD(7)	*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMC1TxER	USB2HostStop	*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD		USB2HostNext	*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER	USB2HostDir	*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMC1TxEN	USB2OTGStop	*/	\
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS	USB2OTGNext	*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV	USB2OTGDir	*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY				*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN				*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN				*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE				*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE				*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0)				*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1)				*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2)				*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0	DMAReq2		IRQ(7)*/ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1	DMAAck2		IRQ(8)*/ \
-},											\
-{											\
-/* GPIO Core 1 */									\
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2	EOT2/TC2	IRQ(9)*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3	DMAReq3		IRQ(4)*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N	UART1_DSR_CTS_N	UART2_SOUT*/ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3	UART3_SIN*/ \
-{GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N	EOT3/TC3	UART3_SOUT*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N	UART1_SOUT	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N	UART1_SIN	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3)				*/	\
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1)				*/	\
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2)				*/	\
-{GPIO1_BASE, GPIO_OUT, GPIO43_USE, GPIO_OUT_0},/* GPIO43 CS(3)		DMAReq1		IRQ(10)*/ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4)		DMAAck1		IRQ(11)*/ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5)		EOT/TC1		IRQ(12)*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5)	DMAReq0		IRQ(13)*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6)	DMAAck0		IRQ(14)*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7)	EOT/TC0		IRQ(15)*/ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63  Unselect via TraceSelect Bit	*/	\
-}											\
-}
-#endif
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/dlvision-10g.h b/include/configs/dlvision-10g.h
deleted file mode 100644
index 59ba0afb29..0000000000
--- a/include/configs/dlvision-10g.h
+++ /dev/null
@@ -1,317 +0,0 @@
-/*
- * (C) Copyright 2010
- * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_405EP		1	/* this is a PPC405 CPU */
-#define CONFIG_DLVISION_10G	1	/*  on a DLVision-10G board */
-
-#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
-
-/*
- * Include common defines/options for all AMCC eval boards
- */
-#define CONFIG_HOSTNAME		dlvsion-10g
-#include "amcc-common.h"
-
-#define CONFIG_BOARD_EARLY_INIT_R
-#define CONFIG_MISC_INIT_R
-#define CONFIG_LAST_STAGE_INIT
-
-#define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll   */
-
-/*
- * Configure PLL
- */
-#define PLLMR0_DEFAULT PLLMR0_266_133_66
-#define PLLMR1_DEFAULT PLLMR1_266_133_66
-
-#define CONFIG_ENV_IS_IN_FLASH	/* use FLASH for environment vars */
-
-/*
- * Default environment variables
- */
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	CONFIG_AMCC_DEF_ENV						\
-	CONFIG_AMCC_DEF_ENV_POWERPC					\
-	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
-	"kernel_addr=fc000000\0"					\
-	"fdt_addr=fc1e0000\0"						\
-	"ramdisk_addr=fc200000\0"					\
-	""
-
-#define CONFIG_PHY_ADDR		4	/* PHY address			*/
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#define CONFIG_PHY1_ADDR	0xc	/* EMAC1 PHY address		*/
-#define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ
-
-/*
- * Commands additional to the ones defined in amcc-common.h
- */
-
-/*
- * SDRAM configuration (please see cpu/ppc/sdram.[ch])
- */
-#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0 */
-
-/* SDRAM timings used in datasheet */
-#define CONFIG_SYS_SDRAM_CL             3	/* CAS latency */
-#define CONFIG_SYS_SDRAM_tRP           20	/* PRECHARGE command period */
-#define CONFIG_SYS_SDRAM_tRC           66	/* ACTIVE-to-ACTIVE period */
-#define CONFIG_SYS_SDRAM_tRCD          20	/* ACTIVE-to-READ delay */
-#define CONFIG_SYS_SDRAM_tRFC          66	/* Auto refresh period */
-
-/*
- * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
- * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
- * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
- * The Linux BASE_BAUD define should match this configuration.
- *    baseBaud = cpuClock/(uartDivisor*16)
- * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
- * set Linux BASE_BAUD to 403200.
- */
-#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
-#undef  CONFIG_SYS_EXT_SERIAL_CLOCK	/* external serial clock */
-#undef  CONFIG_SYS_405_UART_ERRATA_59	/* 405GP/CR Rev. D silicon */
-#define CONFIG_SYS_BASE_BAUD		691200
-
-/*
- * I2C stuff
- */
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		100000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
-
-#define CONFIG_SYS_I2C_IHS
-#define CONFIG_SYS_I2C_IHS_DUAL
-#define CONFIG_SYS_I2C_IHS_CH0
-#define CONFIG_SYS_I2C_IHS_SPEED_0		50000
-#define CONFIG_SYS_I2C_IHS_SLAVE_0		0x7F
-#define CONFIG_SYS_I2C_IHS_SPEED_0_1		50000
-#define CONFIG_SYS_I2C_IHS_SLAVE_0_1		0x7F
-#define CONFIG_SYS_I2C_IHS_CH1
-#define CONFIG_SYS_I2C_IHS_SPEED_1		50000
-#define CONFIG_SYS_I2C_IHS_SLAVE_1		0x7F
-#define CONFIG_SYS_I2C_IHS_SPEED_1_1		50000
-#define CONFIG_SYS_I2C_IHS_SLAVE_1_1		0x7F
-
-#define CONFIG_SYS_SPD_BUS_NUM		4
-
-/* Temp sensor/hwmon/dtt */
-
-#define CONFIG_SYS_ICS8N3QV01_I2C	{1, 3}
-#define CONFIG_SYS_SIL1178_I2C		{0, 2}
-#define CONFIG_SYS_DP501_I2C		{0, 2}
-
-/* EBC peripherals */
-
-#define CONFIG_SYS_FLASH_BASE		0xFC000000
-#define CONFIG_SYS_FPGA0_BASE		0x7f100000
-#define CONFIG_SYS_FPGA1_BASE		0x7f200000
-#define CONFIG_SYS_LATCH_BASE		0x7f300000
-
-#define CONFIG_SYS_FPGA_BASE(k) \
-	(k ? CONFIG_SYS_FPGA1_BASE : CONFIG_SYS_FPGA0_BASE)
-
-#define CONFIG_SYS_FPGA_DONE(k) \
-	(k ? 0x2000 : 0x1000)
-
-#define CONFIG_SYS_FPGA_COUNT		2
-
-#define CONFIG_SYS_FPGA_PTR { \
-	(struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, \
-	(struct ihs_fpga *)CONFIG_SYS_FPGA1_BASE }
-
-#define CONFIG_SYS_FPGA_COMMON
-
-#define CONFIG_SYS_LATCH0_RESET		0xffff
-#define CONFIG_SYS_LATCH0_BOOT		0xffff
-#define CONFIG_SYS_LATCH1_RESET		0xffbf
-#define CONFIG_SYS_LATCH1_BOOT		0xffff
-
-#define CONFIG_SYS_FPGA_NO_RFL_HI
-
-/*
- * FLASH organization
- */
-#define CONFIG_SYS_FLASH_CFI		/* The flash is CFI compatible	*/
-#define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/
-
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max num of sectors per chip*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase/ms */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write/ms */
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buff'd writes */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO	/* 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* no warn upon unknown flash */
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE	0x20000	/* size of one complete sector */
-#define CONFIG_ENV_ADDR		((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
-#define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector */
-
-/* Address and size of Redundant Environment Sector	*/
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
-#endif
-
-/*
- * PPC405 GPIO Configuration
- */
-#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO	Alternate1	*/ \
-{ \
-/* GPIO Core 0 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO0	PerBLast */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO1	TS1E */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO2	TS2E */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO3	TS1O */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO4	TS2O */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1      }, /* GPIO5	TS3 */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO6	TS4 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1      }, /* GPIO7	TS5 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO8	TS6 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO9	TrcClk */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10	PerCS1 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11	PerCS2 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12	PerCS3 */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO13	PerCS4 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14	PerAddr03 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15	PerAddr04 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16	PerAddr05 */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17	IRQ0 */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18	IRQ1 */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19	IRQ2 */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO20	IRQ3 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO21	IRQ4 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO22	IRQ5 */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO23	IRQ6 */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24	UART0_DCD */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25	UART0_DSR */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26	UART0_RI */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27	UART0_DTR */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28	UART1_Rx */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29	UART1_Tx */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO30	RejectPkt0 */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO31	RejectPkt1 */ \
-} \
-}
-
-/*
- * Definitions for initial stack pointer and data area (in data cache)
- */
-/* use on chip memory (OCM) for temperary stack until sdram is tested */
-#define CONFIG_SYS_TEMP_STACK_OCM	1
-
-/* On Chip Memory location */
-#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
-#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE
-
-#define CONFIG_SYS_GBL_DATA_OFFSET \
-	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/*
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (NOR-flash) */
-#define CONFIG_SYS_EBC_PB0AP	(EBC_BXAP_BME_ENABLED		|	\
-				 EBC_BXAP_FWT_ENCODE(8)		|	\
-				 EBC_BXAP_BWT_ENCODE(7)		|	\
-				 EBC_BXAP_BCE_DISABLE		|	\
-				 EBC_BXAP_BCT_2TRANS		|	\
-				 EBC_BXAP_CSN_ENCODE(0)		|	\
-				 EBC_BXAP_OEN_ENCODE(2)		|	\
-				 EBC_BXAP_WBN_ENCODE(2)		|	\
-				 EBC_BXAP_WBF_ENCODE(2)		|	\
-				 EBC_BXAP_TH_ENCODE(4)		|	\
-				 EBC_BXAP_RE_DISABLED		|	\
-				 EBC_BXAP_SOR_NONDELAYED	|	\
-				 EBC_BXAP_BEM_WRITEONLY		|	\
-				 EBC_BXAP_PEN_DISABLED)
-#define CONFIG_SYS_EBC_PB0CR	(EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
-				 EBC_BXCR_BS_64MB		|	\
-				 EBC_BXCR_BU_RW			|	\
-				 EBC_BXCR_BW_16BIT)
-
-/* Memory Bank 1 (FPGA0) */
-#define CONFIG_SYS_EBC_PB1AP	(EBC_BXAP_BME_DISABLED		|	\
-				 EBC_BXAP_TWT_ENCODE(5)		|	\
-				 EBC_BXAP_BCE_DISABLE		|	\
-				 EBC_BXAP_BCT_2TRANS		|	\
-				 EBC_BXAP_CSN_ENCODE(0)		|	\
-				 EBC_BXAP_OEN_ENCODE(2)		|	\
-				 EBC_BXAP_WBN_ENCODE(1)		|	\
-				 EBC_BXAP_WBF_ENCODE(1)		|	\
-				 EBC_BXAP_TH_ENCODE(0)		|	\
-				 EBC_BXAP_RE_DISABLED		|	\
-				 EBC_BXAP_SOR_NONDELAYED	|	\
-				 EBC_BXAP_BEM_WRITEONLY		|	\
-				 EBC_BXAP_PEN_DISABLED)
-#define CONFIG_SYS_EBC_PB1CR	(EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA0_BASE) | \
-				 EBC_BXCR_BS_1MB		|	\
-				 EBC_BXCR_BU_RW			|	\
-				 EBC_BXCR_BW_16BIT)
-
-/* Memory Bank 2 (FPGA1) */
-#define CONFIG_SYS_EBC_PB2AP	(EBC_BXAP_BME_DISABLED		|	\
-				 EBC_BXAP_TWT_ENCODE(6)		|	\
-				 EBC_BXAP_BCE_DISABLE		|	\
-				 EBC_BXAP_BCT_2TRANS		|	\
-				 EBC_BXAP_CSN_ENCODE(0)		|	\
-				 EBC_BXAP_OEN_ENCODE(2)		|	\
-				 EBC_BXAP_WBN_ENCODE(1)		|	\
-				 EBC_BXAP_WBF_ENCODE(1)		|	\
-				 EBC_BXAP_TH_ENCODE(0)		|	\
-				 EBC_BXAP_RE_DISABLED		|	\
-				 EBC_BXAP_SOR_NONDELAYED	|	\
-				 EBC_BXAP_BEM_WRITEONLY		|	\
-				 EBC_BXAP_PEN_DISABLED)
-#define CONFIG_SYS_EBC_PB2CR	(EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA1_BASE) | \
-				 EBC_BXCR_BS_1MB		|	\
-				 EBC_BXCR_BU_RW			|	\
-				 EBC_BXCR_BW_16BIT)
-
-/* Memory Bank 3 (Latches) */
-#define CONFIG_SYS_EBC_PB3AP	(EBC_BXAP_BME_ENABLED		|	\
-				 EBC_BXAP_FWT_ENCODE(8)		|	\
-				 EBC_BXAP_BWT_ENCODE(4)		|	\
-				 EBC_BXAP_BCE_DISABLE		|	\
-				 EBC_BXAP_BCT_2TRANS		|	\
-				 EBC_BXAP_CSN_ENCODE(0)		|	\
-				 EBC_BXAP_OEN_ENCODE(1)		|	\
-				 EBC_BXAP_WBN_ENCODE(1)		|	\
-				 EBC_BXAP_WBF_ENCODE(1)		|	\
-				 EBC_BXAP_TH_ENCODE(2)		|	\
-				 EBC_BXAP_RE_DISABLED		|	\
-				 EBC_BXAP_SOR_NONDELAYED	|	\
-				 EBC_BXAP_BEM_WRITEONLY		|	\
-				 EBC_BXAP_PEN_DISABLED)
-#define CONFIG_SYS_EBC_PB3CR	(EBC_BXCR_BAS_ENCODE(CONFIG_SYS_LATCH_BASE) | \
-				 EBC_BXCR_BS_1MB		|	\
-				 EBC_BXCR_BU_RW			|	\
-				 EBC_BXCR_BW_16BIT)
-
-/*
- * OSD Setup
- */
-#define CONFIG_SYS_MPC92469AC
-#define CONFIG_SYS_OSD_SCREENS		CONFIG_SYS_FPGA_COUNT
-#define CONFIG_SYS_DP501_DIFFERENTIAL
-#define CONFIG_SYS_DP501_VCAPCTRL0	0x01 /* DDR mode 0, DE for H/VSYNC */
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/dlvision.h b/include/configs/dlvision.h
deleted file mode 100644
index 11397bd8e9..0000000000
--- a/include/configs/dlvision.h
+++ /dev/null
@@ -1,200 +0,0 @@
-/*
- * (C) Copyright 2009
- * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_405EP		1	/* this is a PPC405 CPU */
-#define CONFIG_DLVISION	        1	/*  on a Neo board */
-
-#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
-
-/*
- * Include common defines/options for all AMCC eval boards
- */
-#define CONFIG_HOSTNAME		dlvision
-#include "amcc-common.h"
-
-#define CONFIG_MISC_INIT_R		/* call misc_init_r */
-
-#define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll   */
-
-/*
- * Configure PLL
- */
-#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
-#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
-
-#define CONFIG_ENV_IS_IN_FLASH	/* use FLASH for environment vars */
-
-/*
- * Default environment variables
- */
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	CONFIG_AMCC_DEF_ENV						\
-	CONFIG_AMCC_DEF_ENV_POWERPC					\
-	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
-	"kernel_addr=fc000000\0"					\
-	"fdt_addr=fc1e0000\0"						\
-	"ramdisk_addr=fc200000\0"					\
-	""
-
-#define CONFIG_PHY_ADDR		4	/* PHY address			*/
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#define CONFIG_PHY1_ADDR	0xc	/* EMAC1 PHY address		*/
-#define CONFIG_PHY_CLK_FREQ    EMAC_STACR_CLK_66MHZ
-
-/*
- * Commands additional to the ones defined in amcc-common.h
- */
-
-/*
- * SDRAM configuration (please see cpu/ppc/sdram.[ch])
- */
-#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0 */
-
-/* SDRAM timings used in datasheet */
-#define CONFIG_SYS_SDRAM_CL             3	/* CAS latency */
-#define CONFIG_SYS_SDRAM_tRP           20	/* PRECHARGE command period */
-#define CONFIG_SYS_SDRAM_tRC           66	/* ACTIVE-to-ACTIVE period */
-#define CONFIG_SYS_SDRAM_tRCD          20	/* ACTIVE-to-READ delay */
-#define CONFIG_SYS_SDRAM_tRFC          66	/* Auto refresh period */
-
-/*
- * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
- * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
- * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
- * The Linux BASE_BAUD define should match this configuration.
- *    baseBaud = cpuClock/(uartDivisor*16)
- * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
- * set Linux BASE_BAUD to 403200.
- */
-#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
-#undef  CONFIG_SYS_EXT_SERIAL_CLOCK           /* external serial clock */
-#undef  CONFIG_SYS_405_UART_ERRATA_59         /* 405GP/CR Rev. D silicon */
-#define CONFIG_SYS_BASE_BAUD		691200
-
-/*
- * I2C stuff
- */
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		100000
-
-/*
- * FLASH organization
- */
-#define CONFIG_SYS_FLASH_CFI		/* The flash is CFI compatible	*/
-#define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/
-
-#define CONFIG_SYS_FLASH_BASE		0xFC000000
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max num of sectors per chip*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase/ms */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write/ms */
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buff'd writes */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO	/* 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* no warn upon unknown flash */
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE	0x20000	/* size of one complete sector */
-#define CONFIG_ENV_ADDR		((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
-#define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector */
-
-/* Address and size of Redundant Environment Sector	*/
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
-#endif
-
-/*
- * PPC405 GPIO Configuration
- */
-#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO	Alternate1	*/ \
-{ \
-/* GPIO Core 0 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO0	PerBLast */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO1	TS1E */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO2	TS2E */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO3	TS1O */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO4	TS2O */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1      }, /* GPIO5	TS3 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO6	TS4 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO7	TS5 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO8	TS6 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO9	TrcClk */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10	PerCS1 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11	PerCS2 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12	PerCS3 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13	PerCS4 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14	PerAddr03 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15	PerAddr04 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16	PerAddr05 */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17	IRQ0 */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18	IRQ1 */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19	IRQ2 */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO20	IRQ3 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO21	IRQ4 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO22	IRQ5 */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO23	IRQ6 */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24	UART0_DCD */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25	UART0_DSR */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26	UART0_RI */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27	UART0_DTR */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28	UART1_Rx */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29	UART1_Tx */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO30	RejectPkt0 */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO31	RejectPkt1 */ \
-} \
-}
-
-/*
- * Definitions for initial stack pointer and data area (in data cache)
- */
-/* use on chip memory (OCM) for temperary stack until sdram is tested */
-#define CONFIG_SYS_TEMP_STACK_OCM        1
-
-/* On Chip Memory location */
-#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
-#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET \
-	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/*
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (NOR-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB0AP		0x92015480
-/* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit */
-#define CONFIG_SYS_EBC_PB0CR		0xFC0DA000
-
-/* Memory Bank 1 (NVRAM) initializatio */
-#define CONFIG_SYS_EBC_PB1AP		0x92015480
-/* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit  */
-#define CONFIG_SYS_EBC_PB1CR		0xFB858000
-
-/* Memory Bank 2 (UART) initialization */
-#define CONFIG_UART_BASE		0x7f100000
-#define CONFIG_SYS_EBC_PB2AP		0x92015480
-/* BAS=0x7f1,BS=1MB,BU=R/W,BW=8bit */
-#define CONFIG_SYS_EBC_PB2CR		0x7f118000
-
-/* Memory Bank 3 (Latches) initialization */
-#define CONFIG_SYS_LATCH_BASE		0x7f200000
-#define CONFIG_SYS_EBC_PB3AP		0x92015480
-/* BAS=0x7f2,BS=1MB,BU=R/W,BW=16bit */
-#define CONFIG_SYS_EBC_PB3CR		0x7f21a000
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/gdppc440etx.h b/include/configs/gdppc440etx.h
deleted file mode 100644
index 7e03dd63ee..0000000000
--- a/include/configs/gdppc440etx.h
+++ /dev/null
@@ -1,177 +0,0 @@
-/*
- * (C) Copyright 2008
- * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
- *
- * Based on include/configs/yosemite.h
- * (C) Copyright 2005-2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * gdppc440etx.h - configuration for G&D 440EP/GR ETX-Module
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_440GR		1		/* Specific PPC440GR support */
-#define CONFIG_HOSTNAME		gdppc440etx
-#define CONFIG_440		1		/* ... PPC440 family         */
-#define CONFIG_SYS_CLK_FREQ	66666666	/* external freq to pll      */
-
-#define	CONFIG_SYS_TEXT_BASE	0xFFF80000
-
-/*
- * Include common defines/options for all AMCC eval boards
- */
-#include "amcc-common.h"
-
-#define CONFIG_MISC_INIT_R		1	/* call misc_init_r()     */
-
-/*
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- */
-#define CONFIG_SYS_FLASH_BASE		0xfc000000	/* start of FLASH    */
-#define CONFIG_SYS_PCI_MEMBASE		0xa0000000	/* mapped pci memory */
-#define CONFIG_SYS_PCI_MEMBASE1		CONFIG_SYS_PCI_MEMBASE  + 0x10000000
-#define CONFIG_SYS_PCI_MEMBASE2		CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
-#define CONFIG_SYS_PCI_MEMBASE3		CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
-
-/*Don't change either of these*/
-#define CONFIG_SYS_PCI_BASE		0xe0000000	/* internal PCI regs */
-/*Don't change either of these*/
-
-#define CONFIG_SYS_USB_DEVICE		0x50000000
-#define CONFIG_SYS_BOOT_BASE_ADDR	0xf0000000
-
-/*
- * Initial RAM & stack pointer (placed in SDRAM)
- */
-#define CONFIG_SYS_INIT_RAM_DCACHE	1		/* d-cache as init ram*/
-#define CONFIG_SYS_INIT_RAM_ADDR	0x70000000	/* DCache             */
-#define CONFIG_SYS_INIT_RAM_SIZE		(4 << 10)
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE \
-					 - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX	2	/* Use UART1			*/
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
-#define CONFIG_SYS_EXT_SERIAL_CLOCK	11059200	/* ext. 11.059MHz clk */
-
-/*
- * Environment
- * Define here the location of the environment variables (FLASH or EEPROM).
- * Note: DENX encourages to use redundant environment in FLASH.
- */
-#define CONFIG_ENV_IS_IN_FLASH		1		/* FLASH for env. vars*/
-
-/*
- * FLASH related
- */
-#define CONFIG_SYS_FLASH_CFI			/* The flash is CFI compatible*/
-#define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver      */
-#define CONFIG_SYS_FLASH_CFI_AMD_RESET	1	/* AMD RESET for STM 29W320DB!*/
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors/chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 	120000	/* Timeout/Flash Erase (in ms)*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout/Flash Write (in ms)*/
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1/* use buffered writes (20x faster)*/
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE		0x20000 /* size of one complete sector*/
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE			0x2000 /* Total Size of Env. Sector */
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_ADDR_REDUND		(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND		(CONFIG_ENV_SIZE)
-#endif /* CONFIG_ENV_IS_IN_FLASH */
-
-/*
- * DDR SDRAM
- */
-#undef CONFIG_SPD_EEPROM		/* Don't use SPD EEPROM for setup*/
-#define CONFIG_SYS_KBYTES_SDRAM		(128 * 1024)    /* 128MB         */
-#define CONFIG_SYS_SDRAM_BANKS		(2)
-
-#define CONFIG_SDRAM_BANK0
-#define CONFIG_SDRAM_BANK1
-
-#define CONFIG_SYS_SDRAM0_TR0		0x410a4012
-#define CONFIG_SYS_SDRAM0_WDDCTR	0x40000000
-#define CONFIG_SYS_SDRAM0_RTR		0x04080000
-#define CONFIG_SYS_SDRAM0_CFG0		0x80000000
-
-#undef CONFIG_SDRAM_ECC
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
-
-/*
- * Default environment variables
- */
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	CONFIG_AMCC_DEF_ENV						\
-	CONFIG_AMCC_DEF_ENV_POWERPC					\
-	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
-	"kernel_addr=fc000000\0"					\
-	"ramdisk_addr=fc180000\0"					\
-	""
-
-#define CONFIG_HAS_ETH1			1	/* add support for "eth1addr" */
-#define CONFIG_PHY_ADDR			1
-#define CONFIG_PHY1_ADDR		3
-
-#ifdef DEBUG
-#define CONFIG_PANIC_HANG
-#endif
-
-/*
- * Commands additional to the ones defined in amcc-common.h
- */
-#define CONFIG_CMD_PCI
-
-/*
- * PCI stuff
- */
-
-/* General PCI */
-#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
-#define CONFIG_PCI_SCAN_SHOW			/* show pci devices on startup*/
-#define CONFIG_SYS_PCI_TARGBASE		0x80000000	/* PCIaddr mapped to \
-							CONFIG_SYS_PCI_MEMBASE*/
-
-/* Board-specific PCI */
-#define CONFIG_SYS_PCI_TARGET_INIT
-#define CONFIG_SYS_PCI_MASTER_INIT
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID	0x10e8	/* AMCC */
-#define CONFIG_SYS_PCI_SUBSYS_ID	0xcafe	/* tbd */
-
-/*
- * External Bus Controller (EBC) Setup
- */
-#define CONFIG_SYS_FLASH		CONFIG_SYS_FLASH_BASE
-
-/* Memory Bank 0 (NOR-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB0AP		0x03017200
-#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_FLASH | 0xda000)
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/icon.h b/include/configs/icon.h
deleted file mode 100644
index 3ad296be90..0000000000
--- a/include/configs/icon.h
+++ /dev/null
@@ -1,296 +0,0 @@
-/*
- * (C) Copyright 2009-2010
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * icon.h - configuration for Mosaixtech ICON (440SPe)
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_ICON		1		/* Board is icon	*/
-#define CONFIG_440		1		/* ... PPC440 family	*/
-#define CONFIG_440SPE		1		/* Specifc SPe support	*/
-
-#define	CONFIG_SYS_TEXT_BASE	0xFFFA0000
-
-#define CONFIG_SYS_CLK_FREQ	33333333	/* external freq to pll	*/
-#define CONFIG_SYS_4xx_RESET_TYPE 0x2	/* use chip reset on this board	*/
-
-/*
- * Include common defines/options for all AMCC eval boards
- */
-#define CONFIG_HOSTNAME		icon
-#include "amcc-common.h"
-
-#define CONFIG_BOARD_EARLY_INIT_R	/* Call board_early_init_r */
-
-/*
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- */
-#define CONFIG_SYS_FLASH_BASE	0xfc000000	/* later mapped to this addr */
-#define CONFIG_SYS_ISRAM_BASE	0x90000000	/* internal SRAM	*/
-
-#define CONFIG_SYS_PCI_MEMBASE	0x80000000	/* mapped PCI memory	*/
-#define CONFIG_SYS_PCI_BASE	0xd0000000	/* internal PCI regs	*/
-#define CONFIG_SYS_PCI_TARGBASE	CONFIG_SYS_PCI_MEMBASE
-
-#define CONFIG_SYS_PCIE_MEMBASE	0xb0000000	/* mapped PCIe memory	*/
-#define CONFIG_SYS_PCIE_MEMSIZE	0x08000000	/* incr for PCIe port */
-#define CONFIG_SYS_PCIE_BASE	0xe0000000	/* PCIe UTL regs */
-
-#define CONFIG_SYS_PCIE0_CFGBASE	0xc0000000
-#define CONFIG_SYS_PCIE1_CFGBASE	0xc1000000
-#define CONFIG_SYS_PCIE2_CFGBASE	0xc2000000
-#define CONFIG_SYS_PCIE0_XCFGBASE	0xc3000000
-#define CONFIG_SYS_PCIE1_XCFGBASE	0xc3001000
-#define CONFIG_SYS_PCIE2_XCFGBASE	0xc3002000
-
-/* base address of inbound PCIe window */
-#define CONFIG_SYS_PCIE_INBOUND_BASE	0x0000000000000000ULL
-
-/* System RAM mapped to PCI space */
-#define CONFIG_PCI_SYS_MEM_BUS	CONFIG_SYS_SDRAM_BASE
-#define CONFIG_PCI_SYS_MEM_PHYS	CONFIG_SYS_SDRAM_BASE
-#define CONFIG_PCI_SYS_MEM_SIZE	(1024 * 1024 * 1024)
-
-#define CONFIG_SYS_ACE_BASE		0xfb000000	/* Xilinx ACE CF */
-#define CONFIG_SYS_ACE_BASE_PHYS_H	0x4
-#define CONFIG_SYS_ACE_BASE_PHYS_L	0xfe000000
-
-#define CONFIG_SYS_FLASH_SIZE		(64 << 20)
-#define CONFIG_SYS_BOOT_BASE_ADDR	0xFF000000	/* EBC Boot Space */
-#define CONFIG_SYS_FLASH_BASE_PHYS_H	0x4
-#define CONFIG_SYS_FLASH_BASE_PHYS_L	0xEC000000
-#define CONFIG_SYS_FLASH_BASE_PHYS	(((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) | \
-					 (u64)CONFIG_SYS_FLASH_BASE_PHYS_L)
-
-/*
- * Initial RAM & stack pointer (placed in internal SRAM)
- */
-#define CONFIG_SYS_TEMP_STACK_OCM	1
-#define CONFIG_SYS_OCM_DATA_ADDR	CONFIG_SYS_ISRAM_BASE
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_ISRAM_BASE	/* Init RAM */
-#define CONFIG_SYS_INIT_RAM_SIZE	0x2000		/* size of used area */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
-					 GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK
-
-/*
- * DDR2 SDRAM
- */
-#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for setup	*/
-#define SPD_EEPROM_ADDRESS	{ 0x51 } /* SPD I2C SPD addresses	*/
-#define CONFIG_DDR_ECC			/* with ECC support		*/
-#define CONFIG_DDR_RQDC_FIXED	0x80000038 /* fixed value for RQDC	*/
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0	100000
-
-#define CONFIG_SYS_SPD_BUS_NUM	0	/* The I2C bus for SPD		*/
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-/* I2C bootstrap EEPROM */
-#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR	0x50
-#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET	0
-#define CONFIG_4xx_CONFIG_BLOCKSIZE		8
-
-/* I2C RTC */
-#define CONFIG_RTC_M41T11
-#define CONFIG_SYS_RTC_BUS_NUM	1	/* The I2C bus for RTC		*/
-#define CONFIG_SYS_I2C_RTC_ADDR	0x68
-#define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* play along with linux	*/
-
-/*
- * Video options
- */
-
-#ifdef CONFIG_VIDEO
-#define CONFIG_VIDEO_SM501
-#define CONFIG_VIDEO_SM501_32BPP
-#define CONFIG_VIDEO_SM501_PCI
-#define VIDEO_FB_LITTLE_ENDIAN
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_VIDEO_BMP_RLE8
-#define CONFIG_SPLASH_SCREEN
-#define CFG_CONSOLE_IS_IN_ENV
-#endif
-
-/*
- * Environment
- */
-#define	CONFIG_ENV_IS_IN_FLASH	1	/* Environment uses flash	*/
-
-/*
- * Default environment variables
- */
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	CONFIG_AMCC_DEF_ENV						\
-	CONFIG_AMCC_DEF_ENV_POWERPC					\
-	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
-	"kernel_addr=fc000000\0"					\
-	"fdt_addr=fc1e0000\0"						\
-	"ramdisk_addr=fc200000\0"					\
-	"pciconfighost=1\0"						\
-	"pcie_mode=RP:RP:RP\0"						\
-	""
-
-/*
- * Commands additional to the ones defined in amcc-common.h
- */
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_SDRAM
-
-#define	CONFIG_IBM_EMAC4_V4		/* 440SPe has this EMAC version	*/
-#define CONFIG_PHY_ADDR		1	/* PHY address, See schematics	*/
-#define CONFIG_HAS_ETH0
-#define CONFIG_PHY_RESET		/* reset phy upon startup	*/
-#define CONFIG_PHY_RESET_DELAY	1000
-#define CONFIG_CIS8201_PHY		/* Enable RGMII mode for Cicada phy */
-#define CONFIG_PHY_GIGE			/* Include GbE speed/duplex det. */
-
-/*
- * FLASH related
- */
-#define CONFIG_SYS_FLASH_CFI		/* The flash is CFI compatible	*/
-#define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/
-#define CONFIG_SYS_FLASH_CFI_AMD_RESET	/* Use AMD (Spansion) reset cmd */
-#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* use status poll method	*/
-
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of banks	*/
-#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* TO for Flash Erase (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* TO for Flash Write (ms) */
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	/* use buffered writes	*/
-#define CONFIG_SYS_FLASH_EMPTY_INFO		/* 'E' for empty sector */
-
-#define CONFIG_ENV_SECT_SIZE	0x20000	/* size of one complete sector	*/
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
-#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Env Sector	*/
-
-/* Address and size of Redundant Environment Sector	*/
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
-
-/*
- * PCI stuff
- */
-/* General PCI */
-#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
-#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup	*/
-#define CONFIG_PCI_CONFIG_HOST_BRIDGE
-#define CONFIG_PCI_BOOTDELAY	1000	/* enable pci bootdelay variable*/
-
-/* Board-specific PCI */
-#define CONFIG_SYS_PCI_TARGET_INIT	/* let board init pci target    */
-#undef	CONFIG_SYS_PCI_MASTER_INIT
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014	/* IBM			*/
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever		*/
-
-/*
- * Xilinx System ACE support
- */
-#define CONFIG_SYSTEMACE		/* Enable SystemACE support	*/
-#define CONFIG_SYS_SYSTEMACE_WIDTH	16	/* Data bus width is 16	*/
-#define CONFIG_SYS_SYSTEMACE_BASE	CONFIG_SYS_ACE_BASE
-
-/*
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (Flash) initialization					*/
-#define CONFIG_SYS_EBC_PB0AP	(EBC_BXAP_BME_DISABLED      |		\
-				 EBC_BXAP_TWT_ENCODE(7)     |		\
-				 EBC_BXAP_BCE_DISABLE       |		\
-				 EBC_BXAP_BCT_2TRANS        |		\
-				 EBC_BXAP_CSN_ENCODE(0)     |		\
-				 EBC_BXAP_OEN_ENCODE(0)     |		\
-				 EBC_BXAP_WBN_ENCODE(0)     |		\
-				 EBC_BXAP_WBF_ENCODE(0)     |		\
-				 EBC_BXAP_TH_ENCODE(0)      |		\
-				 EBC_BXAP_RE_DISABLED       |		\
-				 EBC_BXAP_SOR_DELAYED       |		\
-				 EBC_BXAP_BEM_WRITEONLY     |		\
-				 EBC_BXAP_PEN_DISABLED)
-#define CONFIG_SYS_EBC_PB0CR	(EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
-				 EBC_BXCR_BS_64MB                    |	\
-				 EBC_BXCR_BU_RW                      |	\
-				 EBC_BXCR_BW_16BIT)
-
-/* Memory Bank 1 (Xilinx System ACE controller) initialization		*/
-#define CONFIG_SYS_EBC_PB1AP	(EBC_BXAP_BME_DISABLED      |		\
-				 EBC_BXAP_TWT_ENCODE(4)     |		\
-				 EBC_BXAP_BCE_DISABLE       |		\
-				 EBC_BXAP_BCT_2TRANS        |		\
-				 EBC_BXAP_CSN_ENCODE(0)     |		\
-				 EBC_BXAP_OEN_ENCODE(0)     |		\
-				 EBC_BXAP_WBN_ENCODE(0)     |		\
-				 EBC_BXAP_WBF_ENCODE(0)     |		\
-				 EBC_BXAP_TH_ENCODE(0)      |		\
-				 EBC_BXAP_RE_DISABLED       |		\
-				 EBC_BXAP_SOR_NONDELAYED    |		\
-				 EBC_BXAP_BEM_WRITEONLY     |		\
-				 EBC_BXAP_PEN_DISABLED)
-#define CONFIG_SYS_EBC_PB1CR	(EBC_BXCR_BAS_ENCODE(CONFIG_SYS_ACE_BASE_PHYS_L) | \
-				 EBC_BXCR_BS_1MB                    |	\
-				 EBC_BXCR_BU_RW                     |	\
-				 EBC_BXCR_BW_16BIT)
-
-/*
- * Initialize EBC CONFIG -
- * Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
- * default value : 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
- */
-#define CONFIG_SYS_EBC_CFG	(EBC_CFG_LE_UNLOCK    |	\
-				 EBC_CFG_PTD_ENABLE   |	\
-				 EBC_CFG_RTC_16PERCLK | \
-				 EBC_CFG_ATC_PREVIOUS | \
-				 EBC_CFG_DTC_PREVIOUS | \
-				 EBC_CFG_CTC_PREVIOUS | \
-				 EBC_CFG_OEO_PREVIOUS | \
-				 EBC_CFG_EMC_DEFAULT  |	\
-				 EBC_CFG_PME_DISABLE  |	\
-				 EBC_CFG_PR_16)
-
-/*
- * GPIO Setup
- */
-#define CONFIG_SYS_GPIO_PCIE_PRESENT0	17
-#define CONFIG_SYS_GPIO_PCIE_PRESENT1	21
-#define CONFIG_SYS_GPIO_PCIE_PRESENT2	23
-#define CONFIG_SYS_GPIO_RS232_FORCEOFF	30
-
-#define CONFIG_SYS_PFC0		(GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT0) | \
-				 GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT1) | \
-				 GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT2) | \
-				 GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF))
-#define CONFIG_SYS_GPIO_OR	GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)
-#define CONFIG_SYS_GPIO_TCR	GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)
-#define CONFIG_SYS_GPIO_ODR	0
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/intip.h b/include/configs/intip.h
deleted file mode 100644
index 036fd20eb4..0000000000
--- a/include/configs/intip.h
+++ /dev/null
@@ -1,399 +0,0 @@
-/*
- * (C) Copyright 2009
- * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
- *
- * Based on include/configs/canyonlands.h
- * (C) Copyright 2008
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * intip.h - configuration for CompactCenter aka intip (460EX) and DevCon-Center
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-/*
- * This config file is used for CompactCenter(codename intip) and DevCon-Center
- */
-#define CONFIG_460EX		1	/* Specific PPC460EX		*/
-#ifdef CONFIG_DEVCONCENTER
-#define CONFIG_HOSTNAME		devconcenter
-#else
-#define CONFIG_HOSTNAME		intip
-#endif
-#define CONFIG_440		1
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE	0xFFFA0000
-#endif
-
-/*
- * Include common defines/options for all AMCC eval boards
- */
-#include "amcc-common.h"
-
-#define CONFIG_SYS_CLK_FREQ	66666667	/* external freq to pll	*/
-
-#define CONFIG_BOARD_EARLY_INIT_R	1	/* Call board_early_init_r */
-#define CONFIG_MISC_INIT_R		1	/* Call misc_init_r */
-#define CONFIG_BOARD_TYPES		1	/* support board types */
-#define CFG_ALT_MEMTEST
-
-/*
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- */
-#define CONFIG_SYS_PCI_MEMBASE		0x80000000	/* mapped PCI memory */
-#define CONFIG_SYS_PCI_BASE		0xd0000000	/* internal PCI regs */
-#define CONFIG_SYS_PCI_TARGBASE	CONFIG_SYS_PCI_MEMBASE
-
-/* EBC stuff */
-#ifdef CONFIG_DEVCONCENTER               /* Devcon-Center has 128 MB of flash */
-#define CONFIG_SYS_FLASH_BASE		0xF8000000	/* later mapped here */
-#define CONFIG_SYS_FLASH_SIZE		(128 << 20)
-#else
-#define CONFIG_SYS_FLASH_BASE		0xFC000000	/* later mapped here */
-#define CONFIG_SYS_FLASH_SIZE		(64 << 20)
-#endif
-
-#define CONFIG_SYS_NVRAM_BASE		0xE0000000
-#define CONFIG_SYS_UART_BASE		0xE0100000
-#define CONFIG_SYS_IO_BASE		0xE0200000
-
-#define CONFIG_SYS_BOOT_BASE_ADDR	0xFF000000	/* EBC Boot Space */
-#define CONFIG_SYS_FLASH_BASE_PHYS_H	0x4
-#ifdef CONFIG_DEVCONCENTER               /* Devcon-Center has 128 MB of flash */
-#define CONFIG_SYS_FLASH_BASE_PHYS_L	0xC8000000
-#else
-#define CONFIG_SYS_FLASH_BASE_PHYS_L	0xCC000000
-#endif
-#define CONFIG_SYS_FLASH_BASE_PHYS \
-	(((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) \
-	| (u64)CONFIG_SYS_FLASH_BASE_PHYS_L)
-
-#define CONFIG_SYS_OCM_BASE		0xE3000000	/* OCM: 64k */
-#define CONFIG_SYS_SRAM_BASE		0xE8000000	/* SRAM: 256k */
-#define CONFIG_SYS_SRAM_SIZE		(256 << 10)
-#define CONFIG_SYS_LOCAL_CONF_REGS	0xEF000000
-
-#define CONFIG_SYS_AHB_BASE		0xE2000000	/* int. AHB periph. */
-
-/*
- * Initial RAM & stack pointer (placed in OCM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_BASE	/* OCM */
-#define CONFIG_SYS_INIT_RAM_SIZE	(4 << 10)
-#define CONFIG_SYS_GBL_DATA_OFFSET \
-	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
-
-/*
- * Environment
- */
-/*
- * Define here the location of the environment variables (FLASH).
- */
-#define	CONFIG_ENV_IS_IN_FLASH	1	/* use FLASH for environment vars */
-#define CONFIG_SYS_NOR_CS		0	/* NOR chip connected to CSx */
-
-/*
- * FLASH related
- */
-#define CONFIG_SYS_FLASH_CFI		/* The flash is CFI compatible	*/
-#define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/
-#define CONFIG_SYS_FLASH_CFI_AMD_RESET	1	/* Use AMD reset cmd */
-
-#define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE}
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks */
-#ifdef CONFIG_DEVCONCENTER
-#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* max num of sectors per chip*/
-#else
-#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max num of sectors per chip*/
-#endif
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase/ms */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write/ms */
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* buff'd writes (20x faster) */
-#define CONFIG_SYS_FLASH_EMPTY_INFO	/* 'E' for empty sector on flinfo */
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE	0x20000		/* size of one complete sector*/
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
-#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector */
-
-/* Address and size of Redundant Environment Sector	*/
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
-#endif /* CONFIG_ENV_IS_IN_FLASH */
-
-/*
- * DDR SDRAM
- */
-
-#define CONFIG_AUTOCALIB	"silent\0"	/* default is non-verbose    */
-
-#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION	/* IBM DDR autocalibration   */
-#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION	/* dynamic DDR autocal debug */
-#undef CONFIG_PPC4xx_DDR_METHOD_A
-
-/* DDR1/2 SDRAM Device Control Register Data Values */
-/* Memory Queue */
-#define CONFIG_SYS_SDRAM_R0BAS		0x0000f800
-#define CONFIG_SYS_SDRAM_R1BAS		0x00000000
-#define CONFIG_SYS_SDRAM_R2BAS		0x00000000
-#define CONFIG_SYS_SDRAM_R3BAS		0x00000000
-#define CONFIG_SYS_SDRAM_PLBADDULL	0x00000000
-#define CONFIG_SYS_SDRAM_PLBADDUHB	0x00000008
-#define CONFIG_SYS_SDRAM_CONF1LL	0x80001C00
-#define CONFIG_SYS_SDRAM_CONF1HB	0x80001C80
-#define CONFIG_SYS_SDRAM_CONFPATHB	0x10a68000
-
-/* SDRAM Controller */
-#define CONFIG_SYS_SDRAM0_MB0CF		0x00000201
-#define CONFIG_SYS_SDRAM0_MB1CF		0x00000000
-#define CONFIG_SYS_SDRAM0_MB2CF		0x00000000
-#define CONFIG_SYS_SDRAM0_MB3CF		0x00000000
-#define CONFIG_SYS_SDRAM0_MCOPT1	0x05120000
-#define CONFIG_SYS_SDRAM0_MCOPT2	0x00000000
-#define CONFIG_SYS_SDRAM0_MODT0		0x00000000
-#define CONFIG_SYS_SDRAM0_MODT1		0x00000000
-#define CONFIG_SYS_SDRAM0_MODT2		0x00000000
-#define CONFIG_SYS_SDRAM0_MODT3		0x00000000
-#define CONFIG_SYS_SDRAM0_CODT		0x00000020
-#define CONFIG_SYS_SDRAM0_RTR		0x06180000
-#define CONFIG_SYS_SDRAM0_INITPLR0	0xA8380000
-#define CONFIG_SYS_SDRAM0_INITPLR1	0x81900400
-#define CONFIG_SYS_SDRAM0_INITPLR2	0x81020000
-#define CONFIG_SYS_SDRAM0_INITPLR3	0x81030000
-#define CONFIG_SYS_SDRAM0_INITPLR4	0x81010002
-#define CONFIG_SYS_SDRAM0_INITPLR5	0xE4000552
-#define CONFIG_SYS_SDRAM0_INITPLR6	0x81900400
-#define CONFIG_SYS_SDRAM0_INITPLR7	0x8A880000
-#define CONFIG_SYS_SDRAM0_INITPLR8	0x8A880000
-#define CONFIG_SYS_SDRAM0_INITPLR9	0x8A880000
-#define CONFIG_SYS_SDRAM0_INITPLR10	0x8A880000
-#define CONFIG_SYS_SDRAM0_INITPLR11	0x81000452
-#define CONFIG_SYS_SDRAM0_INITPLR12	0x81010382
-#define CONFIG_SYS_SDRAM0_INITPLR13	0x81010002
-#define CONFIG_SYS_SDRAM0_INITPLR14	0x00000000
-#define CONFIG_SYS_SDRAM0_INITPLR15	0x00000000
-#define CONFIG_SYS_SDRAM0_RQDC		0x80000038
-#define CONFIG_SYS_SDRAM0_RFDC		0x00000257
-#define CONFIG_SYS_SDRAM0_RDCC		0x40000000
-#define CONFIG_SYS_SDRAM0_DLCR		0x00000000
-#define CONFIG_SYS_SDRAM0_CLKTR		0x40000000
-#define CONFIG_SYS_SDRAM0_WRDTR		0x86000823
-#define CONFIG_SYS_SDRAM0_SDTR1		0x80201000
-#define CONFIG_SYS_SDRAM0_SDTR2		0x32204232
-#define CONFIG_SYS_SDRAM0_SDTR3		0x090C0D15
-#define CONFIG_SYS_SDRAM0_MMODE		0x00000452
-#define CONFIG_SYS_SDRAM0_MEMODE	0x00000002
-
-#define CONFIG_SYS_MBYTES_SDRAM	256	/* 256MB */
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR		(0xa8>>1)
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
-
-/* I2C bootstrap EEPROM */
-#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR	0x54
-#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET	0
-#define CONFIG_4xx_CONFIG_BLOCKSIZE		16
-
-/* RTC configuration */
-#define CONFIG_RTC_DS1337	1
-#define CONFIG_SYS_I2C_RTC_ADDR	0x68
-
-/*
- * Ethernet
- */
-#define CONFIG_IBM_EMAC4_V4	1
-
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-
-#define CONFIG_PHY_ADDR		2	/* PHY address, See schematics	*/
-#define CONFIG_PHY1_ADDR	3
-
-#define CONFIG_PHY_RESET	1	/* reset phy upon startup	*/
-#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
-#define CONFIG_PHY_DYNAMIC_ANEG	1
-
-/*
- * USB-OHCI
- */
-#define CONFIG_USB_OHCI_NEW
-#undef CONFIG_SYS_OHCI_BE_CONTROLLER	/* 460EX has little endian descriptors*/
-#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS	/* 460EX has little endian register */
-#define CONFIG_SYS_OHCI_USE_NPS		/* force NoPowerSwitching mode */
-#define CONFIG_SYS_USB_OHCI_REGS_BASE	(CONFIG_SYS_AHB_BASE | 0xd0000)
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"ppc440"
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
-
-/*
- * Default environment variables
- */
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	CONFIG_AMCC_DEF_ENV						\
-	CONFIG_AMCC_DEF_ENV_POWERPC					\
-	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
-	"kernel_addr=fc000000\0"					\
-	"fdt_addr=fc1e0000\0"						\
-	"ramdisk_addr=fc200000\0"					\
-	"pciconfighost=1\0"						\
-	"pcie_mode=RP:RP\0"						\
-	""
-
-/*
- * Commands additional to the ones defined in amcc-common.h
- */
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_SDRAM
-
-/* Partitions */
-
-/*
- * PCI stuff
- */
-/* General PCI */
-#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
-#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup  */
-#define CONFIG_PCI_CONFIG_HOST_BRIDGE
-#define CONFIG_PCI_DISABLE_PCIE
-
-/* Board-specific PCI */
-#define CONFIG_SYS_PCI_TARGET_INIT	/* let board init pci target */
-#undef	CONFIG_SYS_PCI_MASTER_INIT
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014	/* IBM */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */
-
-/*
- * External Bus Controller (EBC) Setup
- */
-
-/*
- * CompactCenter has 64MBytes of NOR FLASH (Spansion 29GL512), but the
- * boot EBC mapping only supports a maximum of 16MBytes
- * (4.ff00.0000 - 4.ffff.ffff).
- * To solve this problem, the FLASH has to get remapped to another
- * EBC address which accepts bigger regions:
- *
- * 0xfc00.0000 -> 4.cc00.0000
- */
-
-/* Memory Bank 0 (NOR-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB0AP		0x10055e00
-#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_BOOT_BASE_ADDR | 0x9a000)
-
-/* Memory Bank 1 (NVRAM) initialization	*/
-#define CONFIG_SYS_EBC_PB1AP		0x02815480
-/* BAS=NVRAM,BS=1MB,BU=R/W,BW=8bit*/
-#define CONFIG_SYS_EBC_PB1CR		(CONFIG_SYS_NVRAM_BASE | 0x18000)
-
-/* Memory Bank 2 (UART) initialization	*/
-#define CONFIG_SYS_EBC_PB2AP		0x02815480
-/* BAS=UART,BS=1MB,BU=R/W,BW=16bit*/
-#define CONFIG_SYS_EBC_PB2CR		(CONFIG_SYS_UART_BASE | 0x1A000)
-
-/* Memory Bank 3 (IO) initialization */
-#define CONFIG_SYS_EBC_PB3AP		0x02815480
-/* BAS=IO,BS=1MB,BU=R/W,BW=16bit*/
-#define CONFIG_SYS_EBC_PB3CR		(CONFIG_SYS_IO_BASE | 0x1A000)
-
-/*
- * PPC4xx GPIO Configuration
- */
-/* 460EX: Use USB configuration */
-#define CONFIG_SYS_4xx_GPIO_TABLE { /*	  Out		  GPIO	Alternate1	Alternate2	Alternate3 */ \
-{											\
-/* GPIO Core 0 */									\
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0	GMC1TxD(0)	USB2HostD(0)	*/	\
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1	GMC1TxD(1)	USB2HostD(1)	*/	\
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO2	GMC1TxD(2)	USB2HostD(2)	*/	\
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO3	GMC1TxD(3)	USB2HostD(3)	*/	\
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO4	GMC1TxD(4)	USB2HostD(4)	*/	\
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO5	GMC1TxD(5)	USB2HostD(5)	*/	\
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO6	GMC1TxD(6)	USB2HostD(6)	*/	\
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO7	GMC1TxD(7)	USB2HostD(7)	*/	\
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8	GMC1RxD(0)	USB2OTGD(0)	*/	\
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9	GMC1RxD(1)	USB2OTGD(1)	*/	\
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2)	USB2OTGD(2)	*/	\
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3)	USB2OTGD(3)	*/	\
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4)	USB2OTGD(4)	*/	\
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5)	USB2OTGD(5)	*/	\
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6)	USB2OTGD(6)	*/	\
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7)	USB2OTGD(7)	*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_SEL,  GPIO_OUT_0}, /* GPIO16 GMC1TxER	USB2HostStop	*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD		USB2HostNext	*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER	USB2HostDir	*/	\
-{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO19 GMC1TxEN	USB2OTGStop	*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS	USB2OTGNext	*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV	USB2OTGDir	*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY				*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN				*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN				*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE				*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE				*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0)				*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1)				*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2)				*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0	DMAReq2		IRQ(7)*/ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1	DMAAck2		IRQ(8)*/ \
-},											\
-{											\
-/* GPIO Core 1 */									\
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2	EOT2/TC2	IRQ(9)*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3	DMAReq3		IRQ(4)*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N	UART1_DSR_CTS_N	UART2_SOUT*/ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3	UART3_SIN*/ \
-{GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N	EOT3/TC3	UART3_SOUT*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N	UART1_SOUT	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N	UART1_SIN	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3)				*/	\
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1)				*/	\
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2)				*/	\
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3)		DMAReq1		IRQ(10)*/ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4)		DMAAck1		IRQ(11)*/ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5)		EOT/TC1		IRQ(12)*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5)	DMAReq0		IRQ(13)*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6)	DMAAck0		IRQ(14)*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7)	EOT/TC0		IRQ(15)*/ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50  USB_SERVICE_SUSPEND_N		*/	\
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO51  SPI_CSS_N			*/	\
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO52  FPGA_PROGRAM_UC_N		*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53  FPGA_INIT_UC_N		*/	\
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO54  WD_STROBE			*/	\
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55  LED_2_OUT			*/	\
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO56  LED_1_OUT			*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO61  STARTUP_FINISHED_N		*/	\
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO62  STARTUP_FINISHED		*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63  SERVICE_PORT_ACTIVE		*/	\
-}											\
-}
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/io.h b/include/configs/io.h
deleted file mode 100644
index 3fde912bcf..0000000000
--- a/include/configs/io.h
+++ /dev/null
@@ -1,228 +0,0 @@
-/*
- * (C) Copyright 2010
- * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_405EP		1	/* this is a PPC405 CPU */
-#define CONFIG_IO	        1	/*  on a Io board */
-
-#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
-
-/*
- * Include common defines/options for all AMCC eval boards
- */
-#define CONFIG_HOSTNAME		io
-#include "amcc-common.h"
-
-#define CONFIG_BOARD_EARLY_INIT_R
-#define CONFIG_MISC_INIT_R
-#define CONFIG_LAST_STAGE_INIT
-
-#define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll   */
-
-/*
- * Configure PLL
- */
-#define PLLMR0_DEFAULT PLLMR0_266_133_66
-#define PLLMR1_DEFAULT PLLMR1_266_133_66
-
-#define CONFIG_ENV_IS_IN_FLASH	/* use FLASH for environment vars */
-
-/*
- * Default environment variables
- */
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	CONFIG_AMCC_DEF_ENV						\
-	CONFIG_AMCC_DEF_ENV_POWERPC					\
-	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
-	"kernel_addr=fc000000\0"					\
-	"fdt_addr=fc1e0000\0"						\
-	"ramdisk_addr=fc200000\0"					\
-	""
-
-#define CONFIG_PHY_ADDR		4	/* PHY address			*/
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#define CONFIG_PHY1_ADDR	0xc	/* EMAC1 PHY address		*/
-#define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ
-
-/*
- * Commands additional to the ones defined in amcc-common.h
- */
-
-/*
- * SDRAM configuration (please see cpu/ppc/sdram.[ch])
- */
-#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0 */
-
-/* SDRAM timings used in datasheet */
-#define CONFIG_SYS_SDRAM_CL             3	/* CAS latency */
-#define CONFIG_SYS_SDRAM_tRP           20	/* PRECHARGE command period */
-#define CONFIG_SYS_SDRAM_tRC           66	/* ACTIVE-to-ACTIVE period */
-#define CONFIG_SYS_SDRAM_tRCD          20	/* ACTIVE-to-READ delay */
-#define CONFIG_SYS_SDRAM_tRFC          66	/* Auto refresh period */
-
-/*
- * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
- * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
- * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
- * The Linux BASE_BAUD define should match this configuration.
- *    baseBaud = cpuClock/(uartDivisor*16)
- * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
- * set Linux BASE_BAUD to 403200.
- */
-#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
-#undef  CONFIG_SYS_EXT_SERIAL_CLOCK	/* external serial clock */
-#undef  CONFIG_SYS_405_UART_ERRATA_59	/* 405GP/CR Rev. D silicon */
-#define CONFIG_SYS_BASE_BAUD		691200
-
-/*
- * I2C stuff
- */
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		100000
-
-/* Temp sensor/hwmon/dtt */
-
-/*
- * FLASH organization
- */
-#define CONFIG_SYS_FLASH_CFI		/* The flash is CFI compatible	*/
-#define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/
-
-#define CONFIG_SYS_FLASH_BASE		0xFC000000
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max num of sectors per chip*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase/ms */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write/ms */
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buff'd writes */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO	/* 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* no warn upon unknown flash */
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE	0x20000	/* size of one complete sector */
-#define CONFIG_ENV_ADDR		((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
-#define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector */
-
-/* Address and size of Redundant Environment Sector	*/
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
-#endif
-
-/* Gbit PHYs */
-#define CONFIG_BITBANGMII		/* bit-bang MII PHY management */
-#define CONFIG_BITBANGMII_MULTI
-
-#define CONFIG_SYS_MDIO_PIN  (0x80000000 >> 13)	/* our MDIO is GPIO0 */
-#define CONFIG_SYS_MDC_PIN   (0x80000000 >> 7)	/* our MDC  is GPIO7 */
-
-#define CONFIG_SYS_GBIT_MII_BUSNAME	"io_miiphy"
-
-/*
- * PPC405 GPIO Configuration
- */
-#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO	Alternate1	*/ \
-{ \
-/* GPIO Core 0 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO0	PerBLast */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO1	TS1E */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO2	TS2E */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO3	TS1O */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO4	TS2O */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1      }, /* GPIO5	TS3 */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO6	TS4 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1      }, /* GPIO7	TS5 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO8	TS6 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO9	TrcClk */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10	PerCS1 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11	PerCS2 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12	PerCS3 */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO13	PerCS4 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14	PerAddr03 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15	PerAddr04 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16	PerAddr05 */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17	IRQ0 */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18	IRQ1 */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19	IRQ2 */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO20	IRQ3 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO21	IRQ4 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO22	IRQ5 */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO23	IRQ6 */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24	UART0_DCD */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25	UART0_DSR */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26	UART0_RI */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27	UART0_DTR */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28	UART1_Rx */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29	UART1_Tx */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO30	RejectPkt0 */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO31	RejectPkt1 */ \
-} \
-}
-
-/*
- * Definitions for initial stack pointer and data area (in data cache)
- */
-/* use on chip memory (OCM) for temperary stack until sdram is tested */
-#define CONFIG_SYS_TEMP_STACK_OCM        1
-
-/* On Chip Memory location */
-#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
-#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE
-
-#define CONFIG_SYS_GBL_DATA_OFFSET \
-	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/*
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (NOR-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB0AP		0xa382a880
-/* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit */
-#define CONFIG_SYS_EBC_PB0CR		0xFC0DA000
-
-/* Memory Bank 1 (NVRAM) initializatio */
-#define CONFIG_SYS_EBC_PB1AP		0x92015480
-/* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit  */
-#define CONFIG_SYS_EBC_PB1CR		0x7f318000
-
-/* Memory Bank 2 (FPGA) initialization */
-#define CONFIG_SYS_FPGA0_BASE		0x7f100000
-#define CONFIG_SYS_EBC_PB2AP		0x02025080
-/* BAS=0x7f1,BS=1MB,BU=R/W,BW=16bit */
-#define CONFIG_SYS_EBC_PB2CR		0x7f11a000
-
-#define CONFIG_SYS_FPGA_BASE(k)		CONFIG_SYS_FPGA0_BASE
-#define CONFIG_SYS_FPGA_DONE(k)		0x0010
-
-#define CONFIG_SYS_FPGA_COUNT		1
-
-#define CONFIG_SYS_FPGA_PTR \
-	{ (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE }
-
-#define CONFIG_SYS_FPGA_COMMON
-
-/* Memory Bank 3 (Latches) initialization */
-#define CONFIG_SYS_LATCH_BASE		0x7f200000
-#define CONFIG_SYS_EBC_PB3AP		0xa2015480
-/* BAS=0x7f2,BS=1MB,BU=R/W,BW=16bit */
-#define CONFIG_SYS_EBC_PB3CR		0x7f21a000
-
-#define CONFIG_SYS_LATCH0_RESET		0xffff
-#define CONFIG_SYS_LATCH0_BOOT		0xffff
-#define CONFIG_SYS_LATCH1_RESET		0xffbf
-#define CONFIG_SYS_LATCH1_BOOT		0xffff
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/io64.h b/include/configs/io64.h
deleted file mode 100644
index 1b58f04540..0000000000
--- a/include/configs/io64.h
+++ /dev/null
@@ -1,533 +0,0 @@
-/*
- * (C) Copyright 2011
- * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
- *
- * based on kilauea.h
- * by Stefan Roese, DENX Software Engineering, sr@denx.de.
- * and Grant Erickson <gerickson@nuovations.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/************************************************************************
- * io64.h - configuration for Guntermann & Drunck Io64 (405EX)
- ***********************************************************************/
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- *----------------------------------------------------------------------*/
-#define CONFIG_IO64		1		/* Board is Io64 */
-#define CONFIG_405EX		1		/* Specifc 405EX support*/
-#define CONFIG_SYS_CLK_FREQ	33333333	/* ext frequency to pll */
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE	0xFFFA0000
-#endif
-
-/*
- * CHIP_21 errata
- */
-#define CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY
-
-/*
- * Include common defines/options for all AMCC eval boards
- */
-#define CONFIG_HOSTNAME		io64
-#include "amcc-common.h"
-
-#define CONFIG_BOARD_EARLY_INIT_R
-#define CONFIG_MISC_INIT_R
-#define CONFIG_LAST_STAGE_INIT
-
-/*-----------------------------------------------------------------------
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_FLASH_BASE		0xFC000000
-#define CONFIG_SYS_NVRAM_BASE		0xF0000000
-#define CONFIG_SYS_FPGA0_BASE		0xF0100000
-#define CONFIG_SYS_FPGA1_BASE		0xF0108000
-#define CONFIG_SYS_LATCH_BASE		0xF0200000
-
-/*-----------------------------------------------------------------------
- * Initial RAM & Stack Pointer Configuration Options
- *
- *   There are traditionally three options for the primordial
- *   (i.e. initial) stack usage on the 405-series:
- *
- *      1) On-chip Memory (OCM) (i.e. SRAM)
- *      2) Data cache
- *      3) SDRAM
- *
- *   For the 405EX(r), there is no OCM, so we are left with (2) or (3)
- *   the latter of which is less than desireable since it requires
- *   setting up the SDRAM and ECC in assembly code.
- *
- *   To use (2), define 'CONFIG_SYS_INIT_DCACHE_CS' to be an unused chip
- *   select on the External Bus Controller (EBC) and then select a
- *   value for 'CONFIG_SYS_INIT_RAM_ADDR' outside of the range of valid,
- *   physical SDRAM. Otherwise, undefine 'CONFIG_SYS_INIT_DCACHE_CS' and
- *   select a value for 'CONFIG_SYS_INIT_RAM_ADDR' within the range of valid,
- *   physical SDRAM to use (3).
- *-----------------------------------------------------------------------*/
-
-#define CONFIG_SYS_INIT_DCACHE_CS	4
-
-#if defined(CONFIG_SYS_INIT_DCACHE_CS)
-#define CONFIG_SYS_INIT_RAM_ADDR \
-	(CONFIG_SYS_SDRAM_BASE + (1 << 30))	/*  1 GiB */
-#else
-#define CONFIG_SYS_INIT_RAM_ADDR \
-	(CONFIG_SYS_SDRAM_BASE + (32 << 20))	/* 32 MiB */
-#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
-
-#define CONFIG_SYS_INIT_RAM_SIZE \
-	(4 << 10)				/*  4 KiB */
-#define CONFIG_SYS_GBL_DATA_OFFSET \
-	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-/*
- * If the data cache is being used for the primordial stack and global
- * data area, the POST word must be placed somewhere else. The General
- * Purpose Timer (GPT) is unused by u-boot and the kernel and preserves
- * its compare and mask register contents across reset, so it is used
- * for the POST word.
- */
-
-#if defined(CONFIG_SYS_INIT_DCACHE_CS)
-# define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-# define CONFIG_SYS_POST_WORD_ADDR \
-	(CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
-#else
-# define CONFIG_SYS_INIT_EXTRA_SIZE	16
-# define CONFIG_SYS_INIT_SP_OFFSET \
-	(CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_EXTRA_SIZE)
-# define CONFIG_SYS_OCM_DATA_ADDR	CONFIG_SYS_INIT_RAM_ADDR
-#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
-
-/*-----------------------------------------------------------------------
- * Serial Port
- *----------------------------------------------------------------------*/
-#define CONFIG_CONS_INDEX	1	/* Use UART0 */
-#define CONFIG_SYS_BASE_BAUD	691200
-
-/*-----------------------------------------------------------------------
- * Environment
- *----------------------------------------------------------------------*/
-#define CONFIG_ENV_IS_IN_FLASH	1	/* use FLASH for environment vars */
-
-/*-----------------------------------------------------------------------
- * FLASH related
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_FLASH_CFI		/* The flash is CFI compatible */
-#define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver */
-
-#define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE}
-#define CONFIG_SYS_MAX_FLASH_BANKS	1
-#define CONFIG_SYS_MAX_FLASH_SECT	512
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE	0x20000	/* size of one complete sector */
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
-#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector */
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
-#endif /* CONFIG_ENV_IS_IN_FLASH */
-
-/* Gbit PHYs */
-#define CONFIG_BITBANGMII		/* bit-bang MII PHY management */
-#define CONFIG_BITBANGMII_MULTI
-
-#define CONFIG_SYS_MDIO_PIN  (0x80000000 >> 12)	/* MDIO is GPIO12 */
-#define CONFIG_SYS_MDC_PIN   (0x80000000 >> 13)	/* MDC  is GPIO13 */
-
-#define CONFIG_SYS_GBIT_MII_BUSNAME	"io_miiphy0"
-
-#define CONFIG_SYS_MDIO1_PIN  (0x80000000 >> 2)	/* MDIO is GPIO2 */
-#define CONFIG_SYS_MDC1_PIN   (0x80000000 >> 3)	/* MDC  is GPIO3 */
-
-#define CONFIG_SYS_GBIT_MII1_BUSNAME	"io_miiphy1"
-
-/*-----------------------------------------------------------------------
- * DDR SDRAM
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MBYTES_SDRAM        (128)	/* 128MB */
-
-/*
- * CONFIG_PPC4xx_DDR_AUTOCALIBRATION
- *
- * Note: DDR Autocalibration Method_A scans the full range of possible PPC4xx
- *       SDRAM Controller DDR autocalibration values and takes a lot longer
- *       to run than Method_B.
- * (See the Method_A and Method_B algorithm discription in the file:
- *	arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c)
- * Define CONFIG_PPC4xx_DDR_METHOD_A to use DDR autocalibration Method_A
- *
- * DDR Autocalibration Method_B is the default.
- */
-#define	CONFIG_PPC4xx_DDR_AUTOCALIBRATION
-#define	DEBUG_PPC4xx_DDR_AUTOCALIBRATION
-#undef	CONFIG_PPC4xx_DDR_METHOD_A
-
-#define	CONFIG_SYS_SDRAM0_MB0CF_BASE	((0 << 20) + CONFIG_SYS_SDRAM_BASE)
-
-/* DDR1/2 SDRAM Device Control Register Data Values */
-#define CONFIG_SYS_SDRAM0_MB0CF	((CONFIG_SYS_SDRAM0_MB0CF_BASE >> 3) | \
-				 SDRAM_RXBAS_SDSZ_128MB | \
-				 SDRAM_RXBAS_SDAM_MODE2 | \
-				 SDRAM_RXBAS_SDBE_ENABLE)
-#define CONFIG_SYS_SDRAM0_MB1CF	SDRAM_RXBAS_SDBE_DISABLE
-#define CONFIG_SYS_SDRAM0_MB2CF	SDRAM_RXBAS_SDBE_DISABLE
-#define CONFIG_SYS_SDRAM0_MB3CF	SDRAM_RXBAS_SDBE_DISABLE
-#define CONFIG_SYS_SDRAM0_MCOPT1	(SDRAM_MCOPT1_PMU_OPEN | \
-				 SDRAM_MCOPT1_4_BANKS | \
-				 SDRAM_MCOPT1_DDR2_TYPE | \
-				 SDRAM_MCOPT1_QDEP | \
-				 SDRAM_MCOPT1_DCOO_DISABLED)
-#define CONFIG_SYS_SDRAM0_MCOPT2	0x00000000
-#define CONFIG_SYS_SDRAM0_MODT0	(SDRAM_MODT_EB0W_ENABLE | \
-				 SDRAM_MODT_EB0R_ENABLE)
-#define CONFIG_SYS_SDRAM0_MODT1	0x00000000
-#define CONFIG_SYS_SDRAM0_CODT		(SDRAM_CODT_RK0R_ON | \
-				 SDRAM_CODT_CKLZ_36OHM | \
-				 SDRAM_CODT_DQS_1_8_V_DDR2 | \
-				 SDRAM_CODT_IO_NMODE)
-#define CONFIG_SYS_SDRAM0_RTR		SDRAM_RTR_RINT_ENCODE(1560)
-#define CONFIG_SYS_SDRAM0_INITPLR0	(SDRAM_INITPLR_ENABLE | \
-		SDRAM_INITPLR_IMWT_ENCODE(80) | \
-		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_NOP))
-#define CONFIG_SYS_SDRAM0_INITPLR1	(SDRAM_INITPLR_ENABLE | \
-		SDRAM_INITPLR_IMWT_ENCODE(3) | \
-		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \
-		SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
-		SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
-#define CONFIG_SYS_SDRAM0_INITPLR2	(SDRAM_INITPLR_ENABLE | \
-		SDRAM_INITPLR_IMWT_ENCODE(2) | \
-		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
-		SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR2) | \
-		SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR2_TEMP_COMMERCIAL))
-#define CONFIG_SYS_SDRAM0_INITPLR3	(SDRAM_INITPLR_ENABLE | \
-		SDRAM_INITPLR_IMWT_ENCODE(2) | \
-		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
-		SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR3) | \
-		SDRAM_INITPLR_IMA_ENCODE(0))
-#define CONFIG_SYS_SDRAM0_INITPLR4	(SDRAM_INITPLR_ENABLE | \
-		SDRAM_INITPLR_IMWT_ENCODE(2) | \
-		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
-		SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
-		SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_DQS_DISABLE | \
-					 JEDEC_MA_EMR_RTT_75OHM))
-#define CONFIG_SYS_SDRAM0_INITPLR5	(SDRAM_INITPLR_ENABLE | \
-		SDRAM_INITPLR_IMWT_ENCODE(2) | \
-		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
-		SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
-		SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
-					 JEDEC_MA_MR_CL_DDR2_5_0_CLK | \
-					 JEDEC_MA_MR_BLEN_4 | \
-					 JEDEC_MA_MR_DLL_RESET))
-#define CONFIG_SYS_SDRAM0_INITPLR6	(SDRAM_INITPLR_ENABLE | \
-		SDRAM_INITPLR_IMWT_ENCODE(3) | \
-		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \
-		SDRAM_INITPLR_IBA_ENCODE(0x0) | \
-		SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
-#define CONFIG_SYS_SDRAM0_INITPLR7	(SDRAM_INITPLR_ENABLE | \
-		SDRAM_INITPLR_IMWT_ENCODE(26) | \
-		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
-#define CONFIG_SYS_SDRAM0_INITPLR8	(SDRAM_INITPLR_ENABLE | \
-		SDRAM_INITPLR_IMWT_ENCODE(26) | \
-		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
-#define CONFIG_SYS_SDRAM0_INITPLR9	(SDRAM_INITPLR_ENABLE | \
-		SDRAM_INITPLR_IMWT_ENCODE(26) | \
-		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
-#define CONFIG_SYS_SDRAM0_INITPLR10	(SDRAM_INITPLR_ENABLE | \
-		SDRAM_INITPLR_IMWT_ENCODE(26) | \
-		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
-#define CONFIG_SYS_SDRAM0_INITPLR11	(SDRAM_INITPLR_ENABLE | \
-		SDRAM_INITPLR_IMWT_ENCODE(2) | \
-		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
-		SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
-		SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
-					 JEDEC_MA_MR_CL_DDR2_5_0_CLK | \
-					 JEDEC_MA_MR_BLEN_4))
-#define CONFIG_SYS_SDRAM0_INITPLR12	(SDRAM_INITPLR_ENABLE | \
-		SDRAM_INITPLR_IMWT_ENCODE(2) | \
-		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
-		SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
-		SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_ENTER | \
-					 JEDEC_MA_EMR_RDQS_DISABLE | \
-					 JEDEC_MA_EMR_DQS_DISABLE | \
-					 JEDEC_MA_EMR_RTT_DISABLED | \
-					 JEDEC_MA_EMR_ODS_NORMAL))
-#define CONFIG_SYS_SDRAM0_INITPLR13	(SDRAM_INITPLR_ENABLE | \
-		SDRAM_INITPLR_IMWT_ENCODE(2) | \
-		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
-		SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
-		SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_EXIT | \
-					 JEDEC_MA_EMR_RDQS_DISABLE | \
-					 JEDEC_MA_EMR_DQS_DISABLE | \
-					 JEDEC_MA_EMR_RTT_DISABLED | \
-					 JEDEC_MA_EMR_ODS_NORMAL))
-#define CONFIG_SYS_SDRAM0_INITPLR14	(SDRAM_INITPLR_DISABLE)
-#define CONFIG_SYS_SDRAM0_INITPLR15	(SDRAM_INITPLR_DISABLE)
-#define CONFIG_SYS_SDRAM0_RQDC		(SDRAM_RQDC_RQDE_ENABLE | \
-				 SDRAM_RQDC_RQFD_ENCODE(56))
-#define CONFIG_SYS_SDRAM0_RFDC		SDRAM_RFDC_RFFD_ENCODE(521)
-#define CONFIG_SYS_SDRAM0_RDCC		(SDRAM_RDCC_RDSS_T2)
-#define CONFIG_SYS_SDRAM0_DLCR		(SDRAM_DLCR_DCLM_AUTO | \
-				 SDRAM_DLCR_DLCS_CONT_DONE | \
-				 SDRAM_DLCR_DLCV_ENCODE(165))
-#define CONFIG_SYS_SDRAM0_CLKTR	(SDRAM_CLKTR_CLKP_180_DEG_ADV)
-#define CONFIG_SYS_SDRAM0_WRDTR	0x00000000
-#define CONFIG_SYS_SDRAM0_SDTR1	(SDRAM_SDTR1_LDOF_2_CLK | \
-				 SDRAM_SDTR1_RTW_2_CLK | \
-				 SDRAM_SDTR1_WTWO_1_CLK | \
-				 SDRAM_SDTR1_RTRO_1_CLK)
-#define CONFIG_SYS_SDRAM0_SDTR2	(SDRAM_SDTR2_RCD_3_CLK | \
-				 SDRAM_SDTR2_WTR_2_CLK | \
-				 SDRAM_SDTR2_XSNR_32_CLK | \
-				 SDRAM_SDTR2_WPC_4_CLK | \
-				 SDRAM_SDTR2_RPC_2_CLK | \
-				 SDRAM_SDTR2_RP_3_CLK | \
-				 SDRAM_SDTR2_RRD_2_CLK)
-#define CONFIG_SYS_SDRAM0_SDTR3	(SDRAM_SDTR3_RAS_ENCODE(9) | \
-				 SDRAM_SDTR3_RC_ENCODE(12) | \
-				 SDRAM_SDTR3_XCS | \
-				 SDRAM_SDTR3_RFC_ENCODE(21))
-#define CONFIG_SYS_SDRAM0_MMODE	(SDRAM_MMODE_WR_DDR2_3_CYC | \
-				 SDRAM_MMODE_DCL_DDR2_5_0_CLK | \
-				 SDRAM_MMODE_BLEN_4)
-#define CONFIG_SYS_SDRAM0_MEMODE	(SDRAM_MEMODE_DQS_DISABLE | \
-				 SDRAM_MEMODE_RTT_75OHM)
-
-/*-----------------------------------------------------------------------
- * I2C
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0	400000
-
-#define CONFIG_PCA9698		1	/* NXP PCA9698 */
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR	0x52	/* I2C boot EEPROM (24C02BN) */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
-
-/* I2C bootstrap EEPROM */
-#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR	0x54
-#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET	0
-#define CONFIG_4xx_CONFIG_BLOCKSIZE		16
-
-/*-----------------------------------------------------------------------
- * Ethernet
- *----------------------------------------------------------------------*/
-#define CONFIG_M88E1111_PHY	1
-#define CONFIG_IBM_EMAC4_V4	1
-#define CONFIG_EMAC_PHY_MODE	EMAC_PHY_MODE_RGMII_RGMII
-#define CONFIG_PHY_ADDR		0x12	/* PHY address, See schematics */
-
-#define CONFIG_PHY_RESET	1	/* reset phy upon startup */
-#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
-
-#define CONFIG_HAS_ETH0		1
-
-#define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"   */
-#define CONFIG_PHY1_ADDR	0x13
-
-/* Debug messages for the DDR autocalibration */
-#define CONFIG_AUTOCALIB		"silent\0"
-
-/*
- * Default environment variables
- */
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	CONFIG_AMCC_DEF_ENV						\
-	CONFIG_AMCC_DEF_ENV_POWERPC					\
-	CONFIG_AMCC_DEF_ENV_PPC_OLD					\
-	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
-	"logversion=2\0"						\
-	"kernel_addr=fc000000\0"					\
-	"fdt_addr=fc1e0000\0"						\
-	"ramdisk_addr=fc200000\0"					\
-	"pciconfighost=1\0"						\
-	"pcie_mode=RP:RP\0"						\
-	""
-
-/*
- * Commands additional to the ones defined in amcc-common.h
- */
-
-#define CONFIG_SYS_POST_MEMORY_ON	CONFIG_SYS_POST_MEMORY
-
-/* POST support */
-#define CONFIG_POST		(CONFIG_SYS_POST_CACHE		| \
-				 CONFIG_SYS_POST_CPU		| \
-				 CONFIG_SYS_POST_ETHER		| \
-				 CONFIG_SYS_POST_I2C		| \
-				 CONFIG_SYS_POST_MEMORY_ON	| \
-				 CONFIG_SYS_POST_UART)
-
-/* Define here the base-addresses of the UARTs to test in POST */
-#define CONFIG_SYS_POST_UART_TABLE	{ CONFIG_SYS_NS16550_COM1, \
-			CONFIG_SYS_NS16550_COM2 }
-
-#define CONFIG_LOGBUFFER
-#define CONFIG_SYS_POST_CACHE_ADDR	0x00800000 /* free virtual address */
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- *----------------------------------------------------------------------*/
-
-/* Memory Bank 0 (NOR-flash) */
-#define CONFIG_SYS_EBC_PB0AP	(EBC_BXAP_BME_DISABLED		|	\
-				 EBC_BXAP_TWT_ENCODE(11)	|	\
-				 EBC_BXAP_BCE_DISABLE		|	\
-				 EBC_BXAP_BCT_2TRANS		|	\
-				 EBC_BXAP_CSN_ENCODE(0)		|	\
-				 EBC_BXAP_OEN_ENCODE(0)		|	\
-				 EBC_BXAP_WBN_ENCODE(1)		|	\
-				 EBC_BXAP_WBF_ENCODE(2)		|	\
-				 EBC_BXAP_TH_ENCODE(2)		|	\
-				 EBC_BXAP_RE_DISABLED		|	\
-				 EBC_BXAP_SOR_NONDELAYED	|	\
-				 EBC_BXAP_BEM_WRITEONLY		|	\
-				 EBC_BXAP_PEN_DISABLED)
-#define CONFIG_SYS_EBC_PB0CR	(EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
-				 EBC_BXCR_BS_64MB		|	\
-				 EBC_BXCR_BU_RW			|	\
-				 EBC_BXCR_BW_16BIT)
-
-/* Memory Bank 1 (NVRAM/Uart) */
-#define CONFIG_SYS_EBC_PB1AP	(EBC_BXAP_BME_ENABLED		|	\
-				 EBC_BXAP_FWT_ENCODE(8)		|	\
-				 EBC_BXAP_BWT_ENCODE(4)		|	\
-				 EBC_BXAP_BCE_DISABLE		|	\
-				 EBC_BXAP_BCT_2TRANS		|	\
-				 EBC_BXAP_CSN_ENCODE(0)		|	\
-				 EBC_BXAP_OEN_ENCODE(1)		|	\
-				 EBC_BXAP_WBN_ENCODE(1)		|	\
-				 EBC_BXAP_WBF_ENCODE(1)		|	\
-				 EBC_BXAP_TH_ENCODE(2)		|	\
-				 EBC_BXAP_RE_DISABLED		|	\
-				 EBC_BXAP_SOR_NONDELAYED	|	\
-				 EBC_BXAP_BEM_WRITEONLY		|	\
-				 EBC_BXAP_PEN_DISABLED)
-#define CONFIG_SYS_EBC_PB1CR	(EBC_BXCR_BAS_ENCODE(CONFIG_SYS_NVRAM_BASE) | \
-				 EBC_BXCR_BS_1MB		|	\
-				 EBC_BXCR_BU_RW			|	\
-				 EBC_BXCR_BW_8BIT)
-
-/* Memory Bank 2 (FPGA) */
-#define CONFIG_SYS_EBC_PB2AP	(EBC_BXAP_BME_DISABLED		|	\
-				 EBC_BXAP_TWT_ENCODE(5)		|	\
-				 EBC_BXAP_BCE_DISABLE		|	\
-				 EBC_BXAP_BCT_2TRANS		|	\
-				 EBC_BXAP_CSN_ENCODE(0)		|	\
-				 EBC_BXAP_OEN_ENCODE(2)		|	\
-				 EBC_BXAP_WBN_ENCODE(1)		|	\
-				 EBC_BXAP_WBF_ENCODE(1)		|	\
-				 EBC_BXAP_TH_ENCODE(0)		|	\
-				 EBC_BXAP_RE_DISABLED		|	\
-				 EBC_BXAP_SOR_NONDELAYED	|	\
-				 EBC_BXAP_BEM_WRITEONLY		|	\
-				 EBC_BXAP_PEN_DISABLED)
-#define CONFIG_SYS_EBC_PB2CR	(EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA0_BASE) | \
-				 EBC_BXCR_BS_1MB		|	\
-				 EBC_BXCR_BU_RW			|	\
-				 EBC_BXCR_BW_16BIT)
-
-/* Memory Bank 3 (Latches) */
-#define CONFIG_SYS_EBC_PB3AP	(EBC_BXAP_BME_ENABLED		|	\
-				 EBC_BXAP_FWT_ENCODE(8)		|	\
-				 EBC_BXAP_BWT_ENCODE(4)		|	\
-				 EBC_BXAP_BCE_DISABLE		|	\
-				 EBC_BXAP_BCT_2TRANS		|	\
-				 EBC_BXAP_CSN_ENCODE(0)		|	\
-				 EBC_BXAP_OEN_ENCODE(1)		|	\
-				 EBC_BXAP_WBN_ENCODE(1)		|	\
-				 EBC_BXAP_WBF_ENCODE(1)		|	\
-				 EBC_BXAP_TH_ENCODE(2)		|	\
-				 EBC_BXAP_RE_DISABLED		|	\
-				 EBC_BXAP_SOR_NONDELAYED	|	\
-				 EBC_BXAP_BEM_WRITEONLY		|	\
-				 EBC_BXAP_PEN_DISABLED)
-#define CONFIG_SYS_EBC_PB3CR	(EBC_BXCR_BAS_ENCODE(CONFIG_SYS_LATCH_BASE) | \
-				 EBC_BXCR_BS_1MB		|	\
-				 EBC_BXCR_BU_RW			|	\
-				 EBC_BXCR_BW_16BIT)
-
-/* EBC peripherals */
-
-#define CONFIG_SYS_FPGA_BASE(k) \
-	(k ? CONFIG_SYS_FPGA1_BASE : CONFIG_SYS_FPGA0_BASE)
-
-#define CONFIG_SYS_FPGA_DONE(k) \
-	(k ? 0x0040 : 0x0080)
-
-#define CONFIG_SYS_FPGA_COUNT		2
-
-#define CONFIG_SYS_FPGA_PTR { \
-	(struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, \
-	(struct ihs_fpga *)CONFIG_SYS_FPGA1_BASE }
-
-#define CONFIG_SYS_FPGA_COMMON
-
-#define CONFIG_SYS_LATCH0_RESET		0xffff
-#define CONFIG_SYS_LATCH0_BOOT		0xffff
-#define CONFIG_SYS_LATCH1_RESET		0xffbf
-#define CONFIG_SYS_LATCH1_BOOT		0xffff
-
-/*-----------------------------------------------------------------------
- * GPIO Setup
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_4xx_GPIO_TABLE { /*	  Out		GPIO */ \
-{ \
-/* GPIO Core 0 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1     }, /* GPIO0 */ \
-{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG}, /* GPIO1 */ \
-{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG}, /* GPIO2 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1     }, /* GPIO3 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG}, /* GPIO4 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG}, /* GPIO5 */ \
-{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG}, /* GPIO6 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1     }, /* GPIO7 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0     }, /* GPIO8 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0     }, /* GPIO9 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0     }, /* GPIO10 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1     }, /* GPIO11 */ \
-{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG}, /* GPIO12 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1     }, /* GPIO13 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG}, /* GPIO14 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG}, /* GPIO15 */ \
-{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0     }, /* GPIO16 */ \
-{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0     }, /* GPIO17 */ \
-{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0     }, /* GPIO18 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0     }, /* GPIO19 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0     }, /* GPIO20 */ \
-{GPIO0_BASE, GPIO_IN,  GPIO_ALT2, GPIO_OUT_0     }, /* GPIO21 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG}, /* GPIO22 */ \
-{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG}, /* GPIO23 */ \
-{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0     }, /* GPIO24 */ \
-{GPIO0_BASE, GPIO_IN,  GPIO_ALT3, GPIO_OUT_0     }, /* GPIO25 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0     }, /* GPIO26 */ \
-{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0     }, /* GPIO27 */ \
-{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0     }, /* GPIO28 */ \
-{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0     }, /* GPIO29 */ \
-{GPIO0_BASE, GPIO_IN,  GPIO_ALT2, GPIO_OUT_0     }, /* GPIO30 */ \
-{GPIO0_BASE, GPIO_IN,  GPIO_ALT2, GPIO_OUT_0     }, /* GPIO31 */ \
-} \
-}
-
-#define CONFIG_SYS_GPIO_STARTUP_FINISHED	15
-#define CONFIG_SYS_GPIO_STARTUP_FINISHED_N	14
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/iocon.h b/include/configs/iocon.h
deleted file mode 100644
index 99e920b46a..0000000000
--- a/include/configs/iocon.h
+++ /dev/null
@@ -1,294 +0,0 @@
-/*
- * (C) Copyright 2010
- * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_405EP		1	/* this is a PPC405 CPU */
-#define CONFIG_IOCON		1	/*  on a IoCon board */
-
-#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
-
-/*
- * Include common defines/options for all AMCC eval boards
- */
-#define CONFIG_HOSTNAME		iocon
-#include "amcc-common.h"
-
-/* Reclaim some space. */
-#undef CONFIG_SYS_LONGHELP
-
-#define CONFIG_BOARD_EARLY_INIT_R
-#define CONFIG_LAST_STAGE_INIT
-
-#define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll   */
-
-/*
- * Configure PLL
- */
-#define PLLMR0_DEFAULT PLLMR0_266_133_66
-#define PLLMR1_DEFAULT PLLMR1_266_133_66
-
-#define CONFIG_ENV_IS_IN_FLASH	/* use FLASH for environment vars */
-
-/*
- * Default environment variables
- */
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	CONFIG_AMCC_DEF_ENV						\
-	CONFIG_AMCC_DEF_ENV_POWERPC					\
-	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
-	"kernel_addr=fc000000\0"					\
-	"fdt_addr=fc1e0000\0"						\
-	"ramdisk_addr=fc200000\0"					\
-	""
-
-#define CONFIG_PHY_ADDR		4	/* PHY address			*/
-#define CONFIG_HAS_ETH0
-#define CONFIG_PHY_CLK_FREQ    EMAC_STACR_CLK_66MHZ
-
-/*
- * Commands additional to the ones defined in amcc-common.h
- */
-
-/*
- * SDRAM configuration (please see cpu/ppc/sdram.[ch])
- */
-#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0 */
-
-/* SDRAM timings used in datasheet */
-#define CONFIG_SYS_SDRAM_CL             3	/* CAS latency */
-#define CONFIG_SYS_SDRAM_tRP           20	/* PRECHARGE command period */
-#define CONFIG_SYS_SDRAM_tRC           66	/* ACTIVE-to-ACTIVE period */
-#define CONFIG_SYS_SDRAM_tRCD          20	/* ACTIVE-to-READ delay */
-#define CONFIG_SYS_SDRAM_tRFC          66	/* Auto refresh period */
-
-/*
- * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
- * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
- * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
- * The Linux BASE_BAUD define should match this configuration.
- *    baseBaud = cpuClock/(uartDivisor*16)
- * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
- * set Linux BASE_BAUD to 403200.
- */
-#define CONFIG_CONS_INDEX		1	/* Use UART0 */
-#undef  CONFIG_SYS_EXT_SERIAL_CLOCK		/* external serial clock */
-#undef  CONFIG_SYS_405_UART_ERRATA_59		/* 405GP/CR Rev. D silicon */
-#define CONFIG_SYS_BASE_BAUD		691200
-
-/*
- * I2C stuff
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
-#define CONFIG_SYS_I2C_IHS
-
-#define CONFIG_SYS_I2C_SPEED		400000
-#define CONFIG_SYS_SPD_BUS_NUM		4
-
-#define CONFIG_PCA953X			/* NXP PCA9554 */
-#define CONFIG_PCA9698			/* NXP PCA9698 */
-
-#define CONFIG_SYS_I2C_IHS_CH0
-#define CONFIG_SYS_I2C_IHS_SPEED_0		50000
-#define CONFIG_SYS_I2C_IHS_SLAVE_0		0x7F
-#define CONFIG_SYS_I2C_IHS_CH1
-#define CONFIG_SYS_I2C_IHS_SPEED_1		50000
-#define CONFIG_SYS_I2C_IHS_SLAVE_1		0x7F
-#define CONFIG_SYS_I2C_IHS_CH2
-#define CONFIG_SYS_I2C_IHS_SPEED_2		50000
-#define CONFIG_SYS_I2C_IHS_SLAVE_2		0x7F
-#define CONFIG_SYS_I2C_IHS_CH3
-#define CONFIG_SYS_I2C_IHS_SPEED_3		50000
-#define CONFIG_SYS_I2C_IHS_SLAVE_3		0x7F
-
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define CONFIG_SYS_I2C_SOFT
-#define CONFIG_SYS_I2C_SOFT_SPEED		50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE		0x7F
-#define I2C_SOFT_DECLARATIONS2
-#define CONFIG_SYS_I2C_SOFT_SPEED_2		50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE_2		0x7F
-#define I2C_SOFT_DECLARATIONS3
-#define CONFIG_SYS_I2C_SOFT_SPEED_3		50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE_3		0x7F
-#define I2C_SOFT_DECLARATIONS4
-#define CONFIG_SYS_I2C_SOFT_SPEED_4		50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE_4		0x7F
-
-#define CONFIG_SYS_ICS8N3QV01_I2C		{5, 6, 7, 8}
-#define CONFIG_SYS_CH7301_I2C			{5, 6, 7, 8}
-#define CONFIG_SYS_DP501_I2C			{0, 1, 2, 3}
-
-#ifndef __ASSEMBLY__
-void fpga_gpio_set(unsigned int bus, int pin);
-void fpga_gpio_clear(unsigned int bus, int pin);
-int fpga_gpio_get(unsigned int bus, int pin);
-#endif
-
-#define I2C_ACTIVE	{ }
-#define I2C_TRISTATE	{ }
-#define I2C_READ \
-	(fpga_gpio_get(I2C_ADAP_HWNR, 0x0040) ? 1 : 0)
-#define I2C_SDA(bit) \
-	do { \
-		if (bit) \
-			fpga_gpio_set(I2C_ADAP_HWNR, 0x0040); \
-		else \
-			fpga_gpio_clear(I2C_ADAP_HWNR, 0x0040); \
-	} while (0)
-#define I2C_SCL(bit) \
-	do { \
-		if (bit) \
-			fpga_gpio_set(I2C_ADAP_HWNR, 0x0020); \
-		else \
-			fpga_gpio_clear(I2C_ADAP_HWNR, 0x0020); \
-	} while (0)
-#define I2C_DELAY	udelay(25)	/* 1/4 I2C clock duration */
-
-/*
- * FLASH organization
- */
-#define CONFIG_SYS_FLASH_CFI		/* The flash is CFI compatible	*/
-#define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/
-
-#define CONFIG_SYS_FLASH_BASE		0xFC000000
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max num of sectors per chip*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase/ms */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write/ms */
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buff'd writes */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO	/* 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* no warn upon unknown flash */
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE	0x20000	/* size of one complete sector */
-#define CONFIG_ENV_ADDR		((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
-#define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector */
-
-/* Address and size of Redundant Environment Sector	*/
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
-#endif
-
-/*
- * PPC405 GPIO Configuration
- */
-#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO	Alternate1	*/ \
-{ \
-/* GPIO Core 0 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO0	PerBLast */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO1	TS1E */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO2	TS2E */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO3	TS1O */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO4	TS2O */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1      }, /* GPIO5	TS3 */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO6	TS4 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO7	TS5 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO8	TS6 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO9	TrcClk */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10	PerCS1 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11	PerCS2 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12	PerCS3 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13	PerCS4 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14	PerAddr03 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15	PerAddr04 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16	PerAddr05 */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17	IRQ0 */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18	IRQ1 */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19	IRQ2 */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO20	IRQ3 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO21	IRQ4 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO22	IRQ5 */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO23	IRQ6 */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24	UART0_DCD */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25	UART0_DSR */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26	UART0_RI */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27	UART0_DTR */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28	UART1_Rx */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29	UART1_Tx */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO30	RejectPkt0 */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO31	RejectPkt1 */ \
-} \
-}
-
-/*
- * Definitions for initial stack pointer and data area (in data cache)
- */
-/* use on chip memory (OCM) for temperary stack until sdram is tested */
-#define CONFIG_SYS_TEMP_STACK_OCM        1
-
-/* On Chip Memory location */
-#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
-#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE
-
-#define CONFIG_SYS_GBL_DATA_OFFSET \
-	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/*
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (NOR-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB0AP		0xa382a880
-#define CONFIG_SYS_EBC_PB0CR		0xFC0DA000
-
-/* Memory Bank 1 (NVRAM) initializatio */
-#define CONFIG_SYS_EBC_PB1AP		0x92015480
-#define CONFIG_SYS_EBC_PB1CR		0xFB858000
-
-/* Memory Bank 2 (FPGA0) initialization */
-#define CONFIG_SYS_FPGA0_BASE		0x7f100000
-#define CONFIG_SYS_EBC_PB2AP		0x02825080
-#define CONFIG_SYS_EBC_PB2CR		(CONFIG_SYS_FPGA0_BASE | 0x1a000)
-
-#define CONFIG_SYS_FPGA_BASE(k)		CONFIG_SYS_FPGA0_BASE
-#define CONFIG_SYS_FPGA_DONE(k)		0x0010
-
-#define CONFIG_SYS_FPGA_COUNT		1
-
-#define CONFIG_SYS_MCLINK_MAX		3
-
-#define CONFIG_SYS_FPGA_PTR \
-	{ (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
-
-/* Memory Bank 3 (Latches) initialization */
-#define CONFIG_SYS_LATCH_BASE		0x7f200000
-#define CONFIG_SYS_EBC_PB3AP		0x02025080
-#define CONFIG_SYS_EBC_PB3CR		0x7f21a000
-
-#define CONFIG_SYS_LATCH0_RESET		0xffef
-#define CONFIG_SYS_LATCH0_BOOT		0xffff
-#define CONFIG_SYS_LATCH1_RESET		0xffff
-#define CONFIG_SYS_LATCH1_BOOT		0xffff
-
-/*
- * OSD Setup
- */
-#define CONFIG_SYS_MPC92469AC
-#define CONFIG_SYS_OSD_SCREENS		1
-#define CONFIG_SYS_DP501_DIFFERENTIAL
-#define CONFIG_SYS_DP501_VCAPCTRL0	0x01 /* DDR mode 0, DE for H/VSYNC */
-
-#define CONFIG_BITBANGMII		/* bit-bang MII PHY management */
-#define CONFIG_BITBANGMII_MULTI
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/katmai.h b/include/configs/katmai.h
deleted file mode 100644
index 3f39a26d3b..0000000000
--- a/include/configs/katmai.h
+++ /dev/null
@@ -1,287 +0,0 @@
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/************************************************************************
- * katmai.h - configuration for AMCC Katmai (440SPe)
- ***********************************************************************/
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- *----------------------------------------------------------------------*/
-#define CONFIG_KATMAI			1	/* Board is Katmai	*/
-#define CONFIG_440			1	/* ... PPC440 family	*/
-#define CONFIG_440SPE			1	/* Specifc SPe support	*/
-#define CONFIG_440SPE_REVA		1	/* Support old Rev A.	*/
-#define CONFIG_SYS_CLK_FREQ	33333333	/* external freq to pll	*/
-#define CONFIG_SYS_4xx_RESET_TYPE	0x2	/* use chip reset on this board	*/
-
-#define	CONFIG_SYS_TEXT_BASE	0xFFFA0000
-
-/*
- * Enable this board for more than 2GB of SDRAM
- */
-#define	CONFIG_VERY_BIG_RAM
-
-/*
- * Include common defines/options for all AMCC eval boards
- */
-#define CONFIG_HOSTNAME		katmai
-#include "amcc-common.h"
-
-#undef  CONFIG_SHOW_BOOT_PROGRESS
-
-/*-----------------------------------------------------------------------
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_FLASH_BASE		0xff000000	/* start of FLASH	*/
-#define CONFIG_SYS_ISRAM_BASE		0x90000000	/* internal SRAM	*/
-
-#define CONFIG_SYS_PCI_MEMBASE		0x80000000	/* mapped PCI memory	*/
-#define CONFIG_SYS_PCI_BASE		0xd0000000	/* internal PCI regs	*/
-#define CONFIG_SYS_PCI_TARGBASE	CONFIG_SYS_PCI_MEMBASE
-
-#define CONFIG_SYS_PCIE_MEMBASE	0xb0000000	/* mapped PCIe memory	*/
-#define CONFIG_SYS_PCIE_MEMSIZE	0x08000000	/* smallest incr for PCIe port */
-#define CONFIG_SYS_PCIE_BASE		0xe0000000	/* PCIe UTL regs */
-
-#define CONFIG_SYS_PCIE0_CFGBASE	0xc0000000
-#define CONFIG_SYS_PCIE1_CFGBASE	0xc1000000
-#define CONFIG_SYS_PCIE2_CFGBASE	0xc2000000
-#define CONFIG_SYS_PCIE0_XCFGBASE	0xc3000000
-#define CONFIG_SYS_PCIE1_XCFGBASE	0xc3001000
-#define CONFIG_SYS_PCIE2_XCFGBASE	0xc3002000
-
-/* base address of inbound PCIe window */
-#define CONFIG_SYS_PCIE_INBOUND_BASE	0x0000000000000000ULL
-
-/* System RAM mapped to PCI space */
-#define CONFIG_PCI_SYS_MEM_BUS	CONFIG_SYS_SDRAM_BASE
-#define CONFIG_PCI_SYS_MEM_PHYS	CONFIG_SYS_SDRAM_BASE
-#define CONFIG_PCI_SYS_MEM_SIZE	(1024 * 1024 * 1024)
-
-#define CONFIG_SYS_ACE_BASE		0xfe000000	/* Xilinx ACE controller - Compact Flash */
-
-/*-----------------------------------------------------------------------
- * Initial RAM & stack pointer (placed in internal SRAM)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_TEMP_STACK_OCM	1
-#define CONFIG_SYS_OCM_DATA_ADDR	CONFIG_SYS_ISRAM_BASE
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_ISRAM_BASE	/* Initial RAM address	*/
-#define CONFIG_SYS_INIT_RAM_SIZE	0x2000		/* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
-
-/*-----------------------------------------------------------------------
- * Serial Port
- *----------------------------------------------------------------------*/
-#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK
-
-/*-----------------------------------------------------------------------
- * DDR SDRAM
- *----------------------------------------------------------------------*/
-#define CONFIG_SPD_EEPROM	1	/* Use SPD EEPROM for setup	*/
-#define SPD_EEPROM_ADDRESS	{0x51, 0x52}	/* SPD i2c spd addresses*/
-#define CONFIG_DDR_ECC		1	/* with ECC support		*/
-#define CONFIG_DDR_RQDC_FIXED	0x80000038 /* optimal value found by GDA*/
-#undef  CONFIG_STRESS
-
-/*-----------------------------------------------------------------------
- * I2C
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		100000
-
-#define CONFIG_SYS_SPD_BUS_NUM		0	/* The I2C bus for SPD		*/
-
-#define IIC0_BOOTPROM_ADDR	0x50
-#define IIC0_ALT_BOOTPROM_ADDR	0x54
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR	(0x50)
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-/* I2C bootstrap EEPROM */
-#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR	0x50
-#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET	0
-#define CONFIG_4xx_CONFIG_BLOCKSIZE		8
-
-/* I2C RTC */
-#define CONFIG_RTC_M41T11	1
-#define CONFIG_SYS_RTC_BUS_NUM		1	/* The I2C bus for RTC		*/
-#define CONFIG_SYS_I2C_RTC_ADDR	0x68
-#define CONFIG_SYS_M41T11_BASE_YEAR	1900	/* play along with linux	*/
-
-/*-----------------------------------------------------------------------
- * Environment
- *----------------------------------------------------------------------*/
-#define	CONFIG_ENV_IS_IN_FLASH	1	/* Environment uses flash	*/
-
-/*
- * Default environment variables
- */
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	CONFIG_AMCC_DEF_ENV						\
-	CONFIG_AMCC_DEF_ENV_POWERPC					\
-	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
-	"kernel_addr=ff000000\0"					\
-	"fdt_addr=ff1e0000\0"						\
-	"ramdisk_addr=ff200000\0"					\
-	"pciconfighost=1\0"						\
-	"pcie_mode=RP:RP:RP\0"						\
-	""
-
-/*
- * Commands additional to the ones defined in amcc-common.h
- */
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_SDRAM
-
-#define	CONFIG_IBM_EMAC4_V4	1	/* 440SPe has this EMAC version	*/
-#define CONFIG_PHY_ADDR		1	/* PHY address, See schematics	*/
-#define CONFIG_HAS_ETH0
-#define CONFIG_PHY_RESET        1	/* reset phy upon startup	*/
-#define CONFIG_PHY_RESET_DELAY	1000
-#define CONFIG_CIS8201_PHY	1	/* Enable 'special' RGMII mode for Cicada phy */
-#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
-
-/*-----------------------------------------------------------------------
- * FLASH related
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
-
-#define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE}
-#define CONFIG_SYS_MAX_FLASH_BANKS     1		    /* number of banks	    */
-#define CONFIG_SYS_MAX_FLASH_SECT	1024		    /* sectors per device   */
-
-#undef	CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define CONFIG_ENV_SECT_SIZE	0x20000 /* size of one complete sector	*/
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
-#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
-
-/* Address and size of Redundant Environment Sector	*/
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-/* General PCI */
-#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
-#define CONFIG_PCI_SCAN_SHOW	1	/* show pci devices on startup	*/
-#define CONFIG_PCI_CONFIG_HOST_BRIDGE
-
-/* Board-specific PCI */
-#define CONFIG_SYS_PCI_TARGET_INIT		/* let board init pci target    */
-#undef	CONFIG_SYS_PCI_MASTER_INIT
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014	/* IBM				*/
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever			*/
-/* #define CONFIG_SYS_PCI_SUBSYS_ID	CONFIG_SYS_PCI_SUBSYS_DEVICEID */
-
-/*
- *  NETWORK Support (PCI):
- */
-/* Support for Intel 82557/82559/82559ER chips. */
-#define CONFIG_EEPRO100
-
-/*-----------------------------------------------------------------------
- * Xilinx System ACE support
- *----------------------------------------------------------------------*/
-#define CONFIG_SYSTEMACE	1	/* Enable SystemACE support	*/
-#define CONFIG_SYS_SYSTEMACE_WIDTH	16	/* Data bus width is 16		*/
-#define CONFIG_SYS_SYSTEMACE_BASE	CONFIG_SYS_ACE_BASE
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- *----------------------------------------------------------------------*/
-
-/* Memory Bank 0 (Flash) initialization					*/
-#define CONFIG_SYS_EBC_PB0AP		(EBC_BXAP_BME_DISABLED      |		\
-				 EBC_BXAP_TWT_ENCODE(7)     |		\
-				 EBC_BXAP_BCE_DISABLE       |		\
-				 EBC_BXAP_BCT_2TRANS        |		\
-				 EBC_BXAP_CSN_ENCODE(0)     |		\
-				 EBC_BXAP_OEN_ENCODE(0)     |		\
-				 EBC_BXAP_WBN_ENCODE(0)     |		\
-				 EBC_BXAP_WBF_ENCODE(0)     |		\
-				 EBC_BXAP_TH_ENCODE(0)      |		\
-				 EBC_BXAP_RE_DISABLED       |		\
-				 EBC_BXAP_SOR_DELAYED       |		\
-				 EBC_BXAP_BEM_WRITEONLY     |		\
-				 EBC_BXAP_PEN_DISABLED)
-#define CONFIG_SYS_EBC_PB0CR		(EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) |	\
-				 EBC_BXCR_BS_16MB                    |	\
-				 EBC_BXCR_BU_RW                      |	\
-				 EBC_BXCR_BW_16BIT)
-
-/* Memory Bank 1 (Xilinx System ACE controller) initialization		*/
-#define CONFIG_SYS_EBC_PB1AP		(EBC_BXAP_BME_DISABLED      |		\
-				 EBC_BXAP_TWT_ENCODE(4)     |		\
-				 EBC_BXAP_BCE_DISABLE       |		\
-				 EBC_BXAP_BCT_2TRANS        |		\
-				 EBC_BXAP_CSN_ENCODE(0)     |		\
-				 EBC_BXAP_OEN_ENCODE(0)     |		\
-				 EBC_BXAP_WBN_ENCODE(0)     |		\
-				 EBC_BXAP_WBF_ENCODE(0)     |		\
-				 EBC_BXAP_TH_ENCODE(0)      |		\
-				 EBC_BXAP_RE_DISABLED       |		\
-				 EBC_BXAP_SOR_NONDELAYED    |		\
-				 EBC_BXAP_BEM_WRITEONLY     |		\
-				 EBC_BXAP_PEN_DISABLED)
-#define CONFIG_SYS_EBC_PB1CR		(EBC_BXCR_BAS_ENCODE(CONFIG_SYS_ACE_BASE)  |	\
-				 EBC_BXCR_BS_1MB                    |	\
-				 EBC_BXCR_BU_RW                     |	\
-				 EBC_BXCR_BW_16BIT)
-
-/*-------------------------------------------------------------------------
- * Initialize EBC CONFIG -
- * Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
- * default value : 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
- *-------------------------------------------------------------------------*/
-#define CONFIG_SYS_EBC_CFG		(EBC_CFG_LE_UNLOCK    |	\
-				 EBC_CFG_PTD_ENABLE   |	\
-				 EBC_CFG_RTC_16PERCLK | \
-				 EBC_CFG_ATC_PREVIOUS | \
-				 EBC_CFG_DTC_PREVIOUS | \
-				 EBC_CFG_CTC_PREVIOUS | \
-				 EBC_CFG_OEO_PREVIOUS | \
-				 EBC_CFG_EMC_DEFAULT  |	\
-				 EBC_CFG_PME_DISABLE  |	\
-				 EBC_CFG_PR_16)
-
-/*-----------------------------------------------------------------------
- * GPIO Setup
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_GPIO_PCIE_PRESENT0	17
-#define CONFIG_SYS_GPIO_PCIE_PRESENT1	21
-#define CONFIG_SYS_GPIO_PCIE_PRESENT2	23
-#define CONFIG_SYS_GPIO_RS232_FORCEOFF	30
-
-#define CONFIG_SYS_PFC0		(GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT0) | \
-				 GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT1) | \
-				 GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT2) | \
-				 GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF))
-#define CONFIG_SYS_GPIO_OR		GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)
-#define CONFIG_SYS_GPIO_TCR		GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)
-#define CONFIG_SYS_GPIO_ODR		0
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h
deleted file mode 100644
index a91a6a9ee5..0000000000
--- a/include/configs/kilauea.h
+++ /dev/null
@@ -1,521 +0,0 @@
-/*
- * Copyright (c) 2008 Nuovation System Designs, LLC
- *   Grant Erickson <gerickson@nuovations.com>
- *
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/************************************************************************
- * kilauea.h - configuration for AMCC Kilauea (405EX)
- ***********************************************************************/
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- *----------------------------------------------------------------------*/
-#define CONFIG_KILAUEA		1		/* Board is Kilauea	*/
-#define CONFIG_405EX		1		/* Specifc 405EX support*/
-#define CONFIG_SYS_CLK_FREQ	33333333	/* ext frequency to pll	*/
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE	0xFFFA0000
-#endif
-
-/*
- * CHIP_21 errata - you must set this to match your exact CPU, else your
- * board will not boot.  DO NOT enable this unless you have JTAG available
- * for recovery, in the event you get it wrong.
- *
- * Kilauea uses the 405EX, while Haleakala uses the 405EXr.  Either board
- * may be equipped for security or not.  You must look at the CPU part
- * number to be sure what you have.
- */
-/* #define CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY */
-/* #define CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY */
-/* #define CONFIG_SYS_4xx_CHIP_21_405EXr_NO_SECURITY */
-/* #define CONFIG_SYS_4xx_CHIP_21_405EXr_SECURITY */
-
-/*
- * Include common defines/options for all AMCC eval boards
- */
-#define CONFIG_HOSTNAME		kilauea
-#include "amcc-common.h"
-
-#define CONFIG_MISC_INIT_R	1		/* Call misc_init_r	*/
-#define CONFIG_BOARD_TYPES
-#define CONFIG_BOARD_EMAC_COUNT
-
-/*-----------------------------------------------------------------------
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_FLASH_BASE		0xFC000000
-#define CONFIG_SYS_NAND_ADDR		0xF8000000
-#define CONFIG_SYS_FPGA_BASE		0xF0000000
-
-/*-----------------------------------------------------------------------
- * Initial RAM & Stack Pointer Configuration Options
- *
- *   There are traditionally three options for the primordial
- *   (i.e. initial) stack usage on the 405-series:
- *
- *      1) On-chip Memory (OCM) (i.e. SRAM)
- *      2) Data cache
- *      3) SDRAM
- *
- *   For the 405EX(r), there is no OCM, so we are left with (2) or (3)
- *   the latter of which is less than desireable since it requires
- *   setting up the SDRAM and ECC in assembly code.
- *
- *   To use (2), define 'CONFIG_SYS_INIT_DCACHE_CS' to be an unused chip
- *   select on the External Bus Controller (EBC) and then select a
- *   value for 'CONFIG_SYS_INIT_RAM_ADDR' outside of the range of valid,
- *   physical SDRAM. Otherwise, undefine 'CONFIG_SYS_INIT_DCACHE_CS' and
- *   select a value for 'CONFIG_SYS_INIT_RAM_ADDR' within the range of valid,
- *   physical SDRAM to use (3).
- *-----------------------------------------------------------------------*/
-
-#define CONFIG_SYS_INIT_DCACHE_CS	4
-
-#if defined(CONFIG_SYS_INIT_DCACHE_CS)
-#define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_SDRAM_BASE + ( 1 << 30))	/*  1 GiB */
-#else
-#define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_SDRAM_BASE + (32 << 20))	/* 32 MiB */
-#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
-
-#define CONFIG_SYS_INIT_RAM_SIZE        (4 << 10)			/*  4 KiB */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-/*
- * If the data cache is being used for the primordial stack and global
- * data area, the POST word must be placed somewhere else. The General
- * Purpose Timer (GPT) is unused by u-boot and the kernel and preserves
- * its compare and mask register contents across reset, so it is used
- * for the POST word.
- */
-
-#if defined(CONFIG_SYS_INIT_DCACHE_CS)
-# define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-# define CONFIG_SYS_POST_WORD_ADDR	(CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
-#else
-# define CONFIG_SYS_INIT_EXTRA_SIZE	16
-# define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_EXTRA_SIZE)
-# define CONFIG_SYS_OCM_DATA_ADDR	CONFIG_SYS_INIT_RAM_ADDR
-#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
-
-/*-----------------------------------------------------------------------
- * Serial Port
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_EXT_SERIAL_CLOCK	11059200	/* ext. 11.059MHz clk	*/
-#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
-
-/*-----------------------------------------------------------------------
- * Environment
- *----------------------------------------------------------------------*/
-#define CONFIG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
-
-/*-----------------------------------------------------------------------
- * FLASH related
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_FLASH_CFI			/* The flash is CFI compatible	*/
-#define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/
-
-#define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE}
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
-#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE	0x20000	/* size of one complete sector	*/
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
-#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
-
-/* Address and size of Redundant Environment Sector	*/
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
-#endif /* CONFIG_ENV_IS_IN_FLASH */
-
-/*-----------------------------------------------------------------------
- * NAND FLASH
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MAX_NAND_DEVICE	1
-#define CONFIG_SYS_NAND_BASE		(CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
-#define CONFIG_SYS_NAND_SELECT_DEVICE  1	/* nand driver supports mutipl. chips	*/
-
-/*-----------------------------------------------------------------------
- * DDR SDRAM
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MBYTES_SDRAM        (256)		/* 256MB			*/
-
-/*
- * CONFIG_PPC4xx_DDR_AUTOCALIBRATION
- *
- * Note: DDR Autocalibration Method_A scans the full range of possible PPC4xx
- *       SDRAM Controller DDR autocalibration values and takes a lot longer
- *       to run than Method_B.
- * (See the Method_A and Method_B algorithm discription in the file:
- *	arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c)
- * Define CONFIG_PPC4xx_DDR_METHOD_A to use DDR autocalibration Method_A
- *
- * DDR Autocalibration Method_B is the default.
- */
-#define	CONFIG_PPC4xx_DDR_AUTOCALIBRATION	/* IBM DDR autocalibration */
-#define	DEBUG_PPC4xx_DDR_AUTOCALIBRATION	/* dynamic DDR autocal debug */
-#undef	CONFIG_PPC4xx_DDR_METHOD_A
-
-#define	CONFIG_SYS_SDRAM0_MB0CF_BASE	((  0 << 20) + CONFIG_SYS_SDRAM_BASE)
-
-/* DDR1/2 SDRAM Device Control Register Data Values */
-#define CONFIG_SYS_SDRAM0_MB0CF	((CONFIG_SYS_SDRAM0_MB0CF_BASE >> 3)	| \
-				 SDRAM_RXBAS_SDSZ_256MB		| \
-				 SDRAM_RXBAS_SDAM_MODE7		| \
-				 SDRAM_RXBAS_SDBE_ENABLE)
-#define CONFIG_SYS_SDRAM0_MB1CF	SDRAM_RXBAS_SDBE_DISABLE
-#define CONFIG_SYS_SDRAM0_MB2CF	SDRAM_RXBAS_SDBE_DISABLE
-#define CONFIG_SYS_SDRAM0_MB3CF	SDRAM_RXBAS_SDBE_DISABLE
-#define CONFIG_SYS_SDRAM0_MCOPT1	(SDRAM_MCOPT1_PMU_OPEN		| \
-				 SDRAM_MCOPT1_8_BANKS		| \
-				 SDRAM_MCOPT1_DDR2_TYPE		| \
-				 SDRAM_MCOPT1_QDEP		| \
-				 SDRAM_MCOPT1_DCOO_DISABLED)
-#define CONFIG_SYS_SDRAM0_MCOPT2	0x00000000
-#define CONFIG_SYS_SDRAM0_MODT0	(SDRAM_MODT_EB0W_ENABLE | \
-				 SDRAM_MODT_EB0R_ENABLE)
-#define CONFIG_SYS_SDRAM0_MODT1	0x00000000
-#define CONFIG_SYS_SDRAM0_CODT		(SDRAM_CODT_RK0R_ON		| \
-				 SDRAM_CODT_CKLZ_36OHM		| \
-				 SDRAM_CODT_DQS_1_8_V_DDR2	| \
-				 SDRAM_CODT_IO_NMODE)
-#define CONFIG_SYS_SDRAM0_RTR		SDRAM_RTR_RINT_ENCODE(1560)
-#define CONFIG_SYS_SDRAM0_INITPLR0	(SDRAM_INITPLR_ENABLE			| \
-		SDRAM_INITPLR_IMWT_ENCODE(80)				| \
-		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_NOP))
-#define CONFIG_SYS_SDRAM0_INITPLR1	(SDRAM_INITPLR_ENABLE			| \
-		SDRAM_INITPLR_IMWT_ENCODE(3)				| \
-		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE)		| \
-		SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR)			| \
-		SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
-#define CONFIG_SYS_SDRAM0_INITPLR2	(SDRAM_INITPLR_ENABLE			| \
-		SDRAM_INITPLR_IMWT_ENCODE(2)				| \
-		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)		| \
-		SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR2)			| \
-		SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR2_TEMP_COMMERCIAL))
-#define CONFIG_SYS_SDRAM0_INITPLR3	(SDRAM_INITPLR_ENABLE			| \
-		SDRAM_INITPLR_IMWT_ENCODE(2)				| \
-		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)		| \
-		SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR3)			| \
-		SDRAM_INITPLR_IMA_ENCODE(0))
-#define CONFIG_SYS_SDRAM0_INITPLR4	(SDRAM_INITPLR_ENABLE			| \
-		SDRAM_INITPLR_IMWT_ENCODE(2)				| \
-		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)		| \
-		SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR)			| \
-		SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_DQS_DISABLE | \
-					 JEDEC_MA_EMR_RTT_75OHM))
-#define CONFIG_SYS_SDRAM0_INITPLR5	(SDRAM_INITPLR_ENABLE			| \
-		SDRAM_INITPLR_IMWT_ENCODE(2)				| \
-		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)		| \
-		SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR)			| \
-		SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
-					 JEDEC_MA_MR_CL_DDR2_4_0_CLK | \
-					 JEDEC_MA_MR_BLEN_4 | \
-					 JEDEC_MA_MR_DLL_RESET))
-#define CONFIG_SYS_SDRAM0_INITPLR6	(SDRAM_INITPLR_ENABLE			| \
-		SDRAM_INITPLR_IMWT_ENCODE(3)				| \
-		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE)		| \
-		SDRAM_INITPLR_IBA_ENCODE(0x0)				| \
-		SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
-#define CONFIG_SYS_SDRAM0_INITPLR7	(SDRAM_INITPLR_ENABLE			| \
-		SDRAM_INITPLR_IMWT_ENCODE(26)				| \
-		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
-#define CONFIG_SYS_SDRAM0_INITPLR8	(SDRAM_INITPLR_ENABLE			| \
-		SDRAM_INITPLR_IMWT_ENCODE(26)				| \
-		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
-#define CONFIG_SYS_SDRAM0_INITPLR9	(SDRAM_INITPLR_ENABLE			| \
-		SDRAM_INITPLR_IMWT_ENCODE(26)				| \
-		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
-#define CONFIG_SYS_SDRAM0_INITPLR10	(SDRAM_INITPLR_ENABLE			| \
-		SDRAM_INITPLR_IMWT_ENCODE(26)				| \
-		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
-#define CONFIG_SYS_SDRAM0_INITPLR11	(SDRAM_INITPLR_ENABLE			| \
-		SDRAM_INITPLR_IMWT_ENCODE(2)				| \
-		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)		| \
-		SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR)			| \
-		SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
-					 JEDEC_MA_MR_CL_DDR2_4_0_CLK | \
-					 JEDEC_MA_MR_BLEN_4))
-#define CONFIG_SYS_SDRAM0_INITPLR12	(SDRAM_INITPLR_ENABLE			| \
-		SDRAM_INITPLR_IMWT_ENCODE(2)				| \
-		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)		| \
-		SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR)			| \
-		SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_ENTER	| \
-					 JEDEC_MA_EMR_RDQS_DISABLE | \
-					 JEDEC_MA_EMR_DQS_DISABLE | \
-					 JEDEC_MA_EMR_RTT_DISABLED | \
-					 JEDEC_MA_EMR_ODS_NORMAL))
-#define CONFIG_SYS_SDRAM0_INITPLR13	(SDRAM_INITPLR_ENABLE			| \
-		SDRAM_INITPLR_IMWT_ENCODE(2)				| \
-		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)		| \
-		SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR)			| \
-		SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_EXIT | \
-					 JEDEC_MA_EMR_RDQS_DISABLE | \
-					 JEDEC_MA_EMR_DQS_DISABLE | \
-					 JEDEC_MA_EMR_RTT_DISABLED | \
-					 JEDEC_MA_EMR_ODS_NORMAL))
-#define CONFIG_SYS_SDRAM0_INITPLR14	(SDRAM_INITPLR_DISABLE)
-#define CONFIG_SYS_SDRAM0_INITPLR15	(SDRAM_INITPLR_DISABLE)
-#define CONFIG_SYS_SDRAM0_RQDC		(SDRAM_RQDC_RQDE_ENABLE | \
-				 SDRAM_RQDC_RQFD_ENCODE(56))
-#define CONFIG_SYS_SDRAM0_RFDC		SDRAM_RFDC_RFFD_ENCODE(521)
-#define CONFIG_SYS_SDRAM0_RDCC		(SDRAM_RDCC_RDSS_T2)
-#define CONFIG_SYS_SDRAM0_DLCR		(SDRAM_DLCR_DCLM_AUTO		| \
-				 SDRAM_DLCR_DLCS_CONT_DONE	| \
-				 SDRAM_DLCR_DLCV_ENCODE(165))
-#define CONFIG_SYS_SDRAM0_CLKTR	(SDRAM_CLKTR_CLKP_180_DEG_ADV)
-#define CONFIG_SYS_SDRAM0_WRDTR	0x00000000
-#define CONFIG_SYS_SDRAM0_SDTR1	(SDRAM_SDTR1_LDOF_2_CLK	| \
-				 SDRAM_SDTR1_RTW_2_CLK	| \
-				 SDRAM_SDTR1_RTRO_1_CLK)
-#define CONFIG_SYS_SDRAM0_SDTR2	(SDRAM_SDTR2_RCD_3_CLK		| \
-				 SDRAM_SDTR2_WTR_2_CLK		| \
-				 SDRAM_SDTR2_XSNR_32_CLK	| \
-				 SDRAM_SDTR2_WPC_4_CLK		| \
-				 SDRAM_SDTR2_RPC_2_CLK		| \
-				 SDRAM_SDTR2_RP_3_CLK		| \
-				 SDRAM_SDTR2_RRD_2_CLK)
-#define CONFIG_SYS_SDRAM0_SDTR3	(SDRAM_SDTR3_RAS_ENCODE(8)	| \
-				 SDRAM_SDTR3_RC_ENCODE(11)	| \
-				 SDRAM_SDTR3_XCS		| \
-				 SDRAM_SDTR3_RFC_ENCODE(26))
-#define CONFIG_SYS_SDRAM0_MMODE	(SDRAM_MMODE_WR_DDR2_3_CYC | \
-				 SDRAM_MMODE_DCL_DDR2_4_0_CLK | \
-				 SDRAM_MMODE_BLEN_4)
-#define CONFIG_SYS_SDRAM0_MEMODE	(SDRAM_MEMODE_DQS_DISABLE | \
-				 SDRAM_MEMODE_RTT_75OHM)
-
-/*-----------------------------------------------------------------------
- * I2C
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR	0x52	/* I2C boot EEPROM (24C02BN)	*/
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address		*/
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
-
-/* I2C bootstrap EEPROM */
-#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR	0x52
-#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET	0
-#define CONFIG_4xx_CONFIG_BLOCKSIZE		16
-
-/* RTC configuration */
-#define CONFIG_RTC_DS1338	1
-#define CONFIG_SYS_I2C_RTC_ADDR	0x68
-
-/*-----------------------------------------------------------------------
- * Ethernet
- *----------------------------------------------------------------------*/
-#define CONFIG_M88E1111_PHY	1
-#define CONFIG_IBM_EMAC4_V4	1
-#define CONFIG_EMAC_PHY_MODE	EMAC_PHY_MODE_RGMII_RGMII
-#define CONFIG_PHY_ADDR		1	/* PHY address, See schematics	*/
-
-#define CONFIG_PHY_RESET	1	/* reset phy upon startup	*/
-#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
-
-#define CONFIG_HAS_ETH0		1
-
-#define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"   */
-#define CONFIG_PHY1_ADDR	2
-
-/* Debug messages for the DDR autocalibration */
-#define CONFIG_AUTOCALIB		"silent\0"  /* default is non-verbose */
-
-/*
- * Default environment variables
- */
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	CONFIG_AMCC_DEF_ENV						\
-	CONFIG_AMCC_DEF_ENV_POWERPC					\
-	CONFIG_AMCC_DEF_ENV_PPC_OLD					\
-	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
-	"logversion=2\0"						\
-	"kernel_addr=fc000000\0"					\
-	"fdt_addr=fc1e0000\0"						\
-	"ramdisk_addr=fc200000\0"					\
-	"pciconfighost=1\0"						\
-	"pcie_mode=RP:RP\0"						\
-	""
-
-/*
- * Commands additional to the ones defined in amcc-common.h
- */
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_PCI
-
-#define CONFIG_SYS_POST_MEMORY_ON	CONFIG_SYS_POST_MEMORY
-
-/* POST support */
-#define CONFIG_POST		(CONFIG_SYS_POST_CACHE		| \
-				 CONFIG_SYS_POST_CPU		| \
-				 CONFIG_SYS_POST_ETHER		| \
-				 CONFIG_SYS_POST_I2C		| \
-				 CONFIG_SYS_POST_MEMORY_ON	| \
-				 CONFIG_SYS_POST_UART)
-
-/* Define here the base-addresses of the UARTs to test in POST */
-#define CONFIG_SYS_POST_UART_TABLE	{ CONFIG_SYS_NS16550_COM1, \
-			CONFIG_SYS_NS16550_COM2 }
-
-#define CONFIG_LOGBUFFER
-#define CONFIG_SYS_POST_CACHE_ADDR	0x00800000 /* free virtual address	*/
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *----------------------------------------------------------------------*/
-#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
-#define CONFIG_PCI_SCAN_SHOW	1	/* show pci devices on startup	*/
-#define CONFIG_PCI_CONFIG_HOST_BRIDGE
-
-/*-----------------------------------------------------------------------
- * PCIe stuff
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_PCIE_MEMBASE	0x90000000	/* mapped PCIe memory	*/
-#define CONFIG_SYS_PCIE_MEMSIZE	0x08000000      /* 128 Meg, smallest incr per port */
-
-#define	CONFIG_SYS_PCIE0_CFGBASE	0xa0000000      /* remote access */
-#define	CONFIG_SYS_PCIE0_XCFGBASE	0xb0000000      /* local access */
-#define	CONFIG_SYS_PCIE0_CFGMASK	0xe0000001      /* 512 Meg */
-
-#define	CONFIG_SYS_PCIE1_CFGBASE	0xc0000000      /* remote access */
-#define	CONFIG_SYS_PCIE1_XCFGBASE	0xd0000000      /* local access */
-#define	CONFIG_SYS_PCIE1_CFGMASK	0xe0000001      /* 512 Meg */
-
-#define	CONFIG_SYS_PCIE0_UTLBASE	0xef502000
-#define	CONFIG_SYS_PCIE1_UTLBASE	0xef503000
-
-/* base address of inbound PCIe window */
-#define CONFIG_SYS_PCIE_INBOUND_BASE	0x0000000000000000ULL
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_NAND_CS		1		/* NAND chip connected to CSx	*/
-
-/* Memory Bank 0 (NOR-FLASH) initialization					*/
-#define CONFIG_SYS_EBC_PB0AP		0x05806500
-#define CONFIG_SYS_EBC_PB0CR           0xFC0DA000  /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit*/
-
-/* Memory Bank 1 (NAND-FLASH) initialization					*/
-#define CONFIG_SYS_EBC_PB1AP		0x018003c0
-#define CONFIG_SYS_EBC_PB1CR		(CONFIG_SYS_NAND_ADDR | 0x1e000)
-
-/* Memory Bank 2 (FPGA) initialization					*/
-#define CONFIG_SYS_EBC_PB2AP		(EBC_BXAP_BME_ENABLED |		\
-					 EBC_BXAP_FWT_ENCODE(6) |	\
-					 EBC_BXAP_BWT_ENCODE(1) |	\
-					 EBC_BXAP_BCE_DISABLE |		\
-					 EBC_BXAP_BCT_2TRANS |		\
-					 EBC_BXAP_CSN_ENCODE(0) |	\
-					 EBC_BXAP_OEN_ENCODE(0) |	\
-					 EBC_BXAP_WBN_ENCODE(3) |	\
-					 EBC_BXAP_WBF_ENCODE(1) |	\
-					 EBC_BXAP_TH_ENCODE(4) |	\
-					 EBC_BXAP_RE_DISABLED |		\
-					 EBC_BXAP_SOR_DELAYED |		\
-					 EBC_BXAP_BEM_WRITEONLY |	\
-					 EBC_BXAP_PEN_DISABLED)
-#define CONFIG_SYS_EBC_PB2CR	(CONFIG_SYS_FPGA_BASE | 0x18000)
-
-#define CONFIG_SYS_EBC_CFG		0x7FC00000 /*  EBC0_CFG */
-
-/*-----------------------------------------------------------------------
- * GPIO Setup
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_4xx_GPIO_TABLE { /*	  Out		  GPIO	Alternate1	Alternate2	Alternate3 */ \
-{											\
-/* GPIO Core 0 */									\
-{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO0	EBC_DATA_PAR(0)			*/	\
-{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO1	EBC_DATA_PAR(1)			*/	\
-{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO2	EBC_DATA_PAR(2)			*/	\
-{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO3	EBC_DATA_PAR(3)			*/	\
-{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO4	EBC_DATA(20)	USB2_DATA(4)	*/	\
-{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO5	EBC_DATA(21)	USB2_DATA(5)	*/	\
-{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO6	EBC_DATA(22)	USB2_DATA(6)	*/	\
-{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO7	EBC_DATA(23)	USB2_DATA(7)	*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8	CS(1)/NFCE(1)	IRQ(7)		*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9	CS(2)/NFCE(2)	IRQ(8)		*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 CS(3)/NFCE(3)	IRQ(9)		*/	\
-{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 IRQ(6)				*/	\
-{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO12 EBC_DATA(16)	USB2_DATA(0)	*/	\
-{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO13 EBC_DATA(17)	USB2_DATA(1)	*/	\
-{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO14 EBC_DATA(18)	USB2_DATA(2)	*/	\
-{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO15 EBC_DATA(19)	USB2_DATA(3)	*/	\
-{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 UART0_DCD	UART1_CTS	*/	\
-{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 UART0_DSR	UART1_RTS	*/	\
-{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 UART0_CTS			*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 UART0_RTS			*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO20 UART0_DTR	UART1_TX	*/	\
-{GPIO0_BASE, GPIO_IN,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO21 UART0_RI	UART1_RX	*/	\
-{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO22 EBC_HOLD_REQ	DMA_ACK2	*/	\
-{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO23 EBC_HOLD_ACK	DMA_REQ2	*/	\
-{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO24 EBC_EXT_REQ	DMA_EOT2	IRQ(4) */ \
-{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO25 EBC_EXT_ACK	DMA_ACK3	IRQ(3) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 EBC_ADDR(5)	DMA_EOT0	TS(3) */ \
-{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO27 EBC_BUS_REQ	DMA_EOT3	IRQ(5) */ \
-{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO28				*/	\
-{GPIO0_BASE, GPIO_IN,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO29 DMA_EOT1	IRQ(2)		*/	\
-{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO30 DMA_REQ1	IRQ(1)		*/	\
-{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO31 DMA_ACK1	IRQ(0)		*/	\
-}												\
-}
-
-/*-----------------------------------------------------------------------
- * Some Kilauea stuff..., mainly fpga registers
- */
-#define CONFIG_SYS_FPGA_REG_BASE		CONFIG_SYS_FPGA_BASE
-#define CONFIG_SYS_FPGA_FIFO_BASE		(CONFIG_SYS_FPGA_BASE | (1 << 10))
-
-/* interrupt */
-#define CONFIG_SYS_FPGA_SLIC0_R_DPRAM_INT	0x80000000
-#define CONFIG_SYS_FPGA_SLIC0_W_DPRAM_INT	0x40000000
-#define CONFIG_SYS_FPGA_SLIC1_R_DPRAM_INT	0x20000000
-#define CONFIG_SYS_FPGA_SLIC1_W_DPRAM_INT	0x10000000
-#define CONFIG_SYS_FPGA_PHY0_INT		0x08000000
-#define CONFIG_SYS_FPGA_PHY1_INT		0x04000000
-#define CONFIG_SYS_FPGA_SLIC0_INT		0x02000000
-#define CONFIG_SYS_FPGA_SLIC1_INT		0x01000000
-
-/* DPRAM setting */
-/* 00: 32B; 01: 64B; 10: 128B; 11: 256B  */
-#define CONFIG_SYS_FPGA_DPRAM_R_INT_LINE	0x00400000	/* 64 B */
-#define CONFIG_SYS_FPGA_DPRAM_W_INT_LINE	0x00100000	/* 64 B */
-#define CONFIG_SYS_FPGA_DPRAM_RW_TYPE		0x00080000
-#define CONFIG_SYS_FPGA_DPRAM_RST		0x00040000
-#define CONFIG_SYS_FPGA_UART0_FO		0x00020000
-#define CONFIG_SYS_FPGA_UART1_FO		0x00010000
-
-/* loopback */
-#define CONFIG_SYS_FPGA_CHIPSIDE_LOOPBACK	0x00004000
-#define CONFIG_SYS_FPGA_LINESIDE_LOOPBACK	0x00008000
-#define CONFIG_SYS_FPGA_SLIC0_ENABLE		0x00002000
-#define CONFIG_SYS_FPGA_SLIC1_ENABLE		0x00001000
-#define CONFIG_SYS_FPGA_SLIC0_CS		0x00000800
-#define CONFIG_SYS_FPGA_SLIC1_CS		0x00000400
-#define CONFIG_SYS_FPGA_USER_LED0		0x00000200
-#define CONFIG_SYS_FPGA_USER_LED1		0x00000100
-
-#define CONFIG_SYS_FPGA_MAGIC_MASK		0xffff0000
-#define CONFIG_SYS_FPGA_MAGIC			0xabcd0000
-#define CONFIG_SYS_FPGA_VER_MASK		0x0000ff00
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/luan.h b/include/configs/luan.h
deleted file mode 100644
index f4a63de088..0000000000
--- a/include/configs/luan.h
+++ /dev/null
@@ -1,173 +0,0 @@
-/*
- * (C) Copyright 2005
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- * John Otken, jotken@softadvances.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/************************************************************************
- * luan.h - configuration for LUAN board
- ***********************************************************************/
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- *----------------------------------------------------------------------*/
-#define CONFIG_LUAN		1	/* Board is Luan		*/
-#define CONFIG_440SP		1	/* Specific PPC440SP support    */
-#define CONFIG_440		1
-#define CONFIG_SYS_CLK_FREQ	33333333 /* external freq to pll	*/
-
-#define	CONFIG_SYS_TEXT_BASE	0xFFFB0000
-
-/*
- * Include common defines/options for all AMCC eval boards
- */
-#define CONFIG_HOSTNAME		luan
-#include "amcc-common.h"
-
-#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
-
-/*-----------------------------------------------------------------------
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_LARGE_FLASH		0xffc00000	/* 4MB flash address CS0 */
-#define CONFIG_SYS_SMALL_FLASH		0xff900000	/* 1MB flash address CS2 */
-#define CONFIG_SYS_SRAM_BASE		0xff800000	/* 1MB SRAM  address CS2 */
-#define CONFIG_SYS_SRAM_SIZE		(1 << 20)
-#define CONFIG_SYS_EPLD_BASE		0xff000000	/* EPLD and FRAM     CS1 */
-
-#define CONFIG_SYS_ISRAM_BASE	        0xf8000000	/* internal 8k SRAM (L2 cache) */
-
-#define CONFIG_SYS_PCI_MEMBASE		0x80000000	/* mapped pci memory */
-#define CONFIG_SYS_PCI_BASE		0xd0000000	/* internal PCI regs */
-#define CONFIG_SYS_PCI_TARGBASE	0x80000000	/* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
-
-#if CONFIG_SYS_LARGE_FLASH == 0xffc00000
-#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_LARGE_FLASH
-#else
-#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_SMALL_FLASH
-#endif
-
-#if CONFIG_SYS_SRAM_BASE
-#define CONFIG_SYS_KBYTES_SDRAM	1024*2
-#else
-#define CONFIG_SYS_KBYTES_SDRAM	1024
-#endif
-
-/*-----------------------------------------------------------------------
- * Initial RAM & stack pointer (placed in SDRAM)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_ISRAM_BASE
-#define CONFIG_SYS_INIT_RAM_SIZE	(8 << 10)
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Serial Port
- *----------------------------------------------------------------------*/
-#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
-#define CONFIG_SYS_EXT_SERIAL_CLOCK	11059200 /* external 11.059MHz clk */
-
-/*-----------------------------------------------------------------------
- * Environment
- *----------------------------------------------------------------------*/
-/*
- * Define here the location of the environment variables (FLASH or EEPROM).
- * Note: DENX encourages to use redundant environment in FLASH.
- */
-#define CONFIG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
-
-/*-----------------------------------------------------------------------
- * FLASH related
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MAX_FLASH_BANKS	3	/* max number of memory banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-
-#define CONFIG_SYS_FLASH_ADDR0         0x555
-#define CONFIG_SYS_FLASH_ADDR1         0x2aa
-#define CONFIG_SYS_FLASH_WORD_SIZE     unsigned char
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE	0x10000 /* size of one complete sector	*/
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
-
-/* Address and size of Redundant Environment Sector	*/
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
-#endif /* CONFIG_ENV_IS_IN_FLASH */
-
-/*-----------------------------------------------------------------------
- * DDR SDRAM
- *----------------------------------------------------------------------*/
-#define CONFIG_SPD_EEPROM	1	/* Use SPD EEPROM for setup	*/
-#define SPD_EEPROM_ADDRESS	{0x53, 0x52}	/* SPD i2c spd addresses*/
-#define CONFIG_DDR_ECC		1	/* with ECC support		*/
-
-/*-----------------------------------------------------------------------
- * I2C
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR	(0xa8>>1)
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-/*
- * Default environment variables
- */
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	CONFIG_AMCC_DEF_ENV						\
-	CONFIG_AMCC_DEF_ENV_PPC						\
-	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
-	"kernel_addr=fc000000\0"					\
-	"ramdisk_addr=fc100000\0"					\
-	""
-
-#define CONFIG_HAS_ETH0
-#define CONFIG_PHY_ADDR		1
-#define CONFIG_CIS8201_PHY	1	/* Enable 'special' RGMII mode for Cicada phy */
-#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
-
-#ifdef DEBUG
-#define CONFIG_PANIC_HANG
-#else
-#define CONFIG_HW_WATCHDOG			/* watchdog */
-#endif
-
-/*
- * Commands additional to the ones defined in amcc-common.h
- */
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_SDRAM
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#if defined(CONFIG_CMD_PCI)
-
-/* General PCI */
-#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
-#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
-
-/* Board-specific PCI */
-#define CONFIG_SYS_PCI_TARGET_INIT
-#undef  CONFIG_SYS_PCI_MASTER_INIT
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x4403	/* whatever */
-
-#endif
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h
deleted file mode 100644
index 8971096a98..0000000000
--- a/include/configs/lwmon5.h
+++ /dev/null
@@ -1,582 +0,0 @@
-/*
- * (C) Copyright 2007-2013
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * lwmon5.h - configuration for lwmon5 board
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_LWMON5		1		/* Board is lwmon5	*/
-#define CONFIG_440EPX		1		/* Specific PPC440EPx	*/
-#define CONFIG_440		1		/* ... PPC440 family	*/
-
-#define CONFIG_SYS_TEXT_BASE	0xFFF80000
-#define CONFIG_HOSTNAME		lwmon5
-
-#define CONFIG_SYS_CLK_FREQ	33300000	/* external freq to pll	*/
-
-#define CONFIG_4xx_DCACHE		/* enable cache in SDRAM	*/
-
-#define CONFIG_BOARD_EARLY_INIT_R	/* Call board_early_init_r	*/
-#define CONFIG_BOARD_POSTCLK_INIT	/* Call board_postclk_init	*/
-#define CONFIG_MISC_INIT_R		/* Call misc_init_r		*/
-#define CONFIG_BOARD_RESET		/* Call board_reset		*/
-
-/*
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- */
-#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE	/* Start of U-Boot	*/
-#define CONFIG_SYS_MONITOR_LEN		0x80000
-#define CONFIG_SYS_MALLOC_LEN		(1 << 20)	/* Reserved for malloc	*/
-
-#define CONFIG_SYS_BOOT_BASE_ADDR	0xf0000000
-#define CONFIG_SYS_SDRAM_BASE		0x00000000	/* _must_ be 0		*/
-#define CONFIG_SYS_FLASH_BASE		0xf8000000	/* start of FLASH	*/
-#define CONFIG_SYS_LIME_BASE_0		0xc0000000
-#define CONFIG_SYS_LIME_BASE_1		0xc1000000
-#define CONFIG_SYS_LIME_BASE_2		0xc2000000
-#define CONFIG_SYS_LIME_BASE_3		0xc3000000
-#define CONFIG_SYS_FPGA_BASE_0		0xc4000000
-#define CONFIG_SYS_FPGA_BASE_1		0xc4200000
-#define CONFIG_SYS_OCM_BASE		0xe0010000      /* ocm			*/
-#define CONFIG_SYS_PCI_BASE		0xe0000000      /* Internal PCI regs	*/
-#define CONFIG_SYS_PCI_MEMBASE		0x80000000	/* mapped pci memory	*/
-#define CONFIG_SYS_PCI_MEMBASE1		(CONFIG_SYS_PCI_MEMBASE  + 0x10000000)
-#define CONFIG_SYS_PCI_MEMBASE2		(CONFIG_SYS_PCI_MEMBASE1 + 0x10000000)
-#define CONFIG_SYS_PCI_MEMBASE3		(CONFIG_SYS_PCI_MEMBASE2 + 0x10000000)
-
-#define CONFIG_SYS_USB2D0_BASE		0xe0000100
-#define CONFIG_SYS_USB_DEVICE		0xe0000000
-#define CONFIG_SYS_USB_HOST		0xe0000400
-
-/*
- * Initial RAM & stack pointer
- *
- * On LWMON5 we use D-cache as init-ram and stack pointer. We also move
- * the POST_WORD from OCM to a 440EPx register that preserves it's
- * content during reset (GPT0_COMP6). This way we reserve the OCM (16k)
- * for logbuffer only. (GPT0_COMP1-COMP5 are reserved for logbuffer header.)
- */
-#define CONFIG_SYS_INIT_RAM_DCACHE	1		/* d-cache as init ram	*/
-#define CONFIG_SYS_INIT_RAM_ADDR	0x70000000		/* DCache       */
-#define CONFIG_SYS_INIT_RAM_SIZE		(4 << 10)
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
-					 GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/* unused GPT0 COMP reg	*/
-#define CONFIG_SYS_POST_WORD_ADDR	(CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
-#define CONFIG_SYS_OCM_SIZE		(16 << 10)
-/* 440EPx errata CHIP 11: don't use last 4kbytes */
-#define CONFIG_SYS_MEM_TOP_HIDE		(4 << 10)
-
-/* Additional registers for watchdog timer post test */
-#define CONFIG_SYS_WATCHDOG_TIME_ADDR	(CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK2)
-#define CONFIG_SYS_WATCHDOG_FLAGS_ADDR	(CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK1)
-#define CONFIG_SYS_DSPIC_TEST_ADDR	CONFIG_SYS_WATCHDOG_FLAGS_ADDR
-#define CONFIG_SYS_OCM_STATUS_ADDR	CONFIG_SYS_WATCHDOG_FLAGS_ADDR
-#define CONFIG_SYS_WATCHDOG_MAGIC	0x12480000
-#define CONFIG_SYS_WATCHDOG_MAGIC_MASK	0xFFFF0000
-#define CONFIG_SYS_DSPIC_TEST_MASK	0x00000001
-#define CONFIG_SYS_OCM_STATUS_OK	0x00009A00
-#define CONFIG_SYS_OCM_STATUS_FAIL	0x0000A300
-#define CONFIG_SYS_OCM_STATUS_MASK	0x0000FF00
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX	2	/* Use UART1			*/
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK		/* no external clock provided	*/
-
-#define CONFIG_SYS_BAUDRATE_TABLE						\
-	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-/*
- * Environment
- */
-#define CONFIG_ENV_IS_IN_FLASH		/* use FLASH for environment vars	*/
-
-/*
- * FLASH related
- */
-#define CONFIG_SYS_FLASH_CFI			/* The flash is CFI compatible	*/
-#define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver	*/
-
-#define CONFIG_SYS_FLASH0		0xFC000000
-#define CONFIG_SYS_FLASH1		0xF8000000
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
-
-#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2	/* max number of memory banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 	/* use buffered writes (20x faster)	*/
-#define CONFIG_SYS_FLASH_PROTECTION		/* use hardware flash protection	*/
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_QUIET_TEST		/* don't warn upon unknown flash	*/
-
-#define CONFIG_ENV_SECT_SIZE	0x40000	/* size of one complete sector		*/
-#define CONFIG_ENV_ADDR		((-CONFIG_SYS_MONITOR_LEN) - CONFIG_ENV_SECT_SIZE)
-#define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
-
-/* Address and size of Redundant Environment Sector	*/
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
-
-/*
- * DDR SDRAM
- */
-#define CONFIG_SYS_MBYTES_SDRAM		256
-#define CONFIG_SYS_DDR_CACHED_ADDR	0x40000000	/* setup 2nd TLB cached here	*/
-#define CONFIG_DDR_DATA_EYE			/* use DDR2 optimization	*/
-#define CONFIG_DDR_ECC				/* enable ECC			*/
-
-/* POST support */
-#define CONFIG_POST		(CONFIG_SYS_POST_CACHE		| \
-				 CONFIG_SYS_POST_CPU		| \
-				 CONFIG_SYS_POST_ECC		| \
-				 CONFIG_SYS_POST_ETHER		| \
-				 CONFIG_SYS_POST_FPU		| \
-				 CONFIG_SYS_POST_I2C		| \
-				 CONFIG_SYS_POST_MEMORY		| \
-				 CONFIG_SYS_POST_OCM		| \
-				 CONFIG_SYS_POST_RTC		| \
-				 CONFIG_SYS_POST_SPR		| \
-				 CONFIG_SYS_POST_UART		| \
-				 CONFIG_SYS_POST_SYSMON		| \
-				 CONFIG_SYS_POST_WATCHDOG	| \
-				 CONFIG_SYS_POST_DSP		| \
-				 CONFIG_SYS_POST_BSPEC1		| \
-				 CONFIG_SYS_POST_BSPEC2		| \
-				 CONFIG_SYS_POST_BSPEC3		| \
-				 CONFIG_SYS_POST_BSPEC4		| \
-				 CONFIG_SYS_POST_BSPEC5)
-
-/* Define here the base-addresses of the UARTs to test in POST */
-#define CONFIG_SYS_POST_UART_TABLE	{ CONFIG_SYS_NS16550_COM1, \
-			CONFIG_SYS_NS16550_COM2 }
-
-#define CONFIG_POST_UART  {				\
-	"UART test",					\
-	"uart",						\
-	"This test verifies the UART operation.",	\
-	POST_RAM | POST_SLOWTEST | POST_ALWAYS | POST_MANUAL,	\
-	&uart_post_test,				\
-	NULL,						\
-	NULL,						\
-	CONFIG_SYS_POST_UART				\
-	}
-
-#define CONFIG_POST_WATCHDOG  {				\
-	"Watchdog timer test",				\
-	"watchdog",					\
-	"This test checks the watchdog timer.",		\
-	POST_RAM | POST_POWERON | POST_SLOWTEST | POST_MANUAL | POST_REBOOT, \
-	&lwmon5_watchdog_post_test,			\
-	NULL,						\
-	NULL,						\
-	CONFIG_SYS_POST_WATCHDOG			\
-	}
-
-#define CONFIG_POST_BSPEC1    {				\
-	"dsPIC init test",				\
-	"dspic_init",					\
-	"This test returns result of dsPIC READY test run earlier.",	\
-	POST_RAM | POST_ALWAYS,				\
-	&dspic_init_post_test,				\
-	NULL,						\
-	NULL,						\
-	CONFIG_SYS_POST_BSPEC1				\
-	}
-
-#define CONFIG_POST_BSPEC2    {				\
-	"dsPIC test",					\
-	"dspic",					\
-	"This test gets result of dsPIC POST and dsPIC version.",	\
-	POST_RAM | POST_ALWAYS,				\
-	&dspic_post_test,				\
-	NULL,						\
-	NULL,						\
-	CONFIG_SYS_POST_BSPEC2				\
-	}
-
-#define CONFIG_POST_BSPEC3    {				\
-	"FPGA test",					\
-	"fpga",						\
-	"This test checks FPGA registers and memory.",	\
-	POST_RAM | POST_ALWAYS | POST_MANUAL,		\
-	&fpga_post_test,				\
-	NULL,						\
-	NULL,						\
-	CONFIG_SYS_POST_BSPEC3				\
-	}
-
-#define CONFIG_POST_BSPEC4    {				\
-	"GDC test",					\
-	"gdc",						\
-	"This test checks GDC registers and memory.",	\
-	POST_RAM | POST_ALWAYS | POST_MANUAL,\
-	&gdc_post_test,					\
-	NULL,						\
-	NULL,						\
-	CONFIG_SYS_POST_BSPEC4				\
-	}
-
-#define CONFIG_POST_BSPEC5    {				\
-	"SYSMON1 test",					\
-	"sysmon1",					\
-	"This test checks GPIO_62_EPX pin indicating power failure.",	\
-	POST_RAM | POST_MANUAL | POST_NORMAL | POST_SLOWTEST,	\
-	&sysmon1_post_test,				\
-	NULL,						\
-	NULL,						\
-	CONFIG_SYS_POST_BSPEC5				\
-	}
-
-#define CONFIG_SYS_POST_CACHE_ADDR	0x7fff0000 /* free virtual address	*/
-#define CONFIG_LOGBUFFER
-/* Reserve GPT0_COMP1-COMP5 for logbuffer header */
-#define CONFIG_ALT_LH_ADDR	(CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP1)
-#define CONFIG_ALT_LB_ADDR	(CONFIG_SYS_OCM_BASE)
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		100000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
-
-#define CONFIG_SYS_I2C_RTC_ADDR	0x51	/* RTC				*/
-#define CONFIG_SYS_I2C_EEPROM_CPU_ADDR	0x52	/* EEPROM          (CPU Modul)	*/
-#define CONFIG_SYS_I2C_EEPROM_MB_ADDR	0x53	/* EEPROM AT24C128 (MainBoard)	*/
-#define CONFIG_SYS_I2C_DSPIC_ADDR	0x54	/* dsPIC   			*/
-#define CONFIG_SYS_I2C_DSPIC_2_ADDR	0x55	/* dsPIC			*/
-#define CONFIG_SYS_I2C_DSPIC_KEYB_ADDR	0x56	/* dsPIC			*/
-#define CONFIG_SYS_I2C_DSPIC_IO_ADDR	0x57	/* dsPIC			*/
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2	/* Bytes of address		*/
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6	/* The Atmel AT24C128 has	*/
-					/* 64 byte page write mode using*/
-					/* last 6 bits of the address	*/
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
-
-#define CONFIG_RTC_PCF8563			/* enable Philips PCF8563 RTC	*/
-#define CONFIG_SYS_I2C_RTC_ADDR		0x51	/* Philips PCF8563 RTC address	*/
-#define CONFIG_SYS_I2C_KEYBD_ADDR	0x56	/* PIC LWE keyboard		*/
-#define CONFIG_SYS_I2C_DSPIC_IO_ADDR	0x57	/* PIC I/O addr               */
-
-#define CONFIG_SYS_POST_I2C_ADDRS	{CONFIG_SYS_I2C_RTC_ADDR,	\
-					 CONFIG_SYS_I2C_EEPROM_CPU_ADDR,\
-					 CONFIG_SYS_I2C_EEPROM_MB_ADDR,	\
-					 CONFIG_SYS_I2C_DSPIC_ADDR,	\
-					 CONFIG_SYS_I2C_DSPIC_2_ADDR,	\
-					 CONFIG_SYS_I2C_DSPIC_KEYB_ADDR,\
-					 CONFIG_SYS_I2C_DSPIC_IO_ADDR }
-
-/* Update size in "reg" property of NOR FLASH device tree nodes */
-#define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
-
-#define	CONFIG_POST_KEY_MAGIC	"3C+3E"	/* press F3 + F5 keys to force POST */
-
-#define	CONFIG_PREBOOT		"setenv bootdelay 15"
-
-#undef	CONFIG_BOOTARGS
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"hostname=lwmon5\0"						\
-	"netdev=eth0\0"							\
-	"unlock=yes\0"							\
-	"logversion=2\0"						\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\
-	"addmisc=setenv bootargs ${bootargs} rtc-pcf8563.probe=0,0x51\0"\
-	"flash_nfs=run nfsargs addip addtty addmisc;"			\
-		"bootm ${kernel_addr}\0"				\
-	"flash_self=run ramargs addip addtty addmisc;"			\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"net_nfs=tftp 200000 ${bootfile};"				\
-		"run nfsargs addip addtty addmisc;bootm\0"		\
-	"rootpath=/opt/eldk/ppc_4xxFP\0"				\
-	"bootfile=/tftpboot/lwmon5/uImage\0"				\
-	"kernel_addr=FC000000\0"					\
-	"ramdisk_addr=FC180000\0"					\
-	"load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0"		\
-	"update=protect off FFF80000 FFFFFFFF;era FFF80000 FFFFFFFF;"	\
-		"cp.b 200000 FFF80000 80000\0"			        \
-	"upd=run load update\0"						\
-	"lwe_env=tftp 200000 /tftpboot.dev/lwmon5/env_uboot.bin;"	\
-		"autoscr 200000\0"					\
-	""
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#define CONFIG_PPC4xx_EMAC
-#define	CONFIG_IBM_EMAC4_V4	1
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_PHY_ADDR		3	/* PHY address, See schematics	*/
-
-#define CONFIG_PHY_RESET        1	/* reset phy upon startup         */
-#define CONFIG_PHY_RESET_DELAY	300
-
-#define CONFIG_HAS_ETH0
-#define CONFIG_SYS_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
-
-#define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"	*/
-#define CONFIG_PHY1_ADDR	1
-
-/* Video console */
-#define CONFIG_VIDEO_MB862xx
-#define CONFIG_VIDEO_MB862xx_ACCEL
-#define CONFIG_VIDEO_LOGO
-#define VIDEO_FB_16BPP_PIXEL_SWAP
-#define VIDEO_FB_16BPP_WORD_SWAP
-
-#define CONFIG_SPLASH_SCREEN
-
-/*
- * USB/EHCI
- */
-#define CONFIG_USB_EHCI_PPC4XX		/* on PPC4xx platform		*/
-#define CONFIG_SYS_PPC4XX_USB_ADDR	0xe0000300
-#define CONFIG_EHCI_MMIO_BIG_ENDIAN
-#define CONFIG_EHCI_DESC_BIG_ENDIAN
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* re-init HCD after CMD_RESET */
-
-/* Partitions */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SDRAM
-
-#ifdef CONFIG_440EPX
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SUPPORT_VFAT
-
-#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE	        1024	/* Console I/O Buffer Size	*/
-#else
-#define CONFIG_SYS_CBSIZE	        256	/* Console I/O Buffer Size	*/
-#endif
-#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS	        16	/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	        CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x0400000 /* memtest works on		*/
-#define CONFIG_SYS_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
-
-#define CONFIG_SYS_LOAD_ADDR		0x100000  /* default load address	*/
-#define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */
-
-#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
-
-#ifndef DEBUG
-#define CONFIG_HW_WATCHDOG	1	/* Use external HW-Watchdog	*/
-#endif
-#define CONFIG_WD_PERIOD	40000	/* in usec */
-#define CONFIG_WD_MAX_RATE	66600	/* in ticks */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 16 MB of memory, since this is
- * the maximum mapped by the 40x Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ		(16 << 20) /* Initial Memory map for Linux */
-#define CONFIG_SYS_BOOTM_LEN		(16 << 20) /* Increase max gunzip size */
-
-/*
- * External Bus Controller (EBC) Setup
- */
-#define CONFIG_SYS_FLASH		CONFIG_SYS_FLASH_BASE
-
-/* Memory Bank 0 (NOR-FLASH) initialization					*/
-#define CONFIG_SYS_EBC_PB0AP		0x03000280
-#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_FLASH | 0xfc000)
-
-/* Memory Bank 1 (Lime) initialization						*/
-#define CONFIG_SYS_EBC_PB1AP		0x01004380
-#define CONFIG_SYS_EBC_PB1CR		(CONFIG_SYS_LIME_BASE_0 | 0xbc000)
-
-/* Memory Bank 2 (FPGA) initialization						*/
-#define CONFIG_SYS_EBC_PB2AP		0x01004400
-#define CONFIG_SYS_EBC_PB2CR		(CONFIG_SYS_FPGA_BASE_0 | 0x1c000)
-
-/* Memory Bank 3 (FPGA2) initialization						*/
-#define CONFIG_SYS_EBC_PB3AP		0x01004400
-#define CONFIG_SYS_EBC_PB3CR		(CONFIG_SYS_FPGA_BASE_1 | 0x1c000)
-
-#define CONFIG_SYS_EBC_CFG		0xb8400000
-
-/*
- * Graphics (Fujitsu Lime)
- */
-/* SDRAM Clock frequency adjustment register */
-#define CONFIG_SYS_LIME_SDRAM_CLOCK	0xC1FC0038
-#if 1 /* 133MHz is not tested enough, use 100MHz for now */
-/* Lime Clock frequency is to set 100MHz */
-#define CONFIG_SYS_LIME_CLOCK_100MHZ	0x00000
-#else
-/* Lime Clock frequency for 133MHz */
-#define CONFIG_SYS_LIME_CLOCK_133MHZ	0x10000
-#endif
-
-/* SDRAM Parameter register */
-#define CONFIG_SYS_LIME_MMR		0xC1FCFFFC
-/*
- * SDRAM parameter value; was 0x414FB7F2, caused several vertical bars
- * and pixel flare on display when 133MHz was configured. According to
- * SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed
- * Grade
- */
-#ifdef CONFIG_SYS_LIME_CLOCK_133MHZ
-#define CONFIG_SYS_MB862xx_MMR	0x414FB7F3
-#define CONFIG_SYS_MB862xx_CCF	CONFIG_SYS_LIME_CLOCK_133MHZ
-#else
-#define CONFIG_SYS_MB862xx_MMR	0x414FB7F2
-#define CONFIG_SYS_MB862xx_CCF	CONFIG_SYS_LIME_CLOCK_100MHZ
-#endif
-
-/*
- * GPIO Setup
- */
-#define CONFIG_SYS_GPIO_PHY1_RST	12
-#define CONFIG_SYS_GPIO_FLASH_WP	14
-#define CONFIG_SYS_GPIO_PHY0_RST	22
-#define CONFIG_SYS_GPIO_PERM_VOLT_FEED	49
-#define CONFIG_SYS_GPIO_DSPIC_READY	51
-#define CONFIG_SYS_GPIO_CAN_ENABLE	53
-#define CONFIG_SYS_GPIO_LSB_ENABLE	54
-#define CONFIG_SYS_GPIO_EEPROM_EXT_WP	55
-#define CONFIG_SYS_GPIO_HIGHSIDE	56
-#define CONFIG_SYS_GPIO_EEPROM_INT_WP	57
-#define CONFIG_SYS_GPIO_BOARD_RESET	58
-#define CONFIG_SYS_GPIO_LIME_S		59
-#define CONFIG_SYS_GPIO_LIME_RST	60
-#define CONFIG_SYS_GPIO_SYSMON_STATUS	62
-#define CONFIG_SYS_GPIO_WATCHDOG	63
-
-#define GPIO49_VAL	1
-
-/*
- * PPC440 GPIO Configuration
- */
-#define CONFIG_SYS_4xx_GPIO_TABLE { /*	  Out		  GPIO	Alternate1	Alternate2	Alternate3 */ \
-{											\
-/* GPIO Core 0 */									\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0	EBC_ADDR(7)	DMA_REQ(2)	*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1	EBC_ADDR(6)	DMA_ACK(2)	*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2	EBC_ADDR(5)	DMA_EOT/TC(2)	*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3	EBC_ADDR(4)	DMA_REQ(3)	*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4	EBC_ADDR(3)	DMA_ACK(3)	*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5	EBC_ADDR(2)	DMA_EOT/TC(3)	*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6	EBC_CS_N(1)			*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7	EBC_CS_N(2)			*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8	EBC_CS_N(3)			*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9	EBC_CS_N(4)			*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5)			*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR			*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12				*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO13				*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14				*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO15				*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4)			*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMCTxD(5)			*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMCTxD(6)			*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMCTxD(7)			*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0			*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1			*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO22				*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0				*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 GMCTxD(2)			*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 GMCTxD(3)			*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26				*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ	USB2D_RXERROR	*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28		USB2D_TXVALID	*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA	USB2D_PAD_SUSPNDM */	\
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK	USB2D_XCVRSELECT*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ	USB2D_TERMSELECT*/	\
-},											\
-{											\
-/* GPIO Core 1 */									\
-{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO32 USB2D_OPMODE0	EBC_DATA(2)	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO33 USB2D_OPMODE1	EBC_DATA(3)	*/	\
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N	UART1_DSR_CTS_N	UART2_SOUT*/ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0)	UART3_SIN*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N	EBC_DATA(1)	UART3_SOUT*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO38 UART0_DTR_N	UART1_SOUT	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N	UART1_SIN	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0)			*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1)			*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2)			*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3)			*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4)	DMA_ACK(1)	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6)	DMA_EOT/TC(1)	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7)	DMA_REQ(0)	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8)	DMA_ACK(0)	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9)	DMA_EOT/TC(0)	*/	\
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO49_VAL}, /* GPIO49  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN,  GPIO_SEL , GPIO_OUT_0}, /* GPIO50  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO53  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO54  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO56  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO57  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO58  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO59  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO60  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO63  Unselect via TraceSelect Bit	*/	\
-}											\
-}
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#endif
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/makalu.h b/include/configs/makalu.h
deleted file mode 100644
index a92bc43538..0000000000
--- a/include/configs/makalu.h
+++ /dev/null
@@ -1,332 +0,0 @@
-/*
- * Copyright (c) 2008 Nuovation System Designs, LLC
- *   Grant Erickson <gerickson@nuovations.com>
- *
- * (C) Copyright 2007-2008
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/************************************************************************
- * makalu.h - configuration for AMCC Makalu (405EX)
- ***********************************************************************/
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- *----------------------------------------------------------------------*/
-#define CONFIG_MAKALU		1		/* Board is Makalu	*/
-#define CONFIG_405EX		1		/* Specifc 405EX support*/
-#define CONFIG_SYS_CLK_FREQ	33330000	/* ext frequency to pll	*/
-
-#define	CONFIG_SYS_TEXT_BASE	0xFFFA0000
-
-/*
- * Include common defines/options for all AMCC eval boards
- */
-#define CONFIG_HOSTNAME	makalu
-#define CONFIG_ADDMISC	"addmisc=setenv bootargs ${bootargs} rtc-x1205.probe=0,0x6f\0"
-#include "amcc-common.h"
-
-#define CONFIG_MISC_INIT_R	1		/* Call misc_init_r	*/
-
-/*-----------------------------------------------------------------------
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_FLASH_BASE		0xFC000000
-#define CONFIG_SYS_FPGA_BASE		0xF0000000
-
-/*-----------------------------------------------------------------------
- * Initial RAM & Stack Pointer Configuration Options
- *
- *   There are traditionally three options for the primordial
- *   (i.e. initial) stack usage on the 405-series:
- *
- *      1) On-chip Memory (OCM) (i.e. SRAM)
- *      2) Data cache
- *      3) SDRAM
- *
- *   For the 405EX(r), there is no OCM, so we are left with (2) or (3)
- *   the latter of which is less than desireable since it requires
- *   setting up the SDRAM and ECC in assembly code.
- *
- *   To use (2), define 'CONFIG_SYS_INIT_DCACHE_CS' to be an unused chip
- *   select on the External Bus Controller (EBC) and then select a
- *   value for 'CONFIG_SYS_INIT_RAM_ADDR' outside of the range of valid,
- *   physical SDRAM. Otherwise, undefine 'CONFIG_SYS_INIT_DCACHE_CS' and
- *   select a value for 'CONFIG_SYS_INIT_RAM_ADDR' within the range of valid,
- *   physical SDRAM to use (3).
- *-----------------------------------------------------------------------*/
-
-#define CONFIG_SYS_INIT_DCACHE_CS	4
-
-#if defined(CONFIG_SYS_INIT_DCACHE_CS)
-#define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_SDRAM_BASE + ( 1 << 30))	/*  1 GiB */
-#else
-#define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_SDRAM_BASE + (32 << 20))	/* 32 MiB */
-#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
-
-#define CONFIG_SYS_INIT_RAM_SIZE        (4 << 10)			/*  4 KiB */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-/*
- * If the data cache is being used for the primordial stack and global
- * data area, the POST word must be placed somewhere else. The General
- * Purpose Timer (GPT) is unused by u-boot and the kernel and preserves
- * its compare and mask register contents across reset, so it is used
- * for the POST word.
- */
-
-#if defined(CONFIG_SYS_INIT_DCACHE_CS)
-# define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-# define CONFIG_SYS_POST_WORD_ADDR	(CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
-#else
-# define CONFIG_SYS_INIT_EXTRA_SIZE	16
-# define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_EXTRA_SIZE)
-# define CONFIG_SYS_OCM_DATA_ADDR	CONFIG_SYS_INIT_RAM_ADDR
-#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
-
-/*-----------------------------------------------------------------------
- * Serial Port
- *----------------------------------------------------------------------*/
-#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK			/* no ext. clk		*/
-
-/*-----------------------------------------------------------------------
- * Environment
- *----------------------------------------------------------------------*/
-#define CONFIG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
-
-/*-----------------------------------------------------------------------
- * FLASH related
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_FLASH_CFI			/* The flash is CFI compatible	*/
-#define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/
-
-#define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE}
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
-#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE	0x20000	/* size of one complete sector	*/
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
-#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
-
-/* Address and size of Redundant Environment Sector	*/
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
-#endif /* CONFIG_ENV_IS_IN_FLASH */
-
-/*-----------------------------------------------------------------------
- * DDR SDRAM
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MBYTES_SDRAM        (256)		/* 256MB			*/
-
-#define	CONFIG_SYS_SDRAM0_MB0CF_BASE	((  0 << 20) + CONFIG_SYS_SDRAM_BASE)
-#define	CONFIG_SYS_SDRAM0_MB1CF_BASE	((128 << 20) + CONFIG_SYS_SDRAM_BASE)
-
-/* DDR1/2 SDRAM Device Control Register Data Values */
-#define CONFIG_SYS_SDRAM0_MB0CF	((CONFIG_SYS_SDRAM0_MB0CF_BASE >> 3)	| \
-				 SDRAM_RXBAS_SDSZ_128MB 	| \
-				 SDRAM_RXBAS_SDAM_MODE2 	| \
-				 SDRAM_RXBAS_SDBE_ENABLE)
-#define CONFIG_SYS_SDRAM0_MB1CF	((CONFIG_SYS_SDRAM0_MB1CF_BASE >> 3)	| \
-				 SDRAM_RXBAS_SDSZ_128MB 	| \
-				 SDRAM_RXBAS_SDAM_MODE2 	| \
-				 SDRAM_RXBAS_SDBE_ENABLE)
-#define CONFIG_SYS_SDRAM0_MB2CF	SDRAM_RXBAS_SDBE_DISABLE
-#define CONFIG_SYS_SDRAM0_MB3CF	SDRAM_RXBAS_SDBE_DISABLE
-#define CONFIG_SYS_SDRAM0_MCOPT1	0x04322000
-#define CONFIG_SYS_SDRAM0_MCOPT2	0x00000000
-#define CONFIG_SYS_SDRAM0_MODT0	0x01800000
-#define CONFIG_SYS_SDRAM0_MODT1	0x00000000
-#define CONFIG_SYS_SDRAM0_CODT		0x0080f837
-#define CONFIG_SYS_SDRAM0_RTR		0x06180000
-#define CONFIG_SYS_SDRAM0_INITPLR0	0xa8380000
-#define CONFIG_SYS_SDRAM0_INITPLR1	0x81900400
-#define CONFIG_SYS_SDRAM0_INITPLR2	0x81020000
-#define CONFIG_SYS_SDRAM0_INITPLR3	0x81030000
-#define CONFIG_SYS_SDRAM0_INITPLR4	0x81010404
-#define CONFIG_SYS_SDRAM0_INITPLR5	0x81000542
-#define CONFIG_SYS_SDRAM0_INITPLR6	0x81900400
-#define CONFIG_SYS_SDRAM0_INITPLR7	0x8D080000
-#define CONFIG_SYS_SDRAM0_INITPLR8	0x8D080000
-#define CONFIG_SYS_SDRAM0_INITPLR9	0x8D080000
-#define CONFIG_SYS_SDRAM0_INITPLR10	0x8D080000
-#define CONFIG_SYS_SDRAM0_INITPLR11	0x81000442
-#define CONFIG_SYS_SDRAM0_INITPLR12	0x81010780
-#define CONFIG_SYS_SDRAM0_INITPLR13	0x81010400
-#define CONFIG_SYS_SDRAM0_INITPLR14	0x00000000
-#define CONFIG_SYS_SDRAM0_INITPLR15	0x00000000
-#define CONFIG_SYS_SDRAM0_RQDC		0x80000038
-#define CONFIG_SYS_SDRAM0_RFDC		0x00000209
-#define CONFIG_SYS_SDRAM0_RDCC		0x40000000
-#define CONFIG_SYS_SDRAM0_DLCR		0x030000a5
-#define CONFIG_SYS_SDRAM0_CLKTR	0x80000000
-#define CONFIG_SYS_SDRAM0_WRDTR	0x00000000
-#define CONFIG_SYS_SDRAM0_SDTR1	0x80201000
-#define CONFIG_SYS_SDRAM0_SDTR2	0x32204232
-#define CONFIG_SYS_SDRAM0_SDTR3	0x080b0d1a
-#define CONFIG_SYS_SDRAM0_MMODE	0x00000442
-#define CONFIG_SYS_SDRAM0_MEMODE	0x00000404
-
-/*-----------------------------------------------------------------------
- * I2C
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
-
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	6	/* 24C02 requires 5ms delay */
-#define CONFIG_SYS_I2C_EEPROM_ADDR	0x52	/* I2C boot EEPROM (24C02BN)	*/
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address		*/
-
-/* RTC configuration */
-#define CONFIG_RTC_X1205	1
-#define CONFIG_SYS_I2C_RTC_ADDR	0x6f
-
-/*-----------------------------------------------------------------------
- * Ethernet
- *----------------------------------------------------------------------*/
-#define CONFIG_M88E1111_PHY	1
-#define CONFIG_IBM_EMAC4_V4	1
-#define CONFIG_EMAC_PHY_MODE	EMAC_PHY_MODE_RGMII_RGMII
-#define CONFIG_PHY_ADDR		6	/* PHY address, See schematics	*/
-
-#define CONFIG_PHY_RESET	1	/* reset phy upon startup	*/
-#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
-
-#define CONFIG_HAS_ETH0		1
-
-#define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"   */
-#define CONFIG_PHY1_ADDR	0
-
-/*
- * Default environment variables
- */
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	CONFIG_AMCC_DEF_ENV						\
-	CONFIG_AMCC_DEF_ENV_POWERPC					\
-	CONFIG_AMCC_DEF_ENV_PPC_OLD					\
-	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
-	"kernel_addr=fc000000\0"					\
-	"fdt_addr=fc1e0000\0"						\
-	"ramdisk_addr=fc200000\0"					\
-	"pciconfighost=1\0"						\
-	"pcie_mode=RP:RP\0"						\
-	""
-
-/*
- * Commands additional to the ones defined in amcc-common.h
- */
-#define CONFIG_CMD_PCI
-
-/* POST support */
-#define CONFIG_POST		(CONFIG_SYS_POST_CACHE		| \
-				 CONFIG_SYS_POST_CPU		| \
-				 CONFIG_SYS_POST_ETHER		| \
-				 CONFIG_SYS_POST_I2C		| \
-				 CONFIG_SYS_POST_MEMORY	| \
-				 CONFIG_SYS_POST_UART)
-
-/* Define here the base-addresses of the UARTs to test in POST */
-#define CONFIG_SYS_POST_UART_TABLE	{ CONFIG_SYS_NS16550_COM1, \
-			CONFIG_SYS_NS16550_COM2 }
-
-#define CONFIG_LOGBUFFER
-#define CONFIG_SYS_POST_CACHE_ADDR	0x00800000 /* free virtual address	*/
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *----------------------------------------------------------------------*/
-#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
-#define CONFIG_PCI_SCAN_SHOW	1	/* show pci devices on startup	*/
-#define CONFIG_PCI_CONFIG_HOST_BRIDGE
-
-/*-----------------------------------------------------------------------
- * PCIe stuff
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_PCIE_MEMBASE	0x90000000	/* mapped PCIe memory	*/
-#define CONFIG_SYS_PCIE_MEMSIZE	0x08000000      /* 128 Meg, smallest incr per port */
-
-#define	CONFIG_SYS_PCIE0_CFGBASE	0xa0000000      /* remote access */
-#define	CONFIG_SYS_PCIE0_XCFGBASE	0xb0000000      /* local access */
-#define	CONFIG_SYS_PCIE0_CFGMASK	0xe0000001      /* 512 Meg */
-
-#define	CONFIG_SYS_PCIE1_CFGBASE	0xc0000000      /* remote access */
-#define	CONFIG_SYS_PCIE1_XCFGBASE	0xd0000000      /* local access */
-#define	CONFIG_SYS_PCIE1_CFGMASK	0xe0000001      /* 512 Meg */
-
-#define	CONFIG_SYS_PCIE0_UTLBASE	0xef502000
-#define	CONFIG_SYS_PCIE1_UTLBASE	0xef503000
-
-/* base address of inbound PCIe window */
-#define CONFIG_SYS_PCIE_INBOUND_BASE	0x0000000000000000ULL
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- *----------------------------------------------------------------------*/
-/* Memory Bank 0 (NOR-FLASH) initialization					*/
-#define CONFIG_SYS_EBC_PB0AP		0x08033700
-#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_FLASH_BASE | 0xda000)
-
-/* Memory Bank 2 (CPLD) initialization						*/
-#define CONFIG_SYS_EBC_PB2AP           0x9400C800
-#define CONFIG_SYS_EBC_PB2CR           0xF0018000 /*  BAS=0x800,BS=1MB,BU=R/W,BW=8bit	*/
-
-#define CONFIG_SYS_EBC_CFG		0x7FC00000 /*  EBC0_CFG */
-
-/*-----------------------------------------------------------------------
- * GPIO Setup
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_4xx_GPIO_TABLE { /*	  Out		  GPIO	Alternate1	Alternate2	Alternate3 */ \
-{											\
-/* GPIO Core 0 */									\
-{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO0	EBC_DATA_PAR(0)			*/	\
-{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO1	EBC_DATA_PAR(1)			*/	\
-{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO2	EBC_DATA_PAR(2)			*/	\
-{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO3	EBC_DATA_PAR(3)			*/	\
-{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO4	EBC_DATA(20)	USB2_DATA(4)	*/	\
-{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO5	EBC_DATA(21)	USB2_DATA(5)	*/	\
-{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO6	EBC_DATA(22)	USB2_DATA(6)	*/	\
-{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO7	EBC_DATA(23)	USB2_DATA(7)	*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8	CS(1)/NFCE(1)	IRQ(7)		*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9	CS(2)/NFCE(2)	IRQ(8)		*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 CS(3)/NFCE(3)	IRQ(9)		*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 IRQ(6)				*/	\
-{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO12 EBC_DATA(16)	USB2_DATA(0)	*/	\
-{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO13 EBC_DATA(17)	USB2_DATA(1)	*/	\
-{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO14 EBC_DATA(18)	USB2_DATA(2)	*/	\
-{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO15 EBC_DATA(19)	USB2_DATA(3)	*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 UART0_DCD	UART1_CTS	*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 UART0_DSR	UART1_RTS	*/	\
-{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 UART0_CTS			*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 UART0_RTS			*/	\
-{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO20 UART0_DTR	UART1_TX	*/	\
-{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO21 UART0_RI	UART1_RX	*/	\
-{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO22 EBC_HOLD_REQ	DMA_ACK2	*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_0}, /* GPIO23 EBC_HOLD_ACK	DMA_REQ2	*/	\
-{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO24 EBC_EXT_REQ	DMA_EOT2	IRQ(4) */ \
-{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO25 EBC_EXT_ACK	DMA_ACK3	IRQ(3) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 EBC_ADDR(5)	DMA_EOT0	TS(3) */ \
-{GPIO0_BASE, GPIO_IN,  GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EBC_BUS_REQ	DMA_EOT3	IRQ(5) */ \
-{GPIO0_BASE, GPIO_IN,  GPIO_SEL , GPIO_OUT_0}, /* GPIO28				*/	\
-{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO29 DMA_EOT1	IRQ(2)		*/	\
-{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO30 DMA_REQ1	IRQ(1)		*/	\
-{GPIO0_BASE, GPIO_IN,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO31 DMA_ACK1	IRQ(0)		*/	\
-}												\
-}
-
-#define CONFIG_SYS_GPIO_PCIE_RST	23
-#define CONFIG_SYS_GPIO_PCIE_CLKREQ	27
-#define CONFIG_SYS_GPIO_PCIE_WAKE	28
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/neo.h b/include/configs/neo.h
deleted file mode 100644
index 5a8a5c2422..0000000000
--- a/include/configs/neo.h
+++ /dev/null
@@ -1,219 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_405EP		1	/* this is a PPC405 CPU */
-#define CONFIG_NEO	        1	/*  on a Neo board */
-
-#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
-
-/*
- * Include common defines/options for all AMCC eval boards
- */
-#define CONFIG_HOSTNAME		neo
-#include "amcc-common.h"
-
-#define CONFIG_BOARD_EARLY_INIT_R
-#define CONFIG_MISC_INIT_R
-#define CONFIG_LAST_STAGE_INIT
-
-#define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll   */
-
-/*
- * Configure PLL
- */
-#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
-#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
-
-#define CONFIG_ENV_IS_IN_FLASH	/* use FLASH for environment vars */
-
-/*
- * Default environment variables
- */
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	CONFIG_AMCC_DEF_ENV						\
-	CONFIG_AMCC_DEF_ENV_POWERPC					\
-	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
-	"kernel_addr=fc000000\0"					\
-	"fdt_addr=fc1e0000\0"						\
-	"ramdisk_addr=fc200000\0"					\
-	""
-
-#define CONFIG_PHY_ADDR		4	/* PHY address			*/
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#define CONFIG_PHY1_ADDR	0xc	/* EMAC1 PHY address		*/
-#define CONFIG_PHY_CLK_FREQ    EMAC_STACR_CLK_66MHZ
-
-/*
- * Commands additional to the ones defined in amcc-common.h
- */
-
-/*
- * SDRAM configuration (please see cpu/ppc/sdram.[ch])
- */
-#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0 */
-
-/* SDRAM timings used in datasheet */
-#define CONFIG_SYS_SDRAM_CL            3	/* CAS latency */
-#define CONFIG_SYS_SDRAM_tRP           20	/* PRECHARGE command period */
-#define CONFIG_SYS_SDRAM_tRC           66	/* ACTIVE-to-ACTIVE command period */
-#define CONFIG_SYS_SDRAM_tRCD          20	/* ACTIVE-to-READ delay */
-#define CONFIG_SYS_SDRAM_tRFC		66	/* Auto refresh period */
-
-/*
- * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
- * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
- * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
- * The Linux BASE_BAUD define should match this configuration.
- *    baseBaud = cpuClock/(uartDivisor*16)
- * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
- * set Linux BASE_BAUD to 403200.
- */
-#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
-
-#undef  CONFIG_SYS_EXT_SERIAL_CLOCK           /* external serial clock */
-#undef  CONFIG_SYS_405_UART_ERRATA_59         /* 405GP/CR Rev. D silicon */
-#define CONFIG_SYS_BASE_BAUD		691200
-
-/*
- * I2C stuff
- */
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		100000
-
-/* RTC */
-#define CONFIG_RTC_DS1337
-#define CONFIG_SYS_I2C_RTC_ADDR	0x68
-
-/*
- * FLASH organization
- */
-#define CONFIG_SYS_FLASH_CFI				/* The flash is CFI compatible	*/
-#define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver	*/
-
-#define CONFIG_SYS_FLASH_BASE		0xFC000000
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash	*/
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE	0x20000	/* size of one complete sector		*/
-#define CONFIG_ENV_ADDR		0xFFF00000
-#define	CONFIG_ENV_SIZE		0x20000	/* Total Size of Environment Sector */
-
-/* Address and size of Redundant Environment Sector	*/
-#define CONFIG_ENV_ADDR_REDUND	0xFFF20000
-#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
-#endif
-
-/*
- * PPC405 GPIO Configuration
- */
-#define CONFIG_SYS_4xx_GPIO_TABLE { \
-{ \
-/* GPIO Core 0 */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO0	PerBLast   */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO1	TS1E	   */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO2	TS2E	   */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO3	TS1O	   */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO4	TS2O	   */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1      }, /* GPIO5	TS3	   */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO6	TS4	   */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO7	TS5	   */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO8	TS6	   */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO9	TrcClk	   */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10	PerCS1	   */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11	PerCS2	   */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12	PerCS3	   */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13	PerCS4	   */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14	PerAddr03  */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15	PerAddr04  */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16	PerAddr05  */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17	IRQ0	   */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18	IRQ1	   */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19	IRQ2	   */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO20	IRQ3	   */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO21	IRQ4	   */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO22	IRQ5	   */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO23	IRQ6	   */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24	UART0_DCD  */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25	UART0_DSR  */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26	UART0_RI   */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27	UART0_DTR  */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28	UART1_Rx   */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29	UART1_Tx   */ \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO30	RejectPkt0 */ \
-{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO31	RejectPkt1 */ \
-} \
-}
-
-/*
- * Definitions for initial stack pointer and data area (in data cache)
- */
-/* use on chip memory (OCM) for temperary stack until sdram is tested */
-#define CONFIG_SYS_TEMP_STACK_OCM        1
-
-/* On Chip Memory location */
-#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
-#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/*
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (NOR-FLASH) initialization                    */
-#define CONFIG_SYS_EBC_PB0AP		0x92015480
-#define CONFIG_SYS_EBC_PB0CR		0xFC0DA000  /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 1 (NVRAM) initialization                                        */
-#define CONFIG_SYS_EBC_PB1AP		0x92015480
-#define CONFIG_SYS_EBC_PB1CR		0xFB85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit  */
-
-/* Memory Bank 2 (FPGA) initialization                 */
-#define CONFIG_SYS_FPGA0_BASE		0x7f100000
-#define CONFIG_SYS_EBC_PB2AP		0x92015480
-#define CONFIG_SYS_EBC_PB2CR		0x7f11a000  /* BAS=0x7f1,BS=1MB,BU=R/W,BW=16bit */
-
-#define CONFIG_SYS_FPGA_BASE(k)		CONFIG_SYS_FPGA0_BASE
-
-#define CONFIG_SYS_FPGA_COUNT		1
-
-#define CONFIG_SYS_FPGA_PTR \
-	{ (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE }
-
-#define CONFIG_SYS_FPGA_COMMON
-
-/* Memory Bank 3 (Latches) initialization                      */
-#define CONFIG_SYS_LATCH_BASE		0x7f200000
-#define CONFIG_SYS_EBC_PB3AP		0x92015480
-#define CONFIG_SYS_EBC_PB3CR		0x7f21a000  /* BAS=0x7f2,BS=1MB,BU=R/W,BW=16bit */
-
-#define CONFIG_SYS_LATCH0_RESET		0xffff
-#define CONFIG_SYS_LATCH0_BOOT		0xffff
-#define CONFIG_SYS_LATCH1_RESET		0xffbf
-#define CONFIG_SYS_LATCH1_BOOT		0xffff
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/redwood.h b/include/configs/redwood.h
deleted file mode 100644
index 9f8f60c2c1..0000000000
--- a/include/configs/redwood.h
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
- * Configuration for AMCC 460SX Ref (redwood)
- *
- * (C) Copyright 2008
- * Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- *----------------------------------------------------------------------*/
-#define CONFIG_440			1	/* ... PPC460 family	*/
-#define CONFIG_460SX			1	/* ... PPC460 family	*/
-
-#define	CONFIG_SYS_TEXT_BASE	0xfffb0000
-
-/*-----------------------------------------------------------------------
- * Include common defines/options for all AMCC boards
- *----------------------------------------------------------------------*/
-#define CONFIG_HOSTNAME		redwood
-
-#include "amcc-common.h"
-
-#define CONFIG_SYS_CLK_FREQ	33333333	/* external freq to pll	*/
-
-/*-----------------------------------------------------------------------
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_FLASH_BASE		0xfff00000	/* start of FLASH	*/
-#define CONFIG_SYS_ISRAM_BASE		0x90000000	/* internal SRAM	*/
-
-#define CONFIG_SYS_PCI_BASE		0xd0000000	/* internal PCI regs	*/
-
-#define CONFIG_SYS_PCIE_MEMBASE	0x90000000	/* mapped PCIe memory	*/
-#define CONFIG_SYS_PCIE0_MEMBASE	0x90000000	/* mapped PCIe memory	*/
-#define CONFIG_SYS_PCIE1_MEMBASE	0xa0000000	/* mapped PCIe memory	*/
-#define CONFIG_SYS_PCIE_MEMSIZE	0x01000000
-
-#define CONFIG_SYS_PCIE0_XCFGBASE	0xb0000000
-#define CONFIG_SYS_PCIE1_XCFGBASE	0xb2000000
-#define CONFIG_SYS_PCIE2_XCFGBASE	0xb4000000
-#define CONFIG_SYS_PCIE0_CFGBASE	0xb6000000
-#define CONFIG_SYS_PCIE1_CFGBASE	0xb8000000
-#define CONFIG_SYS_PCIE2_CFGBASE	0xba000000
-
-/* PCIe mapped UTL registers */
-#define CONFIG_SYS_PCIE0_REGBASE   0xd0000000
-#define CONFIG_SYS_PCIE1_REGBASE   0xd0010000
-#define CONFIG_SYS_PCIE2_REGBASE   0xd0020000
-
-/* System RAM mapped to PCI space */
-#define CONFIG_PCI_SYS_MEM_BUS	CONFIG_SYS_SDRAM_BASE
-#define CONFIG_PCI_SYS_MEM_PHYS	CONFIG_SYS_SDRAM_BASE
-#define CONFIG_PCI_SYS_MEM_SIZE	(1024 * 1024 * 1024)
-
-#define CONFIG_SYS_FPGA_BASE		0xe2000000	/* epld			*/
-#define CONFIG_SYS_OPER_FLASH		0xe7000000	/* SRAM - OPER Flash	*/
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
-
-/*-----------------------------------------------------------------------
- * Initial RAM & stack pointer (placed in internal SRAM)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_TEMP_STACK_OCM	1
-#define CONFIG_SYS_OCM_DATA_ADDR	CONFIG_SYS_ISRAM_BASE
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_ISRAM_BASE	/* Initial RAM address	*/
-#define CONFIG_SYS_INIT_RAM_SIZE	0x2000		/* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
-
-/*-----------------------------------------------------------------------
- * DDR SDRAM
- *----------------------------------------------------------------------*/
-#define CONFIG_SPD_EEPROM	1	/* Use SPD EEPROM for setup	*/
-#define CONFIG_DDR_ECC		1	/* with ECC support		*/
-
-#define CONFIG_SYS_SPD_MAX_DIMMS	2
-
-/* SPD i2c spd addresses */
-#define SPD_EEPROM_ADDRESS     {IIC0_DIMM0_ADDR, IIC0_DIMM1_ADDR}
-#define IIC0_DIMM0_ADDR		       0x53
-#define IIC0_DIMM1_ADDR		       0x52
-
-/*-----------------------------------------------------------------------
- * I2C
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
-
-#define IIC0_BOOTPROM_ADDR	0x50
-#define IIC0_ALT_BOOTPROM_ADDR	0x54
-
-/* Don't probe these addrs */
-#define CONFIG_SYS_I2C_NOPROBES	{ {0, 0x50}, {0, 0x52}, {0, 0x53}, {0, 0x54} }
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2	/* Bytes of address		*/
-
-/*-----------------------------------------------------------------------
- * Environment
- *----------------------------------------------------------------------*/
-#undef	CONFIG_ENV_IS_IN_NVRAM		/* ... not in NVRAM		*/
-#define	CONFIG_ENV_IS_IN_FLASH	1	/* Environment uses flash	*/
-#undef	CONFIG_ENV_IS_IN_EEPROM		/* ... not in EEPROM		*/
-
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	CONFIG_AMCC_DEF_ENV						\
-	CONFIG_AMCC_DEF_ENV_POWERPC					\
-	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
-	"kernel_addr=fc000000\0"					\
-	"fdt_addr=fc1e0000\0"						\
-	"ramdisk_addr=fc200000\0"					\
-	""
-
-/*----------------------------------------------------------------------------+
-| Commands in addition to amcc-common.h
-+----------------------------------------------------------------------------*/
-#define CONFIG_CMD_SDRAM
-
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-
-#define	CONFIG_IBM_EMAC4_V4	1
-#define CONFIG_PHY_RESET	1	/* reset phy upon startup	*/
-#define CONFIG_PHY_RESET_DELAY	1000
-#define CONFIG_M88E1141_PHY	1	/* Enable phy */
-#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
-
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#define CONFIG_PHY_ADDR		0	/* PHY address, See schematics	*/
-#define CONFIG_PHY1_ADDR	1	/* PHY address, See schematics	*/
-
-#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-/*-----------------------------------------------------------------------
- * FLASH related
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_FLASH_CFI			/* The flash is CFI compatible	*/
-#define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/
-#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1	/* Use AMD (Spansion) reset cmd */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	3	/* number of banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	256	/* sectors per device		*/
-
-#undef	CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE	0x10000	/* size of one complete sector	*/
-#define CONFIG_ENV_ADDR		0xfffa0000
-#define CONFIG_ENV_SIZE		0x10000	/* Size of Environment vars	*/
-#endif /* CONFIG_ENV_IS_IN_FLASH */
-
-/*---------------------------------------------------------------------------*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h
deleted file mode 100644
index 7a120ed5a6..0000000000
--- a/include/configs/sequoia.h
+++ /dev/null
@@ -1,396 +0,0 @@
-/*
- * (C) Copyright 2006-2008
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2006
- * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
- * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * sequoia.h - configuration for Sequoia & Rainier boards
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-/* This config file is used for Sequoia (440EPx) and Rainier (440GRx)	*/
-#ifndef CONFIG_RAINIER
-#define CONFIG_440EPX		1	/* Specific PPC440EPx		*/
-#define CONFIG_HOSTNAME		sequoia
-#else
-#define CONFIG_440GRX		1	/* Specific PPC440GRx		*/
-#define CONFIG_HOSTNAME		rainier
-#endif
-#define CONFIG_440		1	/* ... PPC440 family		*/
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE	0xFFF80000
-#endif
-
-/*
- * Include common defines/options for all AMCC eval boards
- */
-#include "amcc-common.h"
-
-/* Detect Sequoia PLL input clock automatically via CPLD bit		*/
-#define CONFIG_SYS_CLK_FREQ    ((in8(CONFIG_SYS_BCSR_BASE + 3) & 0x80) ? \
-				33333333 : 33000000)
-
-/*
- * Define this if you want support for video console with radeon 9200 pci card
- * Also set CONFIG_SYS_TEXT_BASE to 0xFFF80000 in board/amcc/sequoia/config.mk in this case
- */
-
-#ifdef CONFIG_VIDEO
-/*
- * 44x dcache supported is working now on sequoia, but we don't enable
- * it yet since it needs further testing
- */
-#define CONFIG_4xx_DCACHE		/* enable dcache		*/
-#endif
-
-#define CONFIG_MISC_INIT_R	1	/* Call misc_init_r		*/
-
-/*
- * Base addresses -- Note these are effective addresses where the actual
- * resources get mapped (not physical addresses).
- */
-#define CONFIG_SYS_TLB_FOR_BOOT_FLASH	0x0003
-#define CONFIG_SYS_BOOT_BASE_ADDR	0xf0000000
-#define CONFIG_SYS_FLASH_BASE		0xfc000000	/* start of FLASH	*/
-#define CONFIG_SYS_NAND_ADDR		0xd0000000	/* NAND Flash		*/
-#define CONFIG_SYS_OCM_BASE		0xe0010000	/* ocm			*/
-#define CONFIG_SYS_OCM_DATA_ADDR	CONFIG_SYS_OCM_BASE
-#define CONFIG_SYS_PCI_BASE		0xe0000000	/* Internal PCI regs	*/
-#define CONFIG_SYS_PCI_MEMBASE		0x80000000	/* mapped pci memory	*/
-#define CONFIG_SYS_PCI_MEMBASE1	CONFIG_SYS_PCI_MEMBASE  + 0x10000000
-#define CONFIG_SYS_PCI_MEMBASE2	CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
-#define CONFIG_SYS_PCI_MEMBASE3	CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
-
-#define CONFIG_SYS_USB2D0_BASE		0xe0000100
-#define CONFIG_SYS_USB_DEVICE		0xe0000000
-#define CONFIG_SYS_USB_HOST		0xe0000400
-#define CONFIG_SYS_BCSR_BASE		0xc0000000
-
-/*
- * Initial RAM & stack pointer
- */
-/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache	*/
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_BASE	/* OCM			*/
-#define CONFIG_SYS_INIT_RAM_SIZE	(4 << 10)
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
-#define CONFIG_SYS_EXT_SERIAL_CLOCK	11059200	/* ext. 11.059MHz clk	*/
-
-/*
- * Environment
- */
-#if defined(CONFIG_SYS_RAMBOOT)
-#define CONFIG_ENV_IS_NOWHERE		/* Store env in memory only	*/
-#define CONFIG_ENV_SIZE		(8 << 10)
-#else
-#define CONFIG_ENV_IS_IN_FLASH		/* use FLASH for environ vars	*/
-#endif
-
-#if defined(CONFIG_CMD_FLASH)
-/*
- * FLASH related
- */
-#define CONFIG_SYS_FLASH_CFI			/* The flash is CFI compatible	*/
-#define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/
-
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks	      */
-#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip  */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)    */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)    */
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)   */
-#define CONFIG_SYS_FLASH_PROTECTION	1	/* use hardware flash protection      */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO	      /* print 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash      */
-#endif /* CONFIG_CMD_FLASH */
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE	0x20000	/* size of one complete sector	      */
-#define CONFIG_ENV_ADDR		((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
-#define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector   */
-
-/* Address and size of Redundant Environment Sector	*/
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
-#endif
-
-/*
- * DDR SDRAM
- */
-#define CONFIG_SYS_MBYTES_SDRAM        (256)	/* 256MB			*/
-#if !defined(CONFIG_SYS_RAMBOOT)
-#define CONFIG_DDR_DATA_EYE		/* use DDR2 optimization	*/
-#endif
-#define CONFIG_SYS_MEM_TOP_HIDE	(4 << 10) /* don't use last 4kbytes	*/
-					/* 440EPx errata CHIP 11	*/
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR	(0xa8>>1)
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-/* I2C bootstrap EEPROM */
-#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR	0x52
-#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET	0
-#define CONFIG_4xx_CONFIG_BLOCKSIZE		16
-
-/*
- * Default environment variables
- */
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	CONFIG_AMCC_DEF_ENV						\
-	CONFIG_AMCC_DEF_ENV_POWERPC					\
-	CONFIG_AMCC_DEF_ENV_PPC_OLD					\
-	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
-	"kernel_addr=FC000000\0"					\
-	"ramdisk_addr=FC180000\0"					\
-	""
-
-#define CONFIG_M88E1111_PHY	1
-#define	CONFIG_IBM_EMAC4_V4	1
-#define CONFIG_PHY_ADDR		0	/* PHY address, See schematics	*/
-
-#define CONFIG_PHY_RESET        1	/* reset phy upon startup	*/
-#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
-
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"	*/
-#define CONFIG_PHY1_ADDR	1
-
-/* USB */
-#ifdef CONFIG_440EPX
-#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_USB_EHCI_PPC4XX
-#define CONFIG_SYS_PPC4XX_USB_ADDR	0xe0000300
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_EHCI_MMIO_BIG_ENDIAN
-#define CONFIG_EHCI_DESC_BIG_ENDIAN
-#else /* CONFIG_USB_EHCI_HCD */
-#define CONFIG_USB_OHCI_NEW
-#define CONFIG_SYS_OHCI_BE_CONTROLLER
-
-#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
-#define CONFIG_SYS_USB_OHCI_CPU_INIT	1
-#define CONFIG_SYS_USB_OHCI_REGS_BASE	CONFIG_SYS_USB_HOST
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"ppc440"
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
-#endif
-
-/* Comment this out to enable USB 1.1 device */
-#define USB_2_0_DEVICE
-
-#endif /* CONFIG_440EPX */
-
-/* Partitions */
-
-/*
- * Commands additional to the ones defined in amcc-common.h
- */
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_SDRAM
-
-#ifdef CONFIG_440EPX
-#endif
-
-#ifndef CONFIG_RAINIER
-#define CONFIG_SYS_POST_FPU_ON		CONFIG_SYS_POST_FPU
-#else
-#define CONFIG_SYS_POST_FPU_ON		0
-#endif
-
-/*
- * Don't run the memory POST on the NAND-booting version. It will
- * overwrite part of the U-Boot image which is already loaded from NAND
- * to SDRAM.
- */
-#if defined(CONFIG_SYS_RAMBOOT)
-#define CONFIG_SYS_POST_MEMORY_ON	0
-#else
-#define CONFIG_SYS_POST_MEMORY_ON	CONFIG_SYS_POST_MEMORY
-#endif
-
-/* POST support */
-#define CONFIG_POST		(CONFIG_SYS_POST_CACHE	   | \
-				 CONFIG_SYS_POST_CPU	   | \
-				 CONFIG_SYS_POST_ETHER	   | \
-				 CONFIG_SYS_POST_FPU_ON    | \
-				 CONFIG_SYS_POST_I2C	   | \
-				 CONFIG_SYS_POST_MEMORY_ON | \
-				 CONFIG_SYS_POST_SPR	   | \
-				 CONFIG_SYS_POST_UART)
-
-#define CONFIG_LOGBUFFER
-#define CONFIG_SYS_POST_CACHE_ADDR	0x7fff0000	/* free virtual address     */
-
-#define CONFIG_SUPPORT_VFAT
-
-/*
- * PCI stuff
- */
-/* General PCI */
-#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
-#define CONFIG_SYS_PCI_CACHE_LINE_SIZE	0	/* to avoid problems with PNP	*/
-#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup	*/
-#define CONFIG_SYS_PCI_TARGBASE	0x80000000	/* PCIaddr mapped to	*/
-						/*   CONFIG_SYS_PCI_MEMBASE	*/
-/* Board-specific PCI */
-#define CONFIG_SYS_PCI_TARGET_INIT
-#define CONFIG_SYS_PCI_MASTER_INIT
-#define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC				*/
-#define CONFIG_SYS_PCI_SUBSYS_ID       0xcafe	/* Whatever			*/
-
-/*
- * External Bus Controller (EBC) Setup
- */
-
-/*
- * On Sequoia CS0 and CS3 are switched when configuring for NAND booting
- */
-#if !defined(CONFIG_SYS_RAMBOOT)
-#define CONFIG_SYS_NAND_CS		3	/* NAND chip connected to CSx	*/
-/* Memory Bank 0 (NOR-FLASH) initialization				*/
-#define CONFIG_SYS_EBC_PB0AP		0x03017200
-#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_FLASH_BASE | 0xda000)
-
-/* Memory Bank 3 (NAND-FLASH) initialization				*/
-#define CONFIG_SYS_EBC_PB3AP		0x018003c0
-#define CONFIG_SYS_EBC_PB3CR		(CONFIG_SYS_NAND_ADDR | 0x1c000)
-#else
-#define CONFIG_SYS_NAND_CS		0	/* NAND chip connected to CSx	*/
-/* Memory Bank 3 (NOR-FLASH) initialization				*/
-#define CONFIG_SYS_EBC_PB3AP		0x03017200
-#define CONFIG_SYS_EBC_PB3CR		(CONFIG_SYS_FLASH_BASE | 0xda000)
-
-/* Memory Bank 0 (NAND-FLASH) initialization				*/
-#define CONFIG_SYS_EBC_PB0AP		0x018003c0
-#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_NAND_ADDR | 0x1c000)
-#endif
-
-/* Memory Bank 2 (CPLD) initialization					*/
-#define CONFIG_SYS_EBC_PB2AP		0x24814580
-#define CONFIG_SYS_EBC_PB2CR		(CONFIG_SYS_BCSR_BASE | 0x38000)
-
-#define CONFIG_SYS_BCSR5_PCI66EN	0x80
-
-/*
- * NAND FLASH
- */
-#define CONFIG_SYS_MAX_NAND_DEVICE	1
-#define CONFIG_SYS_NAND_BASE		(CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
-#define CONFIG_SYS_NAND_SELECT_DEVICE  1	/* nand driver supports mutipl. chips */
-
-/*
- * PPC440 GPIO Configuration
- */
-/* test-only: take GPIO init from pcs440ep ???? in config file */
-#define CONFIG_SYS_4xx_GPIO_TABLE { /*	  Out		  GPIO	Alternate1	Alternate2	Alternate3 */ \
-{											\
-/* GPIO Core 0 */									\
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0	EBC_ADDR(7)	DMA_REQ(2)	*/	\
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1	EBC_ADDR(6)	DMA_ACK(2)	*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO2	EBC_ADDR(5)	DMA_EOT/TC(2)	*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO3	EBC_ADDR(4)	DMA_REQ(3)	*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO4	EBC_ADDR(3)	DMA_ACK(3)	*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO5	EBC_ADDR(2)	DMA_EOT/TC(3)	*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO6	EBC_CS_N(1)			*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7	EBC_CS_N(2)			*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8	EBC_CS_N(3)			*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9	EBC_CS_N(4)			*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5)			*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR			*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO12				*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO13				*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO14				*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO15				*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO16 GMCTxD(4)			*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO17 GMCTxD(5)			*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO18 GMCTxD(6)			*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO19 GMCTxD(7)			*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO20 RejectPkt0			*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO21 RejectPkt1			*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO22				*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO23 SCPD0				*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO24 GMCTxD(2)			*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO25 GMCTxD(3)			*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26				*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ	USB2D_RXERROR	*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO28		USB2D_TXVALID	*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO29 EBC_EXT_HDLA	USB2D_PAD_SUSPNDM */	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO30 EBC_EXT_ACK	USB2D_XCVRSELECT*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO31 EBC_EXR_BUSREQ	USB2D_TERMSELECT*/	\
-},											\
-{											\
-/* GPIO Core 1 */									\
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO32 USB2D_OPMODE0	EBC_DATA(2)	*/	\
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO33 USB2D_OPMODE1	EBC_DATA(3)	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO34 UART0_8PIN_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO36 UART0_CTS_N	EBC_DATA(0)	UART3_SIN*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO37 UART0_RTS_N	EBC_DATA(1)	UART3_SOUT*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_8PIN_DTR_N UART1_SOUT	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_8PIN_RI_N UART1_SIN	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0)			*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1)			*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2)			*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3)			*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4)	DMA_ACK(1)	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6)	DMA_EOT/TC(1)	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7)	DMA_REQ(0)	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8)	DMA_ACK(0)	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9)	DMA_EOT/TC(0)	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63  Unselect via TraceSelect Bit	*/	\
-}											\
-}
-
-#ifdef CONFIG_VIDEO
-#define CONFIG_BIOSEMU			/* x86 bios emulator for vga bios */
-#define CONFIG_ATI_RADEON_FB		/* use radeon framebuffer driver */
-#define VIDEO_IO_OFFSET			0xe8000000
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS		VIDEO_IO_OFFSET
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_SPLASH_SCREEN
-#endif
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/t3corp.h b/include/configs/t3corp.h
deleted file mode 100644
index ed5aaa2a63..0000000000
--- a/include/configs/t3corp.h
+++ /dev/null
@@ -1,531 +0,0 @@
-/*
- * (C) Copyright 2010
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * t3corp.h - configuration for T3CORP (460GT)
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_460GT		1	/* Specific PPC460GT	*/
-#define CONFIG_440		1
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE	0xFFFA0000
-#endif
-
-#define CONFIG_HOSTNAME		t3corp
-
-/*
- * Include common defines/options for all AMCC/APM eval boards
- */
-#include "amcc-common.h"
-
-#define CONFIG_SYS_CLK_FREQ	66666667	/* external freq to pll	*/
-
-#define CONFIG_BOARD_EARLY_INIT_R	1	/* Call board_early_init_r */
-#define CONFIG_MISC_INIT_R		1	/* Call misc_init_r */
-#define CONFIG_BOARD_TYPES		1	/* support board types */
-#define CFG_ALT_MEMTEST
-
-/*
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- */
-#define CONFIG_SYS_PCI_MEMBASE		0x80000000	/* mapped PCI memory */
-#define CONFIG_SYS_PCI_BASE		0xd0000000	/* internal PCI regs */
-#define CONFIG_SYS_PCI_TARGBASE	CONFIG_SYS_PCI_MEMBASE
-
-#define CONFIG_SYS_PCIE_MEMBASE		0xb0000000	/* mapped PCIe mem */
-#define CONFIG_SYS_PCIE_MEMSIZE		0x08000000	/* incr for PCIe */
-#define CONFIG_SYS_PCIE_BASE		0xc4000000	/* PCIe UTL regs */
-
-#define CONFIG_SYS_PCIE0_CFGBASE	0xc0000000
-#define CONFIG_SYS_PCIE1_CFGBASE	0xc1000000
-#define CONFIG_SYS_PCIE0_XCFGBASE	0xc3000000
-#define CONFIG_SYS_PCIE1_XCFGBASE	0xc3001000
-
-#define	CONFIG_SYS_PCIE0_UTLBASE	0xc08010000ULL	/* 36bit phys addr */
-
-/* base address of inbound PCIe window */
-#define CONFIG_SYS_PCIE_INBOUND_BASE	0x000000000ULL	/* 36bit phys addr */
-
-/* EBC stuff */
-#define CONFIG_SYS_FLASH_BASE		0xFC000000	/* later mapped here */
-#define CONFIG_SYS_FLASH_SIZE		(64 << 20)
-
-#define CONFIG_SYS_FPGA1_BASE		0xe0000000
-#define CONFIG_SYS_FPGA2_BASE		0xe2000000
-#define CONFIG_SYS_FPGA3_BASE		0xe4000000
-
-#define CONFIG_SYS_BOOT_BASE_ADDR	0xFF000000	/* EBC Boot Space */
-#define CONFIG_SYS_FLASH_BASE_PHYS_H	0x4
-#define CONFIG_SYS_FLASH_BASE_PHYS_L	0xCC000000
-#define CONFIG_SYS_FLASH_BASE_PHYS \
-	(((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) \
-	| (u64)CONFIG_SYS_FLASH_BASE_PHYS_L)
-
-#define CONFIG_SYS_OCM_BASE		0xE7000000	/* OCM: 64k */
-#define CONFIG_SYS_SRAM_BASE		0xE8000000	/* SRAM: 256k */
-#define CONFIG_SYS_SRAM_SIZE		(256 << 10)
-#define CONFIG_SYS_LOCAL_CONF_REGS	0xEF000000
-
-/*
- * Initial RAM & stack pointer (placed in OCM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_BASE	/* OCM */
-#define CONFIG_SYS_INIT_RAM_SIZE	(4 << 10)
-#define CONFIG_SYS_GBL_DATA_OFFSET \
-	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
-
-/*
- * Environment
- */
-/*
- * Define here the location of the environment variables (flash).
- */
-#define	CONFIG_ENV_IS_IN_FLASH		/* use flash for environment vars */
-
-/*
- * Flash related
- */
-#define CONFIG_SYS_FLASH_CFI		/* The flash is CFI compatible	*/
-#define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/
-#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
-#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
-#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* use status poll method	*/
-#define CONFIG_SYS_FLASH_PROTECTION	/* use hardware flash protection */
-
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE, \
-			(CONFIG_SYS_FPGA1_BASE + 0x01000000) }
-#define CONFIG_SYS_CFI_FLASH_CONFIG_REGS { 0xffff,	/* don't set	*/ \
-			0xbddf }		/* set async read mode	*/
-#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max num of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max num of sectors p. chip*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase/ms*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write/ms*/
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	/* buff'd writes (20x faster)*/
-#define CONFIG_SYS_FLASH_EMPTY_INFO	/* 'E' for empty sector on flinfo */
-
-#define CONFIG_ENV_SECT_SIZE		0x20000	/* sector size */
-#define CONFIG_ENV_ADDR			(CONFIG_SYS_MONITOR_BASE - \
-					 CONFIG_ENV_SECT_SIZE)
-#define	CONFIG_ENV_SIZE			0x4000	/* env sector size */
-
-/* Address and size of Redundant Environment Sector	*/
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
-
-/*
- * DDR2 SDRAM
- */
-#define CONFIG_SYS_MBYTES_SDRAM		256
-#define CONFIG_DDR_ECC
-#define CONFIG_AUTOCALIB	"silent\0"	/* default is non-verbose    */
-#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION	/* IBM DDR autocalibration   */
-#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION	/* dynamic DDR autocal debug */
-#undef CONFIG_PPC4xx_DDR_METHOD_A
-#define CONFIG_DDR_RFDC_FIXED		0x000001D7 /* optimal value */
-
-/* DDR1/2 SDRAM Device Control Register Data Values */
-/* Memory Queue */
-#define CONFIG_SYS_SDRAM_R0BAS		(SDRAM_RXBAS_SDBA_ENCODE(0) | \
-					 SDRAM_RXBAS_SDSZ_256)
-#define CONFIG_SYS_SDRAM_R1BAS		0x00000000
-#define CONFIG_SYS_SDRAM_R2BAS		0x00000000
-#define CONFIG_SYS_SDRAM_R3BAS		0x00000000
-#define CONFIG_SYS_SDRAM_PLBADDULL	0x00000000
-#define CONFIG_SYS_SDRAM_PLBADDUHB	0x00000008
-#define CONFIG_SYS_SDRAM_CONF1LL	0x80001C00
-#define CONFIG_SYS_SDRAM_CONF1HB	0x80001C80
-#define CONFIG_SYS_SDRAM_CONFPATHB	0x10a68000
-
-#define CAS_LATENCY			JEDEC_MA_MR_CL_DDR2_5_0_CLK
-
-/* DDR1/2 SDRAM Device Control Register Data Values */
-#define CONFIG_SYS_SDRAM0_MB0CF		(SDRAM_RXBAS_SDAM_MODE7		| \
-					 SDRAM_RXBAS_SDBE_ENABLE)
-#define CONFIG_SYS_SDRAM0_MB1CF		SDRAM_RXBAS_SDBE_DISABLE
-#define CONFIG_SYS_SDRAM0_MB2CF		SDRAM_RXBAS_SDBE_DISABLE
-#define CONFIG_SYS_SDRAM0_MB3CF		SDRAM_RXBAS_SDBE_DISABLE
-#define CONFIG_SYS_SDRAM0_MCOPT1	(SDRAM_MCOPT1_MCHK_GEN		| \
-					 SDRAM_MCOPT1_PMU_OPEN		| \
-					 SDRAM_MCOPT1_DMWD_32		| \
-					 SDRAM_MCOPT1_8_BANKS		| \
-					 SDRAM_MCOPT1_DDR2_TYPE		| \
-					 SDRAM_MCOPT1_QDEP		| \
-					 SDRAM_MCOPT1_RWOO_DISABLED	| \
-					 SDRAM_MCOPT1_WOOO_DISABLED	| \
-					 SDRAM_MCOPT1_DREF_NORMAL)
-#define CONFIG_SYS_SDRAM0_MCOPT2	0x00000000
-#define CONFIG_SYS_SDRAM0_MODT0		SDRAM_MODT_EB0W_ENABLE
-#define CONFIG_SYS_SDRAM0_MODT1		0x00000000
-#define CONFIG_SYS_SDRAM0_MODT2		0x00000000
-#define CONFIG_SYS_SDRAM0_MODT3		0x00000000
-#define CONFIG_SYS_SDRAM0_CODT		(SDRAM_CODT_RK0R_ON		| \
-					 SDRAM_CODT_DQS_1_8_V_DDR2	| \
-					 SDRAM_CODT_IO_NMODE)
-#define CONFIG_SYS_SDRAM0_RTR		SDRAM_RTR_RINT_ENCODE(1560)
-#define CONFIG_SYS_SDRAM0_INITPLR0					\
-	(SDRAM_INITPLR_ENABLE						| \
-	 SDRAM_INITPLR_IMWT_ENCODE(80)					| \
-	 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_NOP))
-#define CONFIG_SYS_SDRAM0_INITPLR1					\
-	(SDRAM_INITPLR_ENABLE						| \
-	 SDRAM_INITPLR_IMWT_ENCODE(3)					| \
-	 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE)			| \
-	 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR)				| \
-	 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
-#define CONFIG_SYS_SDRAM0_INITPLR2					\
-	(SDRAM_INITPLR_ENABLE						| \
-	 SDRAM_INITPLR_IMWT_ENCODE(2)					| \
-	 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)			| \
-	 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR2)			| \
-	 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR2_TEMP_COMMERCIAL))
-#define CONFIG_SYS_SDRAM0_INITPLR3					\
-	(SDRAM_INITPLR_ENABLE						| \
-	 SDRAM_INITPLR_IMWT_ENCODE(2)					| \
-	 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)			| \
-	 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR3)			| \
-	 SDRAM_INITPLR_IMA_ENCODE(0))
-#define CONFIG_SYS_SDRAM0_INITPLR4					\
-	(SDRAM_INITPLR_ENABLE						| \
-	 SDRAM_INITPLR_IMWT_ENCODE(2)					| \
-	 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)			| \
-	 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR)				| \
-	 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_DQS_ENABLE		| \
-				  JEDEC_MA_EMR_RTT_150OHM))
-#define CONFIG_SYS_SDRAM0_INITPLR5					\
-	(SDRAM_INITPLR_ENABLE						| \
-	 SDRAM_INITPLR_IMWT_ENCODE(200)					| \
-	 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)			| \
-	 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR)				| \
-	 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC		| \
-				  CAS_LATENCY				| \
-				  JEDEC_MA_MR_BLEN_4			| \
-				  JEDEC_MA_MR_DLL_RESET))
-#define CONFIG_SYS_SDRAM0_INITPLR6					\
-	(SDRAM_INITPLR_ENABLE						| \
-	 SDRAM_INITPLR_IMWT_ENCODE(3)					| \
-	 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE)			| \
-	 SDRAM_INITPLR_IBA_ENCODE(0x0)					| \
-	 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
-#define CONFIG_SYS_SDRAM0_INITPLR7					\
-	(SDRAM_INITPLR_ENABLE						| \
-	 SDRAM_INITPLR_IMWT_ENCODE(26)					| \
-	 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
-#define CONFIG_SYS_SDRAM0_INITPLR8					\
-	(SDRAM_INITPLR_ENABLE						| \
-	 SDRAM_INITPLR_IMWT_ENCODE(26)					| \
-	 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
-#define CONFIG_SYS_SDRAM0_INITPLR9					\
-	(SDRAM_INITPLR_ENABLE						| \
-	 SDRAM_INITPLR_IMWT_ENCODE(26)					| \
-	 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
-#define CONFIG_SYS_SDRAM0_INITPLR10					\
-	(SDRAM_INITPLR_ENABLE						| \
-	 SDRAM_INITPLR_IMWT_ENCODE(26)					| \
-	 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
-#define CONFIG_SYS_SDRAM0_INITPLR11					\
-	(SDRAM_INITPLR_ENABLE						| \
-	 SDRAM_INITPLR_IMWT_ENCODE(2)					| \
-	 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)			| \
-	 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR)				| \
-	 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC		| \
-				  CAS_LATENCY				| \
-				  JEDEC_MA_MR_BLEN_4))
-#define CONFIG_SYS_SDRAM0_INITPLR12					\
-	(SDRAM_INITPLR_ENABLE						| \
-	 SDRAM_INITPLR_IMWT_ENCODE(2)					| \
-	 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)			| \
-	 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR)				| \
-	 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_ENTER		| \
-				  JEDEC_MA_EMR_RDQS_DISABLE		| \
-				  JEDEC_MA_EMR_DQS_ENABLE		| \
-				  JEDEC_MA_EMR_RTT_150OHM		| \
-				  JEDEC_MA_EMR_ODS_NORMAL))
-#define CONFIG_SYS_SDRAM0_INITPLR13					\
-	(SDRAM_INITPLR_ENABLE						| \
-	 SDRAM_INITPLR_IMWT_ENCODE(2)					| \
-	 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)			| \
-	 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR)				| \
-	 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_EXIT			| \
-				  JEDEC_MA_EMR_RDQS_DISABLE		| \
-				  JEDEC_MA_EMR_DQS_ENABLE		| \
-				  JEDEC_MA_EMR_RTT_150OHM		| \
-				  JEDEC_MA_EMR_ODS_NORMAL))
-#define CONFIG_SYS_SDRAM0_INITPLR14	SDRAM_INITPLR_DISABLE
-#define CONFIG_SYS_SDRAM0_INITPLR15	SDRAM_INITPLR_DISABLE
-#define CONFIG_SYS_SDRAM0_RQDC		(SDRAM_RQDC_RQDE_ENABLE		| \
-					 SDRAM_RQDC_RQFD_ENCODE(56))
-#define CONFIG_SYS_SDRAM0_RFDC		SDRAM_RFDC_RFFD_ENCODE(599)
-#define CONFIG_SYS_SDRAM0_RDCC		(SDRAM_RDCC_RDSS_T2)
-#define CONFIG_SYS_SDRAM0_DLCR		(SDRAM_DLCR_DCLM_AUTO		| \
-					 SDRAM_DLCR_DLCS_CONT_DONE	| \
-					 SDRAM_DLCR_DLCV_ENCODE(155))
-#define CONFIG_SYS_SDRAM0_CLKTR		SDRAM_CLKTR_CLKP_90_DEG_ADV
-#define CONFIG_SYS_SDRAM0_WRDTR		SDRAM_WRDTR_WTR_90_DEG_ADV
-#define CONFIG_SYS_SDRAM0_SDTR1		(SDRAM_SDTR1_LDOF_2_CLK		| \
-					 SDRAM_SDTR1_RTW_2_CLK		| \
-					 SDRAM_SDTR1_RTRO_1_CLK)
-#define CONFIG_SYS_SDRAM0_SDTR2		(SDRAM_SDTR2_RCD_3_CLK		| \
-					 SDRAM_SDTR2_WTR_2_CLK		| \
-					 SDRAM_SDTR2_XSNR_32_CLK	| \
-					 SDRAM_SDTR2_WPC_4_CLK		| \
-					 SDRAM_SDTR2_RPC_2_CLK		| \
-					 SDRAM_SDTR2_RP_3_CLK		| \
-					 SDRAM_SDTR2_RRD_2_CLK)
-#define CONFIG_SYS_SDRAM0_SDTR3		(SDRAM_SDTR3_RAS_ENCODE(8)	| \
-					 SDRAM_SDTR3_RC_ENCODE(11)	| \
-					 SDRAM_SDTR3_XCS		| \
-					 SDRAM_SDTR3_RFC_ENCODE(26))
-#define CONFIG_SYS_SDRAM0_MMODE		(SDRAM_MMODE_WR_DDR2_3_CYC	| \
-					 CAS_LATENCY			| \
-					 SDRAM_MMODE_BLEN_4)
-#define CONFIG_SYS_SDRAM0_MEMODE	(SDRAM_MEMODE_DQS_ENABLE	| \
-					 SDRAM_MEMODE_RTT_150OHM)
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0			400000
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR		(0xa8>>1)
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
-
-/* I2C bootstrap EEPROM */
-#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR	0x52
-#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET	0
-#define CONFIG_4xx_CONFIG_BLOCKSIZE		16
-
-/*
- * Ethernet
- */
-#define CONFIG_IBM_EMAC4_V4	1
-
-#define CONFIG_HAS_ETH0
-
-#define CONFIG_PHY_ADDR		1	/* PHY address, See schematics	*/
-#define CONFIG_M88E1111_PHY
-/* Disable fiber since fiber/copper auto-selection doesn't seem to work */
-#define CONFIG_M88E1111_DISABLE_FIBER
-
-#define CONFIG_PHY_RESET	1	/* reset phy upon startup	*/
-#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
-#define CONFIG_PHY_DYNAMIC_ANEG	1
-
-/*
- * Default environment variables
- */
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	CONFIG_AMCC_DEF_ENV						\
-	CONFIG_AMCC_DEF_ENV_POWERPC					\
-	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
-	"kernel_addr=fc000000\0"					\
-	"fdt_addr=fc1e0000\0"						\
-	"ramdisk_addr=fc200000\0"					\
-	"pciconfighost=1\0"						\
-	"pcie_mode=RP:RP\0"						\
-	"unlock=yes\0"							\
-	""
-
-/*
- * Commands additional to the ones defined in amcc-common.h
- */
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_SDRAM
-
-/*
- * PCI stuff
- */
-/* General PCI */
-#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
-#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup  */
-#define CONFIG_PCI_CONFIG_HOST_BRIDGE
-
-/* Board-specific PCI, no PCI support, only PCIe */
-#undef CONFIG_SYS_PCI_TARGET_INIT
-#undef CONFIG_SYS_PCI_MASTER_INIT
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014	/* IBM */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */
-
-/*
- * External Bus Controller (EBC) Setup
- */
-
-/*
- * T3CORP has 64MBytes of NOR flash (Spansion 29GL512), but the
- * boot EBC mapping only supports a maximum of 16MBytes
- * (4.ff00.0000 - 4.ffff.ffff).
- * To solve this problem, the flash has to get remapped to another
- * EBC address which accepts bigger regions:
- *
- * 0xfc00.0000 -> 4.cc00.0000
- */
-
-/* Memory Bank 0 (NOR-flash) */
-#define CONFIG_SYS_EBC_PB0AP	(EBC_BXAP_BME_DISABLED		|	\
-				 EBC_BXAP_TWT_ENCODE(16)	|	\
-				 EBC_BXAP_BCE_DISABLE		|	\
-				 EBC_BXAP_BCT_2TRANS		|	\
-				 EBC_BXAP_CSN_ENCODE(1)		|	\
-				 EBC_BXAP_OEN_ENCODE(1)		|	\
-				 EBC_BXAP_WBN_ENCODE(1)		|	\
-				 EBC_BXAP_WBF_ENCODE(1)		|	\
-				 EBC_BXAP_TH_ENCODE(7)		|	\
-				 EBC_BXAP_RE_DISABLED		|	\
-				 EBC_BXAP_SOR_DELAYED		|	\
-				 EBC_BXAP_BEM_WRITEONLY		|	\
-				 EBC_BXAP_PEN_DISABLED)
-#define CONFIG_SYS_EBC_PB0CR	(EBC_BXCR_BAS_ENCODE(CONFIG_SYS_BOOT_BASE_ADDR) | \
-				 EBC_BXCR_BS_16MB		|	\
-				 EBC_BXCR_BU_RW			|	\
-				 EBC_BXCR_BW_16BIT)
-
-/* Memory Bank 1 (FPGA 1) */
-#define CONFIG_SYS_EBC_PB1AP	(EBC_BXAP_BME_DISABLED		|	\
-				 EBC_BXAP_TWT_ENCODE(5)		|	\
-				 EBC_BXAP_CSN_ENCODE(0)		|	\
-				 EBC_BXAP_OEN_ENCODE(3)		|	\
-				 EBC_BXAP_WBN_ENCODE(0)		|	\
-				 EBC_BXAP_WBF_ENCODE(0)		|	\
-				 EBC_BXAP_TH_ENCODE(1)		|	\
-				 EBC_BXAP_RE_ENABLED		|	\
-				 EBC_BXAP_SOR_DELAYED		|	\
-				 EBC_BXAP_BEM_RW		|	\
-				 EBC_BXAP_PEN_DISABLED)
-#define CONFIG_SYS_EBC_PB1CR	(EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA1_BASE) | \
-				 EBC_BXCR_BS_32MB		|	\
-				 EBC_BXCR_BU_RW			|	\
-				 EBC_BXCR_BW_32BIT)
-
-/* Memory Bank 2 (FPGA 2) */
-#define CONFIG_SYS_EBC_PB2AP	(EBC_BXAP_BME_DISABLED		|	\
-				 EBC_BXAP_TWT_ENCODE(5)		|	\
-				 EBC_BXAP_CSN_ENCODE(0)		|	\
-				 EBC_BXAP_OEN_ENCODE(3)		|	\
-				 EBC_BXAP_WBN_ENCODE(0)		|	\
-				 EBC_BXAP_WBF_ENCODE(0)		|	\
-				 EBC_BXAP_TH_ENCODE(1)		|	\
-				 EBC_BXAP_RE_ENABLED		|	\
-				 EBC_BXAP_SOR_DELAYED		|	\
-				 EBC_BXAP_BEM_RW		|	\
-				 EBC_BXAP_PEN_DISABLED)
-#define CONFIG_SYS_EBC_PB2CR	(EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA2_BASE) | \
-				 EBC_BXCR_BS_16MB		|	\
-				 EBC_BXCR_BU_RW			|	\
-				 EBC_BXCR_BW_32BIT)
-
-/* Memory Bank 3 (FPGA 3) */
-#define CONFIG_SYS_EBC_PB3AP	(EBC_BXAP_BME_DISABLED		|	\
-				 EBC_BXAP_TWT_ENCODE(5)		|	\
-				 EBC_BXAP_CSN_ENCODE(0)		|	\
-				 EBC_BXAP_OEN_ENCODE(3)		|	\
-				 EBC_BXAP_WBN_ENCODE(0)		|	\
-				 EBC_BXAP_WBF_ENCODE(0)		|	\
-				 EBC_BXAP_TH_ENCODE(1)		|	\
-				 EBC_BXAP_RE_ENABLED		|	\
-				 EBC_BXAP_SOR_DELAYED		|	\
-				 EBC_BXAP_BEM_RW		|	\
-				 EBC_BXAP_PEN_DISABLED)
-#define CONFIG_SYS_EBC_PB3CR	(EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA3_BASE) | \
-				 EBC_BXCR_BS_16MB		|	\
-				 EBC_BXCR_BU_RW			|	\
-				 EBC_BXCR_BW_32BIT)
-
-/*
- * PPC4xx GPIO Configuration
- */
-
-#define CONFIG_SYS_4xx_GPIO_TABLE { /*		  GPIO	Alternate1	Alternate2	Alternate3 */ \
-{											\
-/* GPIO Core 0 */									\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0	GMC1TxD(0)	USB2HostD(0)	*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1	GMC1TxD(1)	USB2HostD(1)	*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2	GMC1TxD(2)	USB2HostD(2)	*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3	GMC1TxD(3)	USB2HostD(3)	*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4	GMC1TxD(4)	USB2HostD(4)	*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5	GMC1TxD(5)	USB2HostD(5)	*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6	GMC1TxD(6)	USB2HostD(6)	*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7	GMC1TxD(7)	USB2HostD(7)	*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8	GMC1RxD(0)	USB2OTGD(0)	*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9	GMC1RxD(1)	USB2OTGD(1)	*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2)	USB2OTGD(2)	*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3)	USB2OTGD(3)	*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4)	USB2OTGD(4)	*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5)	USB2OTGD(5)	*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6)	USB2OTGD(6)	*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7)	USB2OTGD(7)	*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMC1TxER	USB2HostStop	*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD		USB2HostNext	*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER	USB2HostDir	*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMC1TxEN	USB2OTGStop	*/	\
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS	USB2OTGNext	*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV	USB2OTGDir	*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY				*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN				*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN				*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE				*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE				*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0)				*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1)				*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2)				*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0	DMAReq2		IRQ(7)*/ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1	DMAAck2		IRQ(8)*/ \
-},											\
-{											\
-/* GPIO Core 1 */									\
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2	EOT2/TC2	IRQ(9)*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3	DMAReq3		IRQ(4)*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N	UART1_DSR_CTS_N	UART2_SOUT*/ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3	UART3_SIN*/ \
-{GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N	EOT3/TC3	UART3_SOUT*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N	UART1_SOUT	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N	UART1_SIN	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3)				*/	\
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1)				*/	\
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2)				*/	\
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3)		DMAReq1		IRQ(10)*/ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4)		DMAAck1		IRQ(11)*/ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5)		EOT/TC1		IRQ(12)*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5)	DMAReq0		IRQ(13)*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6)	DMAAck0		IRQ(14)*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7)	EOT/TC0		IRQ(15)*/ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63  Unselect via TraceSelect Bit	*/	\
-}											\
-}
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/walnut.h b/include/configs/walnut.h
deleted file mode 100644
index d2d1ce95bc..0000000000
--- a/include/configs/walnut.h
+++ /dev/null
@@ -1,207 +0,0 @@
-/*
- * (C) Copyright 2000-2005
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_WALNUT		1	/* ...on a WALNUT board		*/
-					/* ...or on a SYCAMORE board	*/
-
-#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
-
-/*
- * Include common defines/options for all AMCC eval boards
- */
-#define CONFIG_HOSTNAME		walnut
-#include "amcc-common.h"
-
-#define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll	*/
-
-/*
- * Default environment variables
- */
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	CONFIG_AMCC_DEF_ENV						\
-	CONFIG_AMCC_DEF_ENV_POWERPC					\
-	CONFIG_AMCC_DEF_ENV_PPC_OLD					\
-	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
-	"kernel_addr=fff80000\0"					\
-	"ramdisk_addr=fff80000\0"					\
-	""
-
-#define CONFIG_PHY_ADDR		1	/* PHY address			*/
-#define CONFIG_HAS_ETH0		1
-
-#define CONFIG_RTC_DS174x	1	/* use DS1743 RTC in Walnut	*/
-
-/*
- * Commands additional to the ones defined in amcc-common.h
- */
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_SDRAM
-
-#define CONFIG_SPD_EEPROM      1       /* use SPD EEPROM for setup    */
-
-/*
- * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
- * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
- * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
- * The Linux BASE_BAUD define should match this configuration.
- *    baseBaud = cpuClock/(uartDivisor*16)
- * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
- * set Linux BASE_BAUD to 403200.
- */
-#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
-#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* external serial clock */
-#undef	CONFIG_SYS_405_UART_ERRATA_59	       /* 405GP/CR Rev. D silicon */
-#define CONFIG_SYS_BASE_BAUD	    691200
-
-/*-----------------------------------------------------------------------
- * I2C stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR	(0xa8>>1)
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0		/* configure ar pci adapter	*/
-#define PCI_HOST_FORCE	1		/* configure as pci host	*/
-#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
-
-#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
-#define CONFIG_PCI_HOST PCI_HOST_FORCE	/* select pci host function	*/
-					/* resource configuration	*/
-#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup	*/
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */
-#define CONFIG_SYS_PCI_PTM1LA	0x00000000	/* point to sdram		*/
-#define CONFIG_SYS_PCI_PTM1MS	0x80000001	/* 2GB, enable hard-wired to 1	*/
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
-#define CONFIG_SYS_PCI_PTM2LA	0x00000000	/* disabled			*/
-#define CONFIG_SYS_PCI_PTM2MS	0x00000000	/* disabled			*/
-#define CONFIG_SYS_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- */
-#define CONFIG_SYS_FLASH_BASE		0xFFF80000
-
-/*
- * Define here the location of the environment variables (FLASH or NVRAM).
- * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
- *	 supported for backward compatibility.
- */
-#if 1
-#define CONFIG_ENV_IS_IN_FLASH	1	/* use FLASH for environment vars	*/
-#else
-#define CONFIG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define FLASH_BASE0_PRELIM	CONFIG_SYS_FLASH_BASE	/* FLASH bank #0		*/
-#define FLASH_BASE1_PRELIM	0		/* FLASH bank #1		*/
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-
-#define CONFIG_SYS_FLASH_ADDR0		0x5555
-#define CONFIG_SYS_FLASH_ADDR1		0x2aaa
-#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned char
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE	0x10000		/* size of one complete sector	*/
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
-
-/* Address and size of Redundant Environment Sector	*/
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
-#endif /* CONFIG_ENV_IS_IN_FLASH */
-
-/*-----------------------------------------------------------------------
- * NVRAM organization
- */
-#define CONFIG_SYS_NVRAM_BASE_ADDR	0xf0000000	/* NVRAM base address	*/
-#define CONFIG_SYS_NVRAM_SIZE		0x1ff8		/* NVRAM size	*/
-
-#ifdef CONFIG_ENV_IS_IN_NVRAM
-#define CONFIG_ENV_SIZE		0x1000		/* Size of Environment vars	*/
-#define CONFIG_ENV_ADDR		\
-	(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE)	/* Env	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (Flash Bank 0) initialization					*/
-#define CONFIG_SYS_EBC_PB0AP		0x9B015480
-#define CONFIG_SYS_EBC_PB0CR		0xFFF18000  /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit	*/
-
-#define CONFIG_SYS_EBC_PB1AP		0x02815480
-#define CONFIG_SYS_EBC_PB1CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
-
-#define CONFIG_SYS_EBC_PB2AP		0x04815A80
-#define CONFIG_SYS_EBC_PB2CR		0xF0118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit	*/
-
-#define CONFIG_SYS_EBC_PB3AP		0x01815280
-#define CONFIG_SYS_EBC_PB3CR		0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit	*/
-
-#define CONFIG_SYS_EBC_PB7AP		0x01815280
-#define CONFIG_SYS_EBC_PB7CR		0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit	*/
-
-/*-----------------------------------------------------------------------
- * External peripheral base address
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_KEY_REG_BASE_ADDR	0xF0100000
-#define CONFIG_SYS_IR_REG_BASE_ADDR	0xF0200000
-#define CONFIG_SYS_FPGA_REG_BASE_ADDR	0xF0300000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area
- */
-#define CONFIG_SYS_INIT_DCACHE_CS	4	/* use cs # 4 for data cache memory    */
-
-#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000  /* inside of SDRAM			   */
-#define CONFIG_SYS_INIT_RAM_SIZE	0x2000	/* Size of used area in RAM	       */
-#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Definitions for Serial Presence Detect EEPROM address
- * (to get SDRAM settings)
- */
-#define SPD_EEPROM_ADDRESS	0x50
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/xilinx-ppc405-generic.h b/include/configs/xilinx-ppc405-generic.h
deleted file mode 100644
index 6182b0e7cf..0000000000
--- a/include/configs/xilinx-ppc405-generic.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- *
- * (C) Copyright 2008
- * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
- * This work has been supported by: QTechnology http://qtec.com/
- *
- * (C) Copyright 2008
- * Georg Schardt <schardt@team-ctech.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef __CONFIG_GEN_H
-#define __CONFIG_GEN_H
-
-#include "../board/xilinx/ppc405-generic/xparameters.h"
-
-#define CONFIG_405		1
-#define CONFIG_XILINX_405	1
-
-/* sdram */
-#define CONFIG_SYS_SDRAM_SIZE_MB	256
-
-/* environment */
-#define CONFIG_ENV_IS_IN_FLASH		1
-#define CONFIG_ENV_SIZE			0x10000
-#define CONFIG_ENV_SECT_SIZE		0x10000
-#define CONFIG_SYS_ENV_OFFSET		0x3F0000
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE+CONFIG_SYS_ENV_OFFSET)
-#define CONFIG_ENV_OVERWRITE		1
-
-/*Misc*/
-#define CONFIG_PREBOOT		"echo U-Boot is up and running;"
-
-/*Flash*/
-#define CONFIG_SYS_FLASH_BASE		XPAR_FLASH_MEM0_BASEADDR
-#define CONFIG_SYS_FLASH_SIZE		(128*1024*1024)
-#define CONFIG_SYS_MAX_FLASH_SECT	1024
-#define CONFIG_SYS_FLASH_CFI		1
-#define CONFIG_FLASH_CFI_DRIVER		1
-#define MTDIDS_DEFAULT			"nor0=flash"
-#define MTDPARTS_DEFAULT		"mtdparts=flash:-(user)"
-
-#include <configs/xilinx-ppc.h>
-#endif			/* __CONFIG_H */
diff --git a/include/configs/xilinx-ppc440-generic.h b/include/configs/xilinx-ppc440-generic.h
deleted file mode 100644
index f2505a6cd2..0000000000
--- a/include/configs/xilinx-ppc440-generic.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * (C) Copyright 2008
- *  Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
- *  This work has been supported by: QTechnology  http://qtec.com/
- * SPDX-License-Identifier:	GPL-2.0+
-*/
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* CPU */
-#define CONFIG_440			1
-#define CONFIG_XILINX_440		1
-#define CONFIG_XILINX_PPC440_GENERIC	1
-#include "../board/xilinx/ppc440-generic/xparameters.h"
-
-/* Mem Map */
-#define CONFIG_SYS_SDRAM_SIZE_MB	256
-
-/* Env */
-#define	CONFIG_ENV_IS_IN_FLASH	1
-#define	CONFIG_ENV_SIZE		0x20000
-#define	CONFIG_ENV_SECT_SIZE	0x20000
-#define CONFIG_ENV_OFFSET	0x340000
-#define CONFIG_ENV_ADDR		(XPAR_FLASH_MEM0_BASEADDR+CONFIG_ENV_OFFSET)
-
-/* Misc */
-#define CONFIG_PREBOOT		"echo U-Boot is up and running;"
-
-/* Flash */
-#define	CONFIG_SYS_FLASH_SIZE		(128*1024*1024)
-#define	CONFIG_SYS_MAX_FLASH_SECT	1024
-#define MTDIDS_DEFAULT			"nor0=flash"
-#define MTDPARTS_DEFAULT		"mtdparts=flash:-(user)"
-
-/* Net */
-#ifdef XPAR_LLTEMAC_0_BASEADDR
-#define CONFIG_XILINX_LL_TEMAC
-#define CONFIG_MII
-#define CONFIG_PHYLIB
-#define CONFIG_PHY_MARVELL
-#define CONFIG_NET_RANDOM_ETHADDR
-#define CONFIG_LIB_RAND
-#endif
-
-/* Generic Configs */
-#include <configs/xilinx-ppc.h>
-
-#endif						/* __CONFIG_H */
diff --git a/include/configs/xpedite1000.h b/include/configs/xpedite1000.h
deleted file mode 100644
index 93afb2062f..0000000000
--- a/include/configs/xpedite1000.h
+++ /dev/null
@@ -1,308 +0,0 @@
-/*
- * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * config for XPedite1000 from XES Inc.
- * Ported from EBONY config by Travis B. Sawyer <tsawyer@sandburst.com>
- * (C) Copyright 2003 Sandburst Corporation
- * board/config_EBONY.h - configuration for AMCC 440GP Ref (Ebony)
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* High Level Configuration Options */
-#define CONFIG_XPEDITE1000	1
-#define CONFIG_SYS_BOARD_NAME	"XPedite1000"
-#define CONFIG_SYS_FORM_PMC	1
-#define CONFIG_440		1
-#define CONFIG_440GX		1		/* 440 GX */
-#define CONFIG_SYS_CLK_FREQ	33333333	/* external freq to pll */
-
-#define	CONFIG_SYS_TEXT_BASE	0xFFF80000
-
-/*
- * DDR config
- */
-#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for setup */
-#define SPD_EEPROM_ADDRESS	{0x54}	/* SPD i2c spd addresses */
-#define CONFIG_VERY_BIG_RAM	1
-
-/*
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_FLASH_BASE		0xff000000	/* start of FLASH */
-#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE	/* start of monitor */
-#define CONFIG_SYS_PCI_MEMBASE		0x80000000	/* mapped pci memory */
-#define CONFIG_SYS_ISRAM_BASE		0xc0000000	/* internal SRAM */
-#define CONFIG_SYS_PCI_BASE		0xd0000000	/* internal PCI regs */
-#define CONFIG_SYS_NVRAM_BASE_ADDR	(CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
-#define CONFIG_SYS_GPIO_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x00000700)
-
-/*
- * Diagnostics
- */
-#define CONFIG_SYS_ALT_MEMTEST
-#define CONFIG_SYS_MEMTEST_START	0x0400000
-#define CONFIG_SYS_MEMTEST_END		0x0C00000
-
-/* POST support */
-#define CONFIG_POST		(CONFIG_SYS_POST_RTC	| \
-				 CONFIG_SYS_POST_I2C)
-
-/*
- * LED support
- */
-#define USR_LED0	0x00000080
-#define USR_LED1	0x00000100
-#define USR_LED2	0x00000200
-#define USR_LED3	0x00000400
-
-#ifndef __ASSEMBLY__
-extern unsigned long in32(unsigned int);
-extern void out32(unsigned int, unsigned long);
-
-#define LED0_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED0))
-#define LED1_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED1))
-#define LED2_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED2))
-#define LED3_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED3))
-
-#define LED0_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED0))
-#define LED1_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED1))
-#define LED2_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED2))
-#define LED3_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED3))
-#endif
-
-/*
- * Use internal SRAM for initial stack
- */
-#define CONFIG_SYS_TEMP_STACK_OCM	1
-#define CONFIG_SYS_OCM_DATA_ADDR	CONFIG_SYS_ISRAM_BASE
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_ISRAM_BASE	/* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE		0x2000	/* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
-
-#define CONFIG_SYS_MONITOR_LEN	(512 * 1024)	/* Reserve 512 KB for Mon */
-#define CONFIG_SYS_MALLOC_LEN	(1024 * 1024)	/* Reserved for malloc */
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
-	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400}
-#define CONFIG_LOADS_ECHO		1	/* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
-
-/*
- * NOR flash configuration
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	3
-#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE, 0xf0000000, 0xf4000000 }
-#define CONFIG_SYS_MAX_FLASH_SECT	512	/* sectors per device */
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-#define CONFIG_SYS_FLASH_QUIET_TEST		/* MirrorBit flashes are optional */
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7f
-
-/* I2C EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
-
-/* I2C RTC: STMicro M41T00 */
-#define CONFIG_RTC_M41T11		1
-#define CONFIG_SYS_I2C_RTC_ADDR		0x68
-#define CONFIG_SYS_M41T11_BASE_YEAR	2000
-
-/*
- * PCI
- */
-/* General PCI */
-#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
-#define CONFIG_PCI_SCAN_SHOW			/* show pci devices on startup */
-#define CONFIG_SYS_PCI_TARGBASE	0x80000000	/* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
-
-/* Board-specific PCI */
-#define CONFIG_SYS_PCI_TARGET_INIT		/* let board init pci target */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014	/* IBM */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */
-#define CONFIG_SYS_PCI_FORCE_PCI_CONV		/* Force PCI Conventional Mode */
-
-/*
- * Networking options
- */
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
-#define CONFIG_MII		1	/* MII PHY management */
-#define CONFIG_PHY_RESET	1	/* reset phy upon startup */
-#define CONFIG_SYS_RX_ETH_BUFFER 32	/* Number of ethernet rx buffers & descriptors */
-#define CONFIG_ETHPRIME		"ppc_4xx_eth2"
-#define CONFIG_PHY_ADDR		4	/* PHY address phy0 not populated */
-#define CONFIG_PHY2_ADDR	4	/* PHY address phy2 */
-#define CONFIG_HAS_ETH2		1	/* add support for "eth2addr" */
-#define CONFIG_PHY3_ADDR	8	/* PHY address phy3 */
-#define CONFIG_HAS_ETH3		1	/* add support for "eth3addr" */
-
-/* BOOTP options */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command configuration
- */
-#define CONFIG_CMD_PCI
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory */
-#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
-#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
-#define CONFIG_CMDLINE_EDITING	1		/* Command-line editing */
-#define CONFIG_PANIC_HANG			/* do not reset board on panic */
-#define CONFIG_PREBOOT				/* enable preboot variable */
-#define CONFIG_INTEGRITY			/* support booting INTEGRITY OS */
-#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-/*
- * Environment Configuration
- */
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128k (one sector) for env */
-#define CONFIG_ENV_SIZE		0x8000
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - (256 * 1024))
-
-/*
- * Flash memory map:
- * fff80000 - ffffffff	U-Boot (512 KB)
- * fff40000 - fff7ffff	U-Boot Environment (256 KB)
- * fff00000 - fff3ffff	FDT (256KB)
- * ffc00000 - ffefffff	OS image (3MB)
- * ff000000 - ffbfffff	OS Use/Filesystem (12MB)
- */
-
-#define CONFIG_UBOOT_ENV_ADDR	__stringify(CONFIG_SYS_TEXT_BASE)
-#define CONFIG_FDT_ENV_ADDR	__stringify(0xfff00000)
-#define CONFIG_OS_ENV_ADDR	__stringify(0xffc00000)
-
-#define CONFIG_PROG_UBOOT						\
-	"$download_cmd $loadaddr $ubootfile; "				\
-	"if test $? -eq 0; then "					\
-		"protect off "CONFIG_UBOOT_ENV_ADDR" +80000; "		\
-		"erase "CONFIG_UBOOT_ENV_ADDR" +80000; "		\
-		"cp.w $loadaddr "CONFIG_UBOOT_ENV_ADDR" 40000; "	\
-		"protect on "CONFIG_UBOOT_ENV_ADDR" +80000; "		\
-		"cmp.b $loadaddr "CONFIG_UBOOT_ENV_ADDR" 80000; "	\
-		"if test $? -ne 0; then "				\
-			"echo PROGRAM FAILED; "				\
-		"else; "						\
-			"echo PROGRAM SUCCEEDED; "			\
-		"fi; "							\
-	"else; "							\
-		"echo DOWNLOAD FAILED; "				\
-	"fi;"
-
-#define CONFIG_BOOT_OS_NET						\
-	"$download_cmd $osaddr $osfile; "				\
-	"if test $? -eq 0; then "					\
-		"if test -n $fdtaddr; then "				\
-			"$download_cmd $fdtaddr $fdtfile; "		\
-			"if test $? -eq 0; then "			\
-				"bootm $osaddr - $fdtaddr; "		\
-			"else; "					\
-				"echo FDT DOWNLOAD FAILED; "		\
-			"fi; "						\
-		"else; "						\
-			"bootm $osaddr; "				\
-		"fi; "							\
-	"else; "							\
-		"echo OS DOWNLOAD FAILED; "				\
-	"fi;"
-
-#define CONFIG_PROG_OS							\
-	"$download_cmd $osaddr $osfile; "				\
-	"if test $? -eq 0; then "					\
-		"erase "CONFIG_OS_ENV_ADDR" +$filesize; "		\
-		"cp.b $osaddr "CONFIG_OS_ENV_ADDR" $filesize; "		\
-		"cmp.b $osaddr "CONFIG_OS_ENV_ADDR" $filesize; "	\
-		"if test $? -ne 0; then "				\
-			"echo OS PROGRAM FAILED; "			\
-		"else; "						\
-			"echo OS PROGRAM SUCCEEDED; "			\
-		"fi; "							\
-	"else; "							\
-		"echo OS DOWNLOAD FAILED; "				\
-	"fi;"
-
-#define CONFIG_PROG_FDT							\
-	"$download_cmd $fdtaddr $fdtfile; "				\
-	"if test $? -eq 0; then "					\
-		"erase "CONFIG_FDT_ENV_ADDR" +$filesize;"		\
-		"cp.b $fdtaddr "CONFIG_FDT_ENV_ADDR" $filesize; "	\
-		"cmp.b $fdtaddr "CONFIG_FDT_ENV_ADDR" $filesize; "	\
-		"if test $? -ne 0; then "				\
-			"echo FDT PROGRAM FAILED; "			\
-		"else; "						\
-			"echo FDT PROGRAM SUCCEEDED; "			\
-		"fi; "							\
-	"else; "							\
-		"echo FDT DOWNLOAD FAILED; "				\
-	"fi;"
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"autoload=yes\0"						\
-	"download_cmd=tftp\0"						\
-	"console_args=console=ttyS0,115200\0"				\
-	"root_args=root=/dev/nfs rw\0"					\
-	"misc_args=ip=on\0"						\
-	"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
-	"bootfile=/home/user/file\0"					\
-	"osfile=/home/user/board.uImage\0"				\
-	"fdtfile=/home/user/board.dtb\0"				\
-	"ubootfile=/home/user/u-boot.bin\0"				\
-	"fdtaddr=0x1e00000\0"						\
-	"osaddr=0x1000000\0"						\
-	"loadaddr=0x1000000\0"						\
-	"prog_uboot="CONFIG_PROG_UBOOT"\0"				\
-	"prog_os="CONFIG_PROG_OS"\0"					\
-	"prog_fdt="CONFIG_PROG_FDT"\0"					\
-	"bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0"		\
-	"bootcmd_flash=run set_bootargs; "				\
-		"bootm "CONFIG_OS_ENV_ADDR" - "CONFIG_FDT_ENV_ADDR"\0"	\
-	"bootcmd=run bootcmd_flash\0"
-#endif	/* __CONFIG_H */
diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h
deleted file mode 100644
index d9c09b80cd..0000000000
--- a/include/configs/yosemite.h
+++ /dev/null
@@ -1,216 +0,0 @@
-/*
- * (C) Copyright 2005-2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/************************************************************************
- * yosemite.h - configuration for Yosemite & Yellowstone boards
- ***********************************************************************/
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- *----------------------------------------------------------------------*/
-/* This config file is used for Yosemite (440EP) and Yellowstone (440GR)*/
-#ifndef CONFIG_YELLOWSTONE
-#define CONFIG_440EP		1	/* Specific PPC440EP support	*/
-#define CONFIG_HOSTNAME		yosemite
-#else
-#define CONFIG_440GR		1	/* Specific PPC440GR support	*/
-#define CONFIG_HOSTNAME		yellowstone
-#endif
-#define CONFIG_440		1	/* ... PPC440 family		*/
-#define CONFIG_SYS_CLK_FREQ	66666666    /* external freq to pll	*/
-
-#define	CONFIG_SYS_TEXT_BASE	0xFFF80000
-
-/*
- * Include common defines/options for all AMCC eval boards
- */
-#include "amcc-common.h"
-
-#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
-#define CONFIG_BOARD_RESET	1	/* call board_reset()		*/
-
-/*-----------------------------------------------------------------------
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_FLASH_BASE	        0xfc000000	    /* start of FLASH	*/
-#define CONFIG_SYS_PCI_MEMBASE	        0xa0000000	    /* mapped pci memory*/
-#define CONFIG_SYS_PCI_MEMBASE1        CONFIG_SYS_PCI_MEMBASE  + 0x10000000
-#define CONFIG_SYS_PCI_MEMBASE2        CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
-#define CONFIG_SYS_PCI_MEMBASE3        CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
-
-/*Don't change either of these*/
-#define CONFIG_SYS_PCI_BASE	        0xe0000000	    /* internal PCI regs*/
-/*Don't change either of these*/
-
-#define CONFIG_SYS_USB_DEVICE          0x50000000
-#define CONFIG_SYS_NVRAM_BASE_ADDR     0x80000000
-#define CONFIG_SYS_BCSR_BASE	        (CONFIG_SYS_NVRAM_BASE_ADDR | 0x2000)
-#define CONFIG_SYS_BOOT_BASE_ADDR      0xf0000000
-
-/*-----------------------------------------------------------------------
- * Initial RAM & stack pointer (placed in SDRAM)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_INIT_RAM_DCACHE	1		/* d-cache as init ram	*/
-#define CONFIG_SYS_INIT_RAM_ADDR	0x70000000		/* DCache       */
-#define CONFIG_SYS_INIT_RAM_SIZE	(4 << 10)
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Serial Port
- *----------------------------------------------------------------------*/
-#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
-#define CONFIG_SYS_EXT_SERIAL_CLOCK	11059200 /* use external 11.059MHz clk	*/
-
-/*-----------------------------------------------------------------------
- * Environment
- *----------------------------------------------------------------------*/
-/*
- * Define here the location of the environment variables (FLASH or EEPROM).
- * Note: DENX encourages to use redundant environment in FLASH.
- */
-#if 1
-#define CONFIG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
-#else
-#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * FLASH related
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_FLASH_CFI				/* The flash is CFI compatible	*/
-#define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver	*/
-#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1		/* AMD RESET for STM 29W320DB!	*/
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE	0x20000	/* size of one complete sector		*/
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
-#define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
-
-/* Address and size of Redundant Environment Sector	*/
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
-#endif /* CONFIG_ENV_IS_IN_FLASH */
-
-/*-----------------------------------------------------------------------
- * DDR SDRAM
- *----------------------------------------------------------------------*/
-#undef CONFIG_SPD_EEPROM	       /* Don't use SPD EEPROM for setup    */
-#define CONFIG_SYS_KBYTES_SDRAM        (128 * 1024)    /* 128MB		    */
-#define CONFIG_SYS_SDRAM_BANKS	        (2)
-
-/*-----------------------------------------------------------------------
- * I2C
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR	(0xa8>>1)
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-#ifdef CONFIG_ENV_IS_IN_EEPROM
-#define CONFIG_ENV_SIZE		0x200	    /* Size of Environment vars */
-#define CONFIG_ENV_OFFSET		0x0
-#endif /* CONFIG_ENV_IS_IN_EEPROM */
-
-/*
- * Default environment variables
- */
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	CONFIG_AMCC_DEF_ENV						\
-	CONFIG_AMCC_DEF_ENV_POWERPC					\
-	CONFIG_AMCC_DEF_ENV_PPC_OLD					\
-	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
-	"kernel_addr=fc000000\0"					\
-	"ramdisk_addr=fc180000\0"					\
-	""
-
-#define CONFIG_HAS_ETH0		1	/* add support for "ethaddr"	*/
-#define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"	*/
-#define CONFIG_PHY_ADDR		1	/* PHY address, See schematics	*/
-#define CONFIG_PHY1_ADDR        3
-
-/* Partitions */
-
-#ifdef CONFIG_440EP
-/* USB */
-#define CONFIG_USB_OHCI_NEW
-#define CONFIG_SYS_OHCI_BE_CONTROLLER
-
-#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
-#define CONFIG_SYS_USB_OHCI_CPU_INIT	1
-#define CONFIG_SYS_USB_OHCI_REGS_BASE	(CONFIG_SYS_PERIPHERAL_BASE | 0x1000)
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"ppc440"
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
-
-/* Comment this out to enable USB 1.1 device */
-#define USB_2_0_DEVICE
-
-#define CONFIG_SUPPORT_VFAT
-#endif /* CONFIG_440EP */
-
-#ifdef DEBUG
-#define CONFIG_PANIC_HANG
-#else
-#define CONFIG_HW_WATCHDOG			/* watchdog */
-#endif
-
-/*
- * Commands additional to the ones defined in amcc-common.h
- */
-#define CONFIG_CMD_PCI
-
-#ifdef CONFIG_440EP
-#endif
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-/* General PCI */
-#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
-#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
-#define CONFIG_SYS_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/
-
-/* Board-specific PCI */
-#define CONFIG_SYS_PCI_TARGET_INIT
-#define CONFIG_SYS_PCI_MASTER_INIT
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
-#define CONFIG_SYS_PCI_SUBSYS_ID       0xcafe	/* Whatever */
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_FLASH		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CPLD		0x80000000
-
-/* Memory Bank 0 (NOR-FLASH) initialization					*/
-#define CONFIG_SYS_EBC_PB0AP		0x03017300
-#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_FLASH | 0xda000)
-
-/* Memory Bank 2 (CPLD) initialization						*/
-#define CONFIG_SYS_EBC_PB2AP		0x04814500
-#define CONFIG_SYS_EBC_PB2CR		(CONFIG_SYS_CPLD | 0x18000)
-
-#define CONFIG_SYS_BCSR5_PCI66EN	0x80
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/yucca.h b/include/configs/yucca.h
deleted file mode 100644
index 183bfce2af..0000000000
--- a/include/configs/yucca.h
+++ /dev/null
@@ -1,410 +0,0 @@
-/*
- * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/************************************************************************
- * 1 january 2005	Alain Saurel <asaurel@amcc.com>
- * Adapted to current Das U-Boot source
- ***********************************************************************/
-/************************************************************************
- * yucca.h - configuration for AMCC 440SPe Ref (yucca)
- ***********************************************************************/
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- *----------------------------------------------------------------------*/
-#define CONFIG_440			1	/* ... PPC440 family	*/
-#define CONFIG_440SPE			1	/* Specifc SPe support	*/
-#define CONFIG_440SPE_REVA		1	/* Support old Rev A.	*/
-#define CONFIG_SYS_CLK_FREQ	33333333	/* external freq to pll	*/
-#define EXTCLK_33_33		33333333
-#define EXTCLK_66_66		66666666
-#define EXTCLK_50		50000000
-#define EXTCLK_83		83333333
-
-#define	CONFIG_SYS_TEXT_BASE	0xfffb0000
-
-/*
- * Include common defines/options for all AMCC eval boards
- */
-#define CONFIG_HOSTNAME		yucca
-#include "amcc-common.h"
-
-#define	CONFIG_MISC_INIT_F	1	/* Use misc_init_f()		*/
-#undef  CONFIG_SHOW_BOOT_PROGRESS
-#undef  CONFIG_STRESS
-
-/*-----------------------------------------------------------------------
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_FLASH_BASE		0xfff00000	/* start of FLASH	*/
-#define CONFIG_SYS_ISRAM_BASE		0x90000000	/* internal SRAM	*/
-
-#define CONFIG_SYS_PCI_MEMBASE		0x80000000	/* mapped PCI memory	*/
-#define CONFIG_SYS_PCI_BASE		0xd0000000	/* internal PCI regs	*/
-#define CONFIG_SYS_PCI_TARGBASE	CONFIG_SYS_PCI_MEMBASE
-
-#define CONFIG_SYS_PCIE_MEMBASE	0xb0000000	/* mapped PCIe memory	*/
-#define CONFIG_SYS_PCIE_MEMSIZE	0x08000000	/* smallest incr for PCIe port */
-#define CONFIG_SYS_PCIE_BASE		0xe0000000	/* PCIe UTL regs */
-
-#define CONFIG_SYS_PCIE0_CFGBASE	0xc0000000
-#define CONFIG_SYS_PCIE1_CFGBASE	0xc1000000
-#define CONFIG_SYS_PCIE2_CFGBASE	0xc2000000
-#define CONFIG_SYS_PCIE0_XCFGBASE	0xc3000000
-#define CONFIG_SYS_PCIE1_XCFGBASE	0xc3001000
-#define CONFIG_SYS_PCIE2_XCFGBASE	0xc3002000
-
-/* base address of inbound PCIe window */
-#define CONFIG_SYS_PCIE_INBOUND_BASE	0x0000000400000000ULL
-
-/* System RAM mapped to PCI space */
-#define CONFIG_PCI_SYS_MEM_BUS	CONFIG_SYS_SDRAM_BASE
-#define CONFIG_PCI_SYS_MEM_PHYS	CONFIG_SYS_SDRAM_BASE
-#define CONFIG_PCI_SYS_MEM_SIZE	(1024 * 1024 * 1024)
-
-#define CONFIG_SYS_FPGA_BASE		0xe2000000	/* epld			*/
-#define CONFIG_SYS_OPER_FLASH		0xe7000000	/* SRAM - OPER Flash	*/
-
-/* #define CONFIG_SYS_NVRAM_BASE_ADDR 0x08000000 */
-/*-----------------------------------------------------------------------
- * Initial RAM & stack pointer (placed in internal SRAM)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_TEMP_STACK_OCM	1
-#define CONFIG_SYS_OCM_DATA_ADDR	CONFIG_SYS_ISRAM_BASE
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_ISRAM_BASE	/* Initial RAM address	*/
-#define CONFIG_SYS_INIT_RAM_SIZE	0x2000		/* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
-
-/*-----------------------------------------------------------------------
- * Serial Port
- *----------------------------------------------------------------------*/
-#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
-
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK
-/* #define CONFIG_SYS_EXT_SERIAL_CLOCK	(1843200 * 6) */ /* Ext clk @ 11.059 MHz */
-
-/*-----------------------------------------------------------------------
- * DDR SDRAM
- *----------------------------------------------------------------------*/
-#define CONFIG_SPD_EEPROM	1	/* Use SPD EEPROM for setup	*/
-#define SPD_EEPROM_ADDRESS	{0x53, 0x52}	/* SPD i2c spd addresses*/
-#define CONFIG_DDR_ECC		1	/* with ECC support		*/
-
-/*-----------------------------------------------------------------------
- * I2C
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
-
-#define IIC0_BOOTPROM_ADDR	0x50
-#define IIC0_ALT_BOOTPROM_ADDR	0x54
-
-/* Don't probe these addrs */
-#define CONFIG_SYS_I2C_NOPROBES	{ {0, 0x50}, {0, 0x52}, {0, 0x53}, {0, 0x54} }
-
-/* #if defined(CONFIG_CMD_EEPROM) */
-/* #define CONFIG_SYS_I2C_EEPROM_ADDR	0x50 */	/* I2C boot EEPROM		*/
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2	/* Bytes of address		*/
-/* #endif */
-
-/*-----------------------------------------------------------------------
- * Environment
- *----------------------------------------------------------------------*/
-/* #define CONFIG_SYS_NVRAM_SIZE	(0x2000 - 8) */	/* NVRAM size(8k)- RTC regs */
-
-#undef  CONFIG_ENV_IS_IN_NVRAM		/* ... not in NVRAM		*/
-#define	CONFIG_ENV_IS_IN_FLASH	1	/* Environment uses flash	*/
-#undef	CONFIG_ENV_IS_IN_EEPROM		/* ... not in EEPROM		*/
-#define CONFIG_ENV_OVERWRITE	1
-
-/*
- * Default environment variables
- */
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	CONFIG_AMCC_DEF_ENV						\
-	CONFIG_AMCC_DEF_ENV_PPC						\
-	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
-	"kernel_addr=E7F10000\0"					\
-	"ramdisk_addr=E7F20000\0"					\
-	"pciconfighost=1\0"						\
-	"pcie_mode=RP:EP:EP\0"						\
-	""
-
-/*
- * Commands additional to the ones defined in amcc-common.h
- */
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_SDRAM
-
-#define	CONFIG_IBM_EMAC4_V4	1
-#define CONFIG_PHY_ADDR		1	/* PHY address, See schematics	*/
-#define CONFIG_HAS_ETH0
-#define CONFIG_PHY_RESET        1	/* reset phy upon startup	*/
-#define CONFIG_PHY_RESET_DELAY	1000
-#define CONFIG_CIS8201_PHY	1	/* Enable 'special' RGMII mode for Cicada phy */
-#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
-
-/*-----------------------------------------------------------------------
- * FLASH related
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MAX_FLASH_BANKS	3	/* number of banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	256	/* sectors per device		*/
-
-#undef	CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_ADDR0		0x5555
-#define CONFIG_SYS_FLASH_ADDR1		0x2aaa
-#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned char
-
-#define CONFIG_SYS_FLASH_2ND_16BIT_DEV	1	/* evb440SPe has 8 and 16bit device */
-#define CONFIG_SYS_FLASH_2ND_ADDR	0xe7c00000 /* evb440SPe has 8 and 16bit device*/
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE	0x10000	/* size of one complete sector	*/
-#define CONFIG_ENV_ADDR		0xfffa0000
-/* #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) */
-#define CONFIG_ENV_SIZE		0x10000	/* Size of Environment vars	*/
-#endif /* CONFIG_ENV_IS_IN_FLASH */
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-/* General PCI */
-#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
-#define CONFIG_PCI_SCAN_SHOW	1	/* show pci devices on startup	*/
-#define CONFIG_PCI_CONFIG_HOST_BRIDGE
-
-/* Board-specific PCI */
-#define CONFIG_SYS_PCI_TARGET_INIT		/* let board init pci target    */
-#undef	CONFIG_SYS_PCI_MASTER_INIT
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014	/* IBM				*/
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever			*/
-/* #define CONFIG_SYS_PCI_SUBSYS_ID	CONFIG_SYS_PCI_SUBSYS_DEVICEID */
-
-/*
- *  NETWORK Support (PCI):
- */
-/* Support for Intel 82557/82559/82559ER chips. */
-#define CONFIG_EEPRO100
-
-/* FB Divisor selection */
-#define FPGA_FB_DIV_6		6
-#define FPGA_FB_DIV_10		10
-#define FPGA_FB_DIV_12		12
-#define FPGA_FB_DIV_20		20
-
-/* VCO Divisor selection */
-#define	FPGA_VCO_DIV_4		4
-#define	FPGA_VCO_DIV_6		6
-#define	FPGA_VCO_DIV_8		8
-#define	FPGA_VCO_DIV_10		10
-
-/*----------------------------------------------------------------------------+
-| FPGA registers and bit definitions
-+----------------------------------------------------------------------------*/
-/* PowerPC 440SPe Board FPGA is reached with physical address 0x1 E2000000. */
-/* TLB initialization makes it correspond to logical address 0xE2000000. */
-/* => Done init_chip.s in bootlib */
-#define FPGA_REG_BASE_ADDR	0xE2000000
-#define FPGA_GPIO_BASE_ADDR	0xE2010000
-#define FPGA_INT_BASE_ADDR	0xE2020000
-
-/*----------------------------------------------------------------------------+
-| Display
-+----------------------------------------------------------------------------*/
-#define PPC440SPE_DISPLAY	FPGA_REG_BASE_ADDR
-
-#define PPC440SPE_DISPLAY_D8	(FPGA_REG_BASE_ADDR+0x06)
-#define PPC440SPE_DISPLAY_D4	(FPGA_REG_BASE_ADDR+0x04)
-#define PPC440SPE_DISPLAY_D2	(FPGA_REG_BASE_ADDR+0x02)
-#define PPC440SPE_DISPLAY_D1	(FPGA_REG_BASE_ADDR+0x00)
-/*define   WRITE_DISPLAY_DIGIT(n) IOREG8(FPGA_REG_BASE_ADDR + (2*n))*/
-/*#define   IOREG8(addr) *((volatile unsigned char *)(addr))*/
-
-/*----------------------------------------------------------------------------+
-| ethernet/reset/boot Register 1
-+----------------------------------------------------------------------------*/
-#define FPGA_REG10	(FPGA_REG_BASE_ADDR+0x10)
-
-#define FPGA_REG10_10MHZ_ENABLE		0x8000
-#define FPGA_REG10_100MHZ_ENABLE	0x4000
-#define FPGA_REG10_GIGABIT_ENABLE	0x2000
-#define FPGA_REG10_FULL_DUPLEX		0x1000	/* force Full Duplex*/
-#define FPGA_REG10_RESET_ETH		0x0800
-#define FPGA_REG10_AUTO_NEG_DIS		0x0400
-#define FPGA_REG10_INTP_ETH		0x0200
-
-#define FPGA_REG10_RESET_HISR		0x0080
-#define FPGA_REG10_ENABLE_DISPLAY	0x0040
-#define FPGA_REG10_RESET_SDRAM		0x0020
-#define FPGA_REG10_OPER_BOOT		0x0010
-#define FPGA_REG10_SRAM_BOOT		0x0008
-#define FPGA_REG10_SMALL_BOOT		0x0004
-#define FPGA_REG10_FORCE_COLA		0x0002
-#define FPGA_REG10_COLA_MANUAL		0x0001
-
-#define FPGA_REG10_SDRAM_ENABLE		0x0020
-
-#define FPGA_REG10_ENET_ENCODE2(n) ((((unsigned long)(n))&0x0F)<<4) /*from ocotea ?*/
-#define FPGA_REG10_ENET_DECODE2(n) ((((unsigned long)(n))>>4)&0x0F) /*from ocotea ?*/
-
-/*----------------------------------------------------------------------------+
-| MUX control
-+----------------------------------------------------------------------------*/
-#define FPGA_REG12	(FPGA_REG_BASE_ADDR+0x12)
-
-#define FPGA_REG12_EBC_CTL		0x8000
-#define FPGA_REG12_UART1_CTS_RTS	0x4000
-#define FPGA_REG12_UART0_RX_ENABLE	0x2000
-#define FPGA_REG12_UART1_RX_ENABLE	0x1000
-#define FPGA_REG12_UART2_RX_ENABLE	0x0800
-#define FPGA_REG12_EBC_OUT_ENABLE	0x0400
-#define FPGA_REG12_GPIO0_OUT_ENABLE	0x0200
-#define FPGA_REG12_GPIO1_OUT_ENABLE	0x0100
-#define FPGA_REG12_GPIO_SELECT		0x0010
-#define FPGA_REG12_GPIO_CHREG		0x0008
-#define FPGA_REG12_GPIO_CLK_CHREG	0x0004
-#define FPGA_REG12_GPIO_OETRI		0x0002
-#define FPGA_REG12_EBC_ERROR		0x0001
-
-/*----------------------------------------------------------------------------+
-| PCI Clock control
-+----------------------------------------------------------------------------*/
-#define FPGA_REG16	(FPGA_REG_BASE_ADDR+0x16)
-
-#define FPGA_REG16_PCI_CLK_CTL0		0x8000
-#define FPGA_REG16_PCI_CLK_CTL1		0x4000
-#define FPGA_REG16_PCI_CLK_CTL2		0x2000
-#define FPGA_REG16_PCI_CLK_CTL3		0x1000
-#define FPGA_REG16_PCI_CLK_CTL4		0x0800
-#define FPGA_REG16_PCI_CLK_CTL5		0x0400
-#define FPGA_REG16_PCI_CLK_CTL6		0x0200
-#define FPGA_REG16_PCI_CLK_CTL7		0x0100
-#define FPGA_REG16_PCI_CLK_CTL8		0x0080
-#define FPGA_REG16_PCI_CLK_CTL9		0x0040
-#define FPGA_REG16_PCI_EXT_ARB0		0x0020
-#define FPGA_REG16_PCI_MODE_1		0x0010
-#define FPGA_REG16_PCI_TARGET_MODE	0x0008
-#define FPGA_REG16_PCI_INTP_MODE	0x0004
-
-/* FB1 Divisor selection */
-#define FPGA_REG16_FB2_DIV_MASK		0x1000
-#define FPGA_REG16_FB2_DIV_LOW		0x0000
-#define FPGA_REG16_FB2_DIV_HIGH		0x1000
-/* FB2 Divisor selection */
-/* S3 switch on Board */
-#define FPGA_REG16_FB1_DIV_MASK		0x2000
-#define FPGA_REG16_FB1_DIV_LOW		0x0000
-#define FPGA_REG16_FB1_DIV_HIGH		0x2000
-/* PCI0 Clock Selection */
-/* S3 switch on Board */
-#define FPGA_REG16_PCI0_CLK_MASK	0x0c00
-#define FPGA_REG16_PCI0_CLK_33_33	0x0000
-#define FPGA_REG16_PCI0_CLK_66_66	0x0800
-#define FPGA_REG16_PCI0_CLK_100		0x0400
-#define FPGA_REG16_PCI0_CLK_133_33	0x0c00
-/* VCO Divisor selection */
-/* S3 switch on Board */
-#define FPGA_REG16_VCO_DIV_MASK		0xc000
-#define FPGA_REG16_VCO_DIV_4		0x0000
-#define FPGA_REG16_VCO_DIV_8		0x4000
-#define FPGA_REG16_VCO_DIV_6		0x8000
-#define FPGA_REG16_VCO_DIV_10		0xc000
-/* Master Clock Selection */
-/* S3, S4 switches on Board */
-#define FPGA_REG16_MASTER_CLK_MASK	0x01c0
-#define FPGA_REG16_MASTER_CLK_EXT	0x0000
-#define FPGA_REG16_MASTER_CLK_66_66	0x0040
-#define FPGA_REG16_MASTER_CLK_50	0x0080
-#define FPGA_REG16_MASTER_CLK_33_33	0x00c0
-#define FPGA_REG16_MASTER_CLK_25	0x0100
-
-/*----------------------------------------------------------------------------+
-| PCI Miscellaneous
-+----------------------------------------------------------------------------*/
-#define FPGA_REG18	(FPGA_REG_BASE_ADDR+0x18)
-
-#define FPGA_REG18_PCI_PRSNT1		0x8000
-#define FPGA_REG18_PCI_PRSNT2		0x4000
-#define FPGA_REG18_PCI_INTA		0x2000
-#define FPGA_REG18_PCI_SLOT0_INTP	0x1000
-#define FPGA_REG18_PCI_SLOT1_INTP	0x0800
-#define FPGA_REG18_PCI_SLOT2_INTP	0x0400
-#define FPGA_REG18_PCI_SLOT3_INTP	0x0200
-#define FPGA_REG18_PCI_PCI0_VC		0x0100
-#define FPGA_REG18_PCI_PCI0_VTH1	0x0080
-#define FPGA_REG18_PCI_PCI0_VTH2	0x0040
-#define FPGA_REG18_PCI_PCI0_VTH3	0x0020
-
-/*----------------------------------------------------------------------------+
-| PCIe Miscellaneous
-+----------------------------------------------------------------------------*/
-#define FPGA_REG1A	(FPGA_REG_BASE_ADDR+0x1A)
-
-#define FPGA_REG1A_PE0_GLED		0x8000
-#define FPGA_REG1A_PE1_GLED		0x4000
-#define FPGA_REG1A_PE2_GLED		0x2000
-#define FPGA_REG1A_PE0_YLED		0x1000
-#define FPGA_REG1A_PE1_YLED		0x0800
-#define FPGA_REG1A_PE2_YLED		0x0400
-#define FPGA_REG1A_PE0_PWRON		0x0200
-#define FPGA_REG1A_PE1_PWRON		0x0100
-#define FPGA_REG1A_PE2_PWRON		0x0080
-#define FPGA_REG1A_PE0_REFCLK_ENABLE	0x0040
-#define FPGA_REG1A_PE1_REFCLK_ENABLE	0x0020
-#define FPGA_REG1A_PE2_REFCLK_ENABLE	0x0010
-#define FPGA_REG1A_PE_SPREAD0		0x0008
-#define FPGA_REG1A_PE_SPREAD1		0x0004
-#define FPGA_REG1A_PE_SELSOURCE_0	0x0002
-#define FPGA_REG1A_PE_SELSOURCE_1	0x0001
-
-#define FPGA_REG1A_GLED_ENCODE(n)	(FPGA_REG1A_PE0_GLED >> (n))
-#define FPGA_REG1A_YLED_ENCODE(n)	(FPGA_REG1A_PE0_YLED >> (n))
-#define FPGA_REG1A_PWRON_ENCODE(n)	(FPGA_REG1A_PE0_PWRON >> (n))
-#define FPGA_REG1A_REFCLK_ENCODE(n)	(FPGA_REG1A_PE0_REFCLK_ENABLE >> (n))
-
-/*----------------------------------------------------------------------------+
-| PCIe Miscellaneous
-+----------------------------------------------------------------------------*/
-#define FPGA_REG1C	(FPGA_REG_BASE_ADDR+0x1C)
-
-#define FPGA_REG1C_PE0_ROOTPOINT	0x8000
-#define FPGA_REG1C_PE1_ENDPOINT		0x4000
-#define FPGA_REG1C_PE2_ENDPOINT		0x2000
-#define FPGA_REG1C_PE0_PRSNT		0x1000
-#define FPGA_REG1C_PE1_PRSNT		0x0800
-#define FPGA_REG1C_PE2_PRSNT		0x0400
-#define FPGA_REG1C_PE0_WAKE		0x0080
-#define FPGA_REG1C_PE1_WAKE		0x0040
-#define FPGA_REG1C_PE2_WAKE		0x0020
-#define FPGA_REG1C_PE0_PERST		0x0010
-#define FPGA_REG1C_PE1_PERST		0x0008
-#define FPGA_REG1C_PE2_PERST		0x0004
-
-#define FPGA_REG1C_ROOTPOINT_ENCODE(n)	(FPGA_REG1C_PE0_ROOTPOINT >> (n))
-#define FPGA_REG1C_PERST_ENCODE(n)	(FPGA_REG1C_PE0_PERST >> (n))
-
-/*----------------------------------------------------------------------------+
-| Defines
-+----------------------------------------------------------------------------*/
-#define PERIOD_133_33MHZ	7500	/* 7,5ns */
-#define PERIOD_100_00MHZ	10000	/* 10ns */
-#define PERIOD_83_33MHZ		12000	/* 12ns */
-#define PERIOD_75_00MHZ		13333	/* 13,333ns */
-#define PERIOD_66_66MHZ		15000	/* 15ns */
-#define PERIOD_50_00MHZ		20000	/* 20ns */
-#define PERIOD_33_33MHZ		30000	/* 30ns */
-#define PERIOD_25_00MHZ		40000	/* 40ns */
-
-#endif	/* __CONFIG_H */
diff --git a/include/post.h b/include/post.h
index b9b9c3775b..d5278111e8 100644
--- a/include/post.h
+++ b/include/post.h
@@ -35,10 +35,6 @@
 #include <asm/immap_86xx.h>
 #define _POST_WORD_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PIC_OFFSET + \
 				offsetof(ccsr_pic_t, tfrr))
-
-#elif defined (CONFIG_4xx)
-#define _POST_WORD_ADDR \
-	(CONFIG_SYS_OCM_DATA_ADDR + CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
 #endif
 
 #ifndef _POST_WORD_ADDR
diff --git a/include/serial.h b/include/serial.h
index a5b555d14c..f4171964ae 100644
--- a/include/serial.h
+++ b/include/serial.h
@@ -26,10 +26,7 @@ extern struct serial_device serial_smc_device;
 extern struct serial_device serial_scc_device;
 extern struct serial_device *default_serial_console(void);
 
-#if	defined(CONFIG_405GP) || \
-	defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
-	defined(CONFIG_405EX) || defined(CONFIG_440) || \
-	defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \
+#if	defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \
 	defined(CONFIG_MPC86xx) || \
 	defined(CONFIG_TEGRA) || defined(CONFIG_SYS_COREBOOT) || \
 	defined(CONFIG_MICROBLAZE)
diff --git a/include/watchdog.h b/include/watchdog.h
index 322dda79f0..52f4c506b0 100644
--- a/include/watchdog.h
+++ b/include/watchdog.h
@@ -72,11 +72,6 @@ int init_func_watchdog_reset(void);
  * Prototypes from $(CPU)/cpu.c.
  */
 
-/* AMCC 4xx */
-#if defined(CONFIG_4xx) && !defined(__ASSEMBLY__)
-	void reset_4xx_watchdog(void);
-#endif
-
 #if defined(CONFIG_HW_WATCHDOG) && !defined(__ASSEMBLY__)
 	void hw_watchdog_init(void);
 #endif