diff options
| author | Sylwester Nawrocki <s.nawrocki@samsung.com> | 2020-05-25 13:39:52 +0200 |
|---|---|---|
| committer | Matthias Brugger <mbrugger@suse.com> | 2020-07-09 15:46:12 +0200 |
| commit | 8e2ab05000ab91daea63022665d2b0c86f5cba3c (patch) | |
| tree | a4537a3fa32a7f818fe4226a7186c0b72773cb5a /include/usb | |
| parent | 61293f519ef75b3ead00a083f65811df31692b9d (diff) | |
| download | u-boot-8e2ab05000ab91daea63022665d2b0c86f5cba3c.tar.gz u-boot-8e2ab05000ab91daea63022665d2b0c86f5cba3c.tar.bz2 u-boot-8e2ab05000ab91daea63022665d2b0c86f5cba3c.zip | |
usb: xhci: Use only 32-bit accesses in xhci_writeq/xhci_readq
There might be hardware configurations where 64-bit data accesses
to XHCI registers are not supported properly. This patch removes
the readq/writeq so always two 32-bit accesses are used to read/write
64-bit XHCI registers, similarly as it is done in Linux kernel.
This patch fixes operation of the XHCI controller on RPI4 Broadcom
BCM2711 SoC based board, where the VL805 USB XHCI controller is
connected to the PCIe Root Complex, which is attached to the system
through the SCB bridge.
Even though the architecture is 64-bit the PCIe BAR is 32-bit and likely
the 64-bit wide register accesses initiated by the CPU are not properly
translated to a sequence of 32-bit PCIe accesses.
xhci_readq(), for example, always returns same value in upper and lower
32-bits, e.g. 0xabcd1234abcd1234 instead of 0x00000000abcd1234.
Cc: Sergey Temerkhanov <s.temerkhanov@gmail.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Diffstat (limited to 'include/usb')
| -rw-r--r-- | include/usb/xhci.h | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/include/usb/xhci.h b/include/usb/xhci.h index 20e4a21066..1170c0ac69 100644 --- a/include/usb/xhci.h +++ b/include/usb/xhci.h @@ -1114,28 +1114,20 @@ static inline void xhci_writel(uint32_t volatile *regs, const unsigned int val) */ static inline u64 xhci_readq(__le64 volatile *regs) { -#if BITS_PER_LONG == 64 - return readq(regs); -#else __u32 *ptr = (__u32 *)regs; u64 val_lo = readl(ptr); u64 val_hi = readl(ptr + 1); return val_lo + (val_hi << 32); -#endif } static inline void xhci_writeq(__le64 volatile *regs, const u64 val) { -#if BITS_PER_LONG == 64 - writeq(val, regs); -#else __u32 *ptr = (__u32 *)regs; u32 val_lo = lower_32_bits(val); /* FIXME */ u32 val_hi = upper_32_bits(val); writel(val_lo, ptr); writel(val_hi, ptr + 1); -#endif } int xhci_hcd_init(int index, struct xhci_hccr **ret_hccr, |