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| author | Sean Anderson <sean.anderson@seco.com> | 2023-10-27 16:57:03 -0400 |
|---|---|---|
| committer | Jaehoon Chung <jh80.chung@samsung.com> | 2023-11-01 10:01:10 +0900 |
| commit | 21c84bb1112695f9bd49379f7e32c251b55a3cad (patch) | |
| tree | 2fbe9e0e90b289fe6073799180d31806f9fe6d7f /include/sdhci.h | |
| parent | c27c8102e128827c684d8d3da7f0ce03d550b65a (diff) | |
| download | u-boot-21c84bb1112695f9bd49379f7e32c251b55a3cad.tar.gz u-boot-21c84bb1112695f9bd49379f7e32c251b55a3cad.tar.bz2 u-boot-21c84bb1112695f9bd49379f7e32c251b55a3cad.zip | |
mmc: sdhci: Rework SDHCI_QUIRK_BROKEN_R1B
As noted in commit 3a6383207be ("mmc: sdhci: add the quirk for broken
r1b response"), some MMC controllers don't always set the transfer
complete bit with R1b responses.
According to the SD Host Controller Simplified Specification v4.20,
> In the case of a command pairing with response-with-busy[, Transfer
> Complete] is set when busy is de-asserted. Refer to DAT Line Active
> and Command Inhibit (DAT) in the Present State register.
By polling the DAT Line Active bit in the present state register, we can
detect when we are no longer busy, without waiting for a long timeout.
This results in much faster reads/writes on buggy controllers.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Tested-by: Henrik Grimler <henrik@grimler.se>
Diffstat (limited to 'include/sdhci.h')
| -rw-r--r-- | include/sdhci.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/sdhci.h b/include/sdhci.h index 70fefca2a9..a1b74e3bd7 100644 --- a/include/sdhci.h +++ b/include/sdhci.h @@ -57,6 +57,7 @@ #define SDHCI_PRESENT_STATE 0x24 #define SDHCI_CMD_INHIBIT BIT(0) #define SDHCI_DATA_INHIBIT BIT(1) +#define SDHCI_DAT_ACTIVE BIT(2) #define SDHCI_DOING_WRITE BIT(8) #define SDHCI_DOING_READ BIT(9) #define SDHCI_SPACE_AVAILABLE BIT(10) |