diff options
| author | Stephen Carlson <stcarlso@linux.microsoft.com> | 2023-03-10 11:07:13 -0800 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2023-03-30 15:09:59 -0400 |
| commit | 59b1c9be01934222cf773b35de7c8d086dabaef6 (patch) | |
| tree | f56283a9ea04afe388987fb53faf873336bb6d84 /include/pci.h | |
| parent | 19213d7a65e9e3f8cfd0852599170636c894169e (diff) | |
| download | u-boot-59b1c9be01934222cf773b35de7c8d086dabaef6.tar.gz u-boot-59b1c9be01934222cf773b35de7c8d086dabaef6.tar.bz2 u-boot-59b1c9be01934222cf773b35de7c8d086dabaef6.zip | |
cmd: pci: Add command to set MPS of all PCIe devices
Enable tuning of the PCI Express MPS (Maximum Payload Size) of
each device. The Maximum Read Request Size is not altered.
The SAFE method uses the largest MPS value supported by all devices in the
system for each device. This method is the same algorithm as used by Linux
pci=pcie_bus_safe.
The PEER2PEER method sets all devices to the minimal (128 byte) MPS, which
allows hot plug of devices later that might only support the minimum size,
and ensures compatibility of DMA between two devices on the bus.
Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com>
Diffstat (limited to 'include/pci.h')
| -rw-r--r-- | include/pci.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/include/pci.h b/include/pci.h index c55d6107a4..2f5eb30b83 100644 --- a/include/pci.h +++ b/include/pci.h @@ -360,6 +360,13 @@ #define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIe Bridge */ #define PCI_EXP_DEVCAP 4 /* Device capabilities */ #define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */ +#define PCI_EXP_DEVCAP_PAYLOAD 0x0007 /* Max payload size supported */ +#define PCI_EXP_DEVCAP_PAYLOAD_128B 0x0000 /* 128 Bytes */ +#define PCI_EXP_DEVCAP_PAYLOAD_256B 0x0001 /* 256 Bytes */ +#define PCI_EXP_DEVCAP_PAYLOAD_512B 0x0002 /* 512 Bytes */ +#define PCI_EXP_DEVCAP_PAYLOAD_1024B 0x0003 /* 1024 Bytes */ +#define PCI_EXP_DEVCAP_PAYLOAD_2048B 0x0004 /* 2048 Bytes */ +#define PCI_EXP_DEVCAP_PAYLOAD_4096B 0x0005 /* 4096 Bytes */ #define PCI_EXP_DEVCTL 8 /* Device Control */ #define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */ #define PCI_EXP_DEVCTL_PAYLOAD_128B 0x0000 /* 128 Bytes */ |