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| author | Lukasz Majewski <lukma@denx.de> | 2018-05-15 16:26:33 +0200 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2018-05-18 08:27:26 +0200 |
| commit | 07dc39ae02f956e949170270526f652689c18712 (patch) | |
| tree | 8d5c9188de12160c79d56718f010e6c27fb5bd5a /include/fsl_pmic.h | |
| parent | 84a50745a65a6ca0018034d840d5f6bb6542b8af (diff) | |
| download | u-boot-07dc39ae02f956e949170270526f652689c18712.tar.gz u-boot-07dc39ae02f956e949170270526f652689c18712.tar.bz2 u-boot-07dc39ae02f956e949170270526f652689c18712.zip | |
pmic: fsl: Provide some more definitions for MC34708 PMIC
This commit adds some more defines for MC34708 PMIC.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'include/fsl_pmic.h')
| -rw-r--r-- | include/fsl_pmic.h | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/include/fsl_pmic.h b/include/fsl_pmic.h index 6cab77ecb5..fc9e3152a9 100644 --- a/include/fsl_pmic.h +++ b/include/fsl_pmic.h @@ -107,6 +107,7 @@ enum { /* MC34708 Definitions */ #define SWx_VOLT_MASK_MC34708 0x3F +#define SWx_1_110V_MC34708 0x24 #define SWx_1_250V_MC34708 0x30 #define SWx_1_300V_MC34708 0x34 #define TIMER_MASK_MC34708 0x300 @@ -116,4 +117,43 @@ enum { #define SWBST_CTRL 31 #define SWBST_AUTO 0x8 +#define MC34708_REG_SW12_OPMODE 28 + +#define MC34708_SW1AMODE_MASK 0x00000f +#define MC34708_SW1AMHMODE 0x000010 +#define MC34708_SW1AUOMODE 0x000020 +#define MC34708_SW1DVSSPEED 0x0000c0 +#define MC34708_SW2MODE_MASK 0x03c000 +#define MC34708_SW2MHMODE 0x040000 +#define MC34708_SW2UOMODE 0x080000 +#define MC34708_SW2DVSSPEED 0x300000 +#define MC34708_PLLEN 0x400000 +#define MC34708_PLLX 0x800000 + +#define MC34708_REG_SW345_OPMODE 29 + +#define MC34708_SW3MODE_MASK 0x00000f +#define MC34708_SW3MHMODE 0x000010 +#define MC34708_SW3UOMODE 0x000020 +#define MC34708_SW4AMODE_MASK 0x0003c0 +#define MC34708_SW4AMHMODE 0x000400 +#define MC34708_SW4AUOMODE 0x000800 +#define MC34708_SW4BMODE_MASK 0x00f000 +#define MC34708_SW4BMHMODE 0x010000 +#define MC34708_SW4BUOMODE 0x020000 +#define MC34708_SW5MODE_MASK 0x3c0000 +#define MC34708_SW5MHMODE 0x400000 +#define MC34708_SW5UOMODE 0x800000 + +#define SW_MODE_OFFOFF 0x00 +#define SW_MODE_PWMOFF 0x01 +#define SW_MODE_PFMOFF 0x03 +#define SW_MODE_APSOFF 0x04 +#define SW_MODE_PWMPWM 0x05 +#define SW_MODE_PWMAPS 0x06 +#define SW_MODE_APSAPS 0x08 +#define SW_MODE_APSPFM 0x0c +#define SW_MODE_PWMPFM 0x0d +#define SW_MODE_PFMPFM 0x0f + #endif |