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| author | York Sun <yorksun@freescale.com> | 2015-01-06 13:18:55 -0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-02-24 13:09:42 -0800 |
| commit | e32d59a2fa6446b64167bba31c0dd40eb023e8bb (patch) | |
| tree | d2d58e20f9d05aabb5d1d12a4a91ef4cbbb545bd /include/fsl_ddr.h | |
| parent | 064d031ca6490d9641bbe308690b1f15b1f56077 (diff) | |
| download | u-boot-e32d59a2fa6446b64167bba31c0dd40eb023e8bb.tar.gz u-boot-e32d59a2fa6446b64167bba31c0dd40eb023e8bb.tar.bz2 u-boot-e32d59a2fa6446b64167bba31c0dd40eb023e8bb.zip | |
driver/ddr/fsl: Add sync of refresh
Add sync of refresh for multiple DDR controllers. DDRC initialization
needs to complete first. Code is re-ordered to keep refresh close.
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'include/fsl_ddr.h')
| -rw-r--r-- | include/fsl_ddr.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/fsl_ddr.h b/include/fsl_ddr.h index 96fde91687..feccef9c9c 100644 --- a/include/fsl_ddr.h +++ b/include/fsl_ddr.h @@ -118,6 +118,8 @@ void fsl_ddr_set_lawbar( const common_timing_params_t *memctl_common_params, unsigned int memctl_interleaved, unsigned int ctrl_num); +void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl, + unsigned int last_ctrl); int fsl_ddr_interactive_env_var_exists(void); unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set); |