Patch by Klaus Heydeck, 12 May 2004:

Using external watchdog for KUP4 boards in mpc8xx/cpu.c;
load_sernum_ethaddr() for KUP4 boards in lib_ppc/board.c;
various changes to KUP4 board specific files

2 files changed, 152 insertions, 31 deletions

diff --git a/include/configs/KUP4K.h b/include/configs/KUP4K.h
index d6aa8e1037..fc225c918e 100644
--- a/include/configs/KUP4K.h
+++ b/include/configs/KUP4K.h
@@ -72,8 +72,8 @@
 "contrast=55\0"									\
 "silent=1\0"									\
 "load=tftp 200000 bootloader-4k.bitmap;tftp 100000 bootloader-4k.bin\0"		\
-"update=protect off 1:0-5;era 1:0-5;cp.b 100000 40000000 $(filesize);"		\
- "cp.b 200000 40040000 14000\0"
+"update=protect off 1:0-7;era 1:0-7;cp.b 100000 40000000 $(filesize);"		\
+ "cp.b 200000 40050000 14000\0"
 
 #define CONFIG_BOOTCOMMAND  \
     "run slot_a_boot;run slot_b_boot;run nfs_boot;run panic_boot"
@@ -85,7 +85,7 @@
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
 #undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+#define	CONFIG_WATCHDOG	1		/* watchdog enabled		*/
 
 #define CONFIG_STATUS_LED	1	/* Status LED enabled		*/
 
@@ -96,23 +96,81 @@
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
 
-#define CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
 
-#define CONFIG_HARD_I2C
-#define CFG_I2C_SPEED	40000
-#define CFG_I2C_SLAVE	0x7F
+/*
+ * enable I2C and select the hardware/software driver
+ */
+#undef	CONFIG_HARD_I2C			/* I2C with hardware support	*/
+#define	CONFIG_SOFT_I2C         1	/* I2C bit-banged		*/
+
+#define CFG_I2C_SPEED		93000	/* 93 kHz is supposed to work	*/
+#define CFG_I2C_SLAVE		0xFE
+
+#ifdef CONFIG_SOFT_I2C
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define PB_SCL		0x00000020	/* PB 26 */
+#define PB_SDA		0x00000010	/* PB 27 */
+
+#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
+#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
+#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
+#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
+#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
+			else    immr->im_cpm.cp_pbdat &= ~PB_SDA
+#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
+			else    immr->im_cpm.cp_pbdat &= ~PB_SCL
+#define I2C_DELAY	udelay(2)	/* 1/4 I2C clock duration */
+#endif	/* CONFIG_SOFT_I2C */
+
+
+/*-----------------------------------------------------------------------
+ * I2C Configuration
+ */
+
+#define CFG_I2C_PICIO_ADDR	0x21	/* PCF8574 IO Expander			*/
+#define CFG_I2C_RTC_ADDR	0x51	/* PCF8563 RTC				*/
+
 
-#define CONFIG_ETHADDR			00:0B:64:00:00:00 /* our OUI from IEEE */
-#define CONFIG_KUP4K_LOGO		0x40040000  /* Address of logo bitmap */
+/* List of I2C addresses to be verified by POST */
+
+#define I2C_ADDR_LIST	{CFG_I2C_PICIO_ADDR,	\
+			CFG_I2C_RTC_ADDR,	\
+			}
+
+
+#define CONFIG_RTC_PCF8563		/* use Philips PCF8563 RTC	*/
+
+#define CFG_DISCOVER_PHY
+
+#if 0
+#define CONFIG_ETHADDR                  00:0B:64:00:00:00 /* our OUI from IEEE */
+#endif
+#define CONFIG_KUP4K_LOGO               0x40050000  /* Address of logo bitmap */
 
 /* Define to allow the user to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
+#if 1
+/* POST support */
+
+#define CONFIG_POST		(CFG_POST_CPU	   | \
+				 CFG_POST_RTC	   | \
+				 CFG_POST_I2C)
+
+#ifdef CONFIG_POST
+#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
+#else
+#define CFG_CMD_POST_DIAG 0
+#endif
+#endif
 
 #define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
 				CFG_CMD_DHCP	| \
-				CFG_CMD_IDE	| \
 				CFG_CMD_I2C	| \
-				CFG_CMD_DATE	)
+				CFG_CMD_DATE	| \
+				CFG_CMD_POST_DIAG	| \
+				CFG_CMD_IDE	)
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
@@ -189,7 +247,7 @@
 #define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
 #define CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_OFFSET		0x30000 /*   Offset   of Environment Sector	*/
+#define CFG_ENV_OFFSET		0x40000 /*   Offset   of Environment Sector	*/
 #define CFG_ENV_SIZE		0x1000	/* Total Size of Environment Sector	*/
 #define CFG_ENV_SECT_SIZE	0x10000
 
@@ -201,10 +259,10 @@
 /*-----------------------------------------------------------------------
  * Hardware Information Block
  */
-#if 0
-#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
-#define CFG_HWINFO_SIZE		0x00000040	/* size	  of HW Info block */
-#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+#if 1
+#define CFG_HWINFO_OFFSET	0x000F0000	/* offset of HW Info block */
+#define CFG_HWINFO_SIZE		0x00000100	/* size   of HW Info block */
+#define CFG_HWINFO_MAGIC	0x4B26500D	/* 'K&P<CR>' */
 #endif
 /*-----------------------------------------------------------------------
  * Cache Configuration
@@ -220,7 +278,7 @@
  *-----------------------------------------------------------------------
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
-#if defined(CONFIG_WATCHDOG)
+#if 0 && defined(CONFIG_WATCHDOG)       /* KUP uses external TPS3705 WD */
 #define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
diff --git a/include/configs/KUP4X.h b/include/configs/KUP4X.h
index a5dcb4e7c7..849f308267 100644
--- a/include/configs/KUP4X.h
+++ b/include/configs/KUP4X.h
@@ -69,8 +69,9 @@
 #define CONFIG_EXTRA_ENV_SETTINGS						\
 "slot_a_boot=setenv bootargs root=/dev/hda2 ip=off;"				\
   "run addhw;diskboot 200000 0:1;bootm 200000\0"				\
-"slot_b_boot=setenv bootargs root=/dev/hda2 ip=off;"				\
- "run addhw;diskboot 200000 2:1;bootm 200000\0"					\
+"usb_boot=setenv bootargs root=/dev/sda2 ip=off;\
+ run addhw; sleep 2; usb reset; usb scan; usbboot 200000 0:1;\
+ usb stop; bootm 200000\0"      \
 "nfs_boot=dhcp;run nfsargs addip addhw;bootm 200000\0"				\
 "panic_boot=echo No Bootdevice !!! reset\0"					\
 "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath)\0"	\
@@ -85,7 +86,7 @@
  "cp.b 200000 40040000 14000\0"
 
 #define CONFIG_BOOTCOMMAND  \
-    "run slot_a_boot;run nfs_boot;run panic_boot"
+    "run usb_boot;run_slot_a_boot;run nfs_boot;run panic_boot"
 
 
 #define CONFIG_MISC_INIT_R	1
@@ -94,7 +95,7 @@
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
 #undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+#define	CONFIG_WATCHDOG		1	/* watchdog enabled		*/
 
 #define CONFIG_STATUS_LED	1	/* Status LED enabled		*/
 
@@ -105,19 +106,81 @@
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
 
-#define CONFIG_HARD_I2C
-#define CFG_I2C_SPEED 40000
-#define CFG_I2C_SLAVE 0x7F
+/*
+ * enable I2C and select the hardware/software driver
+ */
+#undef	CONFIG_HARD_I2C			/* I2C with hardware support	*/
+#define	CONFIG_SOFT_I2C         1	/* I2C bit-banged		*/
+
+#define CFG_I2C_SPEED		93000	/* 93 kHz is supposed to work	*/
+#define CFG_I2C_SLAVE		0xFE
+
+#ifdef CONFIG_SOFT_I2C
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define PB_SCL		0x00000020	/* PB 26 */
+#define PB_SDA		0x00000010	/* PB 27 */
+
+#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
+#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
+#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
+#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
+#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
+			else    immr->im_cpm.cp_pbdat &= ~PB_SDA
+#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
+			else    immr->im_cpm.cp_pbdat &= ~PB_SCL
+#define I2C_DELAY	udelay(2)	/* 1/4 I2C clock duration */
+#endif	/* CONFIG_SOFT_I2C */
+
+
+/*-----------------------------------------------------------------------
+ * I2C Configuration
+ */
+
+#define CFG_I2C_PICIO_ADDR	0x21	/* PCF8574 IO Expander			*/
+#define CFG_I2C_RTC_ADDR	0x51	/* PCF8563 RTC				*/
+
+
+/* List of I2C addresses to be verified by POST */
 
-#define CONFIG_ETHADDR			00:0B:64:80:00:00 /* our OUI from IEEE */
+#define I2C_ADDR_LIST	{CFG_I2C_PICIO_ADDR,	\
+			CFG_I2C_RTC_ADDR,	\
+			}
+
+
+#define CONFIG_RTC_PCF8563		/* use Philips PCF8563 RTC	*/
+
+#define CFG_DISCOVER_PHY
+
+#if 0
+#define CONFIG_ETHADDR                  00:0B:64:80:00:00 /* our OUI from IEEE */
+#endif
 #undef CONFIG_KUP4K_LOGO
 
 /* Define to allow the user to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 
+
+#if 1
+/* POST support */
+
+#define CONFIG_POST		(CFG_POST_CPU	   | \
+				 CFG_POST_RTC	   | \
+				 CFG_POST_I2C)
+
+#ifdef CONFIG_POST
+#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
+#else
+#define CFG_CMD_POST_DIAG 0
+#endif
+#endif
+
 #define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
 				CFG_CMD_DHCP	| \
 				CFG_CMD_I2C	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_POST_DIAG	| \
 				CFG_CMD_IDE	| \
 				CFG_CMD_USB	| \
 				CFG_CMD_FAT)
@@ -196,7 +259,7 @@
 #define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
 #define CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_OFFSET		0x30000 /*   Offset   of Environment Sector	*/
+#define CFG_ENV_OFFSET		0x40000 /*   Offset   of Environment Sector	*/
 #define CFG_ENV_SIZE		0x1000	/* Total Size of Environment Sector	*/
 #define CFG_ENV_SECT_SIZE	0x10000
 
@@ -208,10 +271,10 @@
 /*-----------------------------------------------------------------------
  * Hardware Information Block
  */
-#if 0
-#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
-#define CFG_HWINFO_SIZE		0x00000040	/* size	  of HW Info block */
-#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+#if 1
+#define CFG_HWINFO_OFFSET	0x000F0000	/* offset of HW Info block */
+#define CFG_HWINFO_SIZE		0x00000100	/* size   of HW Info block */
+#define CFG_HWINFO_MAGIC	0x4B26500D	/* 'K&P<CR>' */
 #endif
 /*-----------------------------------------------------------------------
  * Cache Configuration
@@ -227,7 +290,7 @@
  *-----------------------------------------------------------------------
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
-#if defined(CONFIG_WATCHDOG)
+#if 0 && defined(CONFIG_WATCHDOG)       /* KUP uses external TPS3705 WD */
 #define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else