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| author | Stefan Roese <sr@denx.de> | 2007-10-31 17:57:52 +0100 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2007-10-31 21:21:47 +0100 |
| commit | d25dfe08fbd1220cb994e7e6b105049aa9aa8e79 (patch) | |
| tree | b3fe3e942a36d0e6f668194e6cf911a4b436fca8 /include/configs/CANBT.h | |
| parent | 9b94ac61d2176185c30adf0793e079ec30e68687 (diff) | |
| download | u-boot-d25dfe08fbd1220cb994e7e6b105049aa9aa8e79.tar.gz u-boot-d25dfe08fbd1220cb994e7e6b105049aa9aa8e79.tar.bz2 u-boot-d25dfe08fbd1220cb994e7e6b105049aa9aa8e79.zip | |
ppc4xx: Remove cache definition from 4xx board config files
All 4xx board config files don't need the cache definitions anymore.
These are now defined in common headers.
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'include/configs/CANBT.h')
| -rw-r--r-- | include/configs/CANBT.h | 9 |
1 files changed, 0 insertions, 9 deletions
diff --git a/include/configs/CANBT.h b/include/configs/CANBT.h index ae32f6b14a..7029dbddef 100644 --- a/include/configs/CANBT.h +++ b/include/configs/CANBT.h @@ -181,15 +181,6 @@ /* mask of address bits that overflow into the "EEPROM chip address" */ #define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Init Memory Controller: * |