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| author | Ley Foon Tan <ley.foon.tan@intel.com> | 2019-05-24 10:30:00 +0800 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2019-08-11 16:43:41 -0400 |
| commit | d44f793207973845fdaa0c539bed785607659bab (patch) | |
| tree | 1221a2036460f1beba4043c83974d8d737ae4218 /drivers | |
| parent | bf9b9813ad6c4727f733828a100267601cef52d2 (diff) | |
| download | u-boot-d44f793207973845fdaa0c539bed785607659bab.tar.gz u-boot-d44f793207973845fdaa0c539bed785607659bab.tar.bz2 u-boot-d44f793207973845fdaa0c539bed785607659bab.zip | |
pci: intel: Fix configuration type based on secondary number
This fix issue when access config from PCIe switch.
The PCIe controller need to send Type 0 config TLP if the targeting bus
matches with the secondary bus number, which is when the TLP is targeting
the immediate device on the link.
The PCIe controller send Type 1 config TLP if the targeting bus is
larger than the secondary bus, which is when the TLP is targeting the
device not immediate on the link.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/pci/pcie_intel_fpga.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/drivers/pci/pcie_intel_fpga.c b/drivers/pci/pcie_intel_fpga.c index a096d1c697..a5ea4888f3 100644 --- a/drivers/pci/pcie_intel_fpga.c +++ b/drivers/pci/pcie_intel_fpga.c @@ -36,16 +36,18 @@ #define RP_CFG_ADDR(pcie, reg) \ ((pcie->hip_base) + (reg) + (1 << 20)) +#define RP_SECONDARY(pcie) \ + readb(RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS)) #define TLP_REQ_ID(bus, devfn) (((bus) << 8) | (devfn)) #define TLP_CFGRD_DW0(pcie, bus) \ - ((((bus != pcie->first_busno) ? TLP_FMTTYPE_CFGRD0 \ - : TLP_FMTTYPE_CFGRD1) << 24) | \ + ((((bus > RP_SECONDARY(pcie)) ? TLP_FMTTYPE_CFGRD1 \ + : TLP_FMTTYPE_CFGRD0) << 24) | \ TLP_PAYLOAD_SIZE) #define TLP_CFGWR_DW0(pcie, bus) \ - ((((bus != pcie->first_busno) ? TLP_FMTTYPE_CFGWR0 \ - : TLP_FMTTYPE_CFGWR1) << 24) | \ + ((((bus > RP_SECONDARY(pcie)) ? TLP_FMTTYPE_CFGWR1 \ + : TLP_FMTTYPE_CFGWR0) << 24) | \ TLP_PAYLOAD_SIZE) #define TLP_CFG_DW1(pcie, tag, be) \ |