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authorDaniel Wagenknecht <dwagenk@mailbox.org>2021-12-16 20:42:10 +0100
committerAndre Przywara <andre.przywara@arm.com>2022-01-30 01:03:37 +0000
commitb106a14e2f5dfac53d9cd64a11875c011628558d (patch)
tree407904f244ac60b0488ffc1f09e5bfa71ab25dca /drivers
parent98a90b2730696c1ba773359b7944f6685ae13344 (diff)
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sunxi: SPI: fix pinmuxing for Allwinner H6 SoCs
The driver for SPI0 on Allwinner H6 SoCs did not use the correct define SUN50I_GPC_SPI0 for the pin function, but one for a different Allwinner SoC series. Fix the conditionals to use the correct define for H6 SoCs. This matches the conditional logic in the SPL spi driver. Tested by probing the spi-flash on a pine64_h64-model-b board with adapted device-tree (disable mmc2, enable spi0). Signed-off-by: Daniel Wagenknecht <dwagenk@mailbox.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/spi/spi-sunxi.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/spi/spi-sunxi.c b/drivers/spi/spi-sunxi.c
index bc2f544e86..d62355ec6f 100644
--- a/drivers/spi/spi-sunxi.c
+++ b/drivers/spi/spi-sunxi.c
@@ -249,7 +249,8 @@ static int sun4i_spi_parse_pins(struct udevice *dev)
if (pin < 0)
break;
- if (IS_ENABLED(CONFIG_MACH_SUN50I))
+ if (IS_ENABLED(CONFIG_MACH_SUN50I) ||
+ IS_ENABLED(CONFIG_SUN50I_GEN_H6))
sunxi_gpio_set_cfgpin(pin, SUN50I_GPC_SPI0);
else
sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SPI0);