phy: socionext: Add UniPhier PCIe PHY driver

Add PCIe PHY driver support for Pro5, LD20 and PXs3 SoCs.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>

5 files changed, 80 insertions, 0 deletions

diff --git a/drivers/Kconfig b/drivers/Kconfig
index b1ada1cb7f..c9c812b752 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -80,6 +80,8 @@ source "drivers/phy/allwinner/Kconfig"
 
 source "drivers/phy/marvell/Kconfig"
 
+source "drivers/phy/socionext/Kconfig"
+
 source "drivers/pinctrl/Kconfig"
 
 source "drivers/power/Kconfig"
diff --git a/drivers/Makefile b/drivers/Makefile
index 3510daba29..4081289104 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -96,6 +96,7 @@ obj-$(CONFIG_PCH) += pch/
 obj-y += phy/allwinner/
 obj-y += phy/marvell/
 obj-y += phy/rockchip/
+obj-y += phy/socionext/
 obj-y += rtc/
 obj-y += scsi/
 obj-y += sound/
diff --git a/drivers/phy/socionext/Kconfig b/drivers/phy/socionext/Kconfig
new file mode 100644
index 0000000000..bcd579e98e
--- /dev/null
+++ b/drivers/phy/socionext/Kconfig
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# PHY drivers for Socionext platforms.
+#
+
+config PHY_UNIPHIER_PCIE
+	bool "UniPhier PCIe PHY driver"
+	depends on PHY && ARCH_UNIPHIER
+	imply REGMAP
+	help
+	  Enable this to support PHY implemented in PCIe controller
+	  on UniPhier SoCs.
diff --git a/drivers/phy/socionext/Makefile b/drivers/phy/socionext/Makefile
new file mode 100644
index 0000000000..5484360b70
--- /dev/null
+++ b/drivers/phy/socionext/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Makefile for the phy drivers.
+#
+
+obj-$(CONFIG_PHY_UNIPHIER_PCIE)	+= phy-uniphier-pcie.o
diff --git a/drivers/phy/socionext/phy-uniphier-pcie.c b/drivers/phy/socionext/phy-uniphier-pcie.c
new file mode 100644
index 0000000000..d352c4ca3a
--- /dev/null
+++ b/drivers/phy/socionext/phy-uniphier-pcie.c
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * phy_uniphier_pcie.c - Socionext UniPhier PCIe PHY driver
+ * Copyright 2019-2021 Socionext, Inc.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <generic-phy.h>
+#include <linux/bitops.h>
+#include <linux/compat.h>
+#include <regmap.h>
+#include <syscon.h>
+
+/* SG */
+#define SG_USBPCIESEL		0x590
+#define SG_USBPCIESEL_PCIE	BIT(0)
+
+struct uniphier_pciephy_priv {
+	int dummy;
+};
+
+static int uniphier_pciephy_init(struct phy *phy)
+{
+	return 0;
+}
+
+static int uniphier_pciephy_probe(struct udevice *dev)
+{
+	struct regmap *regmap;
+
+	regmap = syscon_regmap_lookup_by_phandle(dev,
+						 "socionext,syscon");
+	if (!IS_ERR(regmap))
+		regmap_update_bits(regmap, SG_USBPCIESEL,
+				   SG_USBPCIESEL_PCIE, SG_USBPCIESEL_PCIE);
+
+	return 0;
+}
+
+static struct phy_ops uniphier_pciephy_ops = {
+	.init = uniphier_pciephy_init,
+};
+
+static const struct udevice_id uniphier_pciephy_ids[] = {
+	{ .compatible = "socionext,uniphier-pro5-pcie-phy" },
+	{ .compatible = "socionext,uniphier-ld20-pcie-phy" },
+	{ .compatible = "socionext,uniphier-pxs3-pcie-phy" },
+	{ }
+};
+
+U_BOOT_DRIVER(uniphier_pcie_phy) = {
+	.name		= "uniphier-pcie-phy",
+	.id		= UCLASS_PHY,
+	.of_match	= uniphier_pciephy_ids,
+	.ops		= &uniphier_pciephy_ops,
+	.probe		= uniphier_pciephy_probe,
+	.priv_auto      = sizeof(struct uniphier_pciephy_priv),
+};