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| author | Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> | 2024-07-11 13:59:39 +0530 |
|---|---|---|
| committer | Michal Simek <michal.simek@amd.com> | 2024-08-05 16:10:36 +0200 |
| commit | aceac0c52bd25e1e96de5b3a31873eebdc1f5ed8 (patch) | |
| tree | 7bbd498ce9ee664a8801a6bf687cd1d98e0e73b3 /drivers | |
| parent | 6becf9ba1ab82af6f4fcf9f4d0da38f9c75212d2 (diff) | |
| download | u-boot-aceac0c52bd25e1e96de5b3a31873eebdc1f5ed8.tar.gz u-boot-aceac0c52bd25e1e96de5b3a31873eebdc1f5ed8.tar.bz2 u-boot-aceac0c52bd25e1e96de5b3a31873eebdc1f5ed8.zip | |
clk: zynqmp: Add set_rate support for display clocks
If "assigned-clock-rates" property is included in the
device tree, display driver probe is getting failed, as dp_video_ref
till dp_stc_ref clocks are missing from set rate function, adding
them to fix the probe failure.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20240711082939.29260-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/clk/clk_zynqmp.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c index 97f3b999d7..a8239e228c 100644 --- a/drivers/clk/clk_zynqmp.c +++ b/drivers/clk/clk_zynqmp.c @@ -726,6 +726,7 @@ static ulong zynqmp_clk_set_rate(struct clk *clk, ulong rate) case gem_tsu: case qspi_ref ... can1_ref: case usb0_bus_ref ... usb3_dual_ref: + case dp_video_ref ... dp_stc_ref: return zynqmp_clk_set_peripheral_rate(priv, id, rate, two_divs); default: |