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| author | Alexander Dahl <ada@thorsis.com> | 2024-03-20 10:02:13 +0100 |
|---|---|---|
| committer | Dario Binacchi <dario.binacchi@amarulasolutions.com> | 2024-04-14 08:49:40 +0200 |
| commit | 8f9a445c15d173a5aa50d4e4399453de53e9c89e (patch) | |
| tree | 532abbacea8ceb1d2dc132fd4046e556511ce0fd /drivers | |
| parent | e3b7545eb111b544c94c6f1cdd2e6f4252de0211 (diff) | |
| download | u-boot-8f9a445c15d173a5aa50d4e4399453de53e9c89e.tar.gz u-boot-8f9a445c15d173a5aa50d4e4399453de53e9c89e.tar.bz2 u-boot-8f9a445c15d173a5aa50d4e4399453de53e9c89e.zip | |
mtd: nand: raw: atmel: Fix comment in timings preparation
Introduced with commit 6a8dfd57220d ("nand: atmel: Add DM based NAND
driver") when driver was initially ported from Linux. The context
around this and especially the code itself suggests 'read' is meant
instead of write.
The fix is the same as accepted in Linux already with mainline Linux
kernel commit 1c60e027ffde ("mtd: nand: raw: atmel: Fix comment in
timings preparation").
Link: https://lore.kernel.org/all/20240320090214.40465-6-ada@thorsis.com
Link: https://lore.kernel.org/linux-mtd/20240307172835.3453880-1-miquel.raynal@bootlin.com/T/#t
Signed-off-by: Alexander Dahl <ada@thorsis.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/mtd/nand/raw/atmel/nand-controller.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/mtd/nand/raw/atmel/nand-controller.c b/drivers/mtd/nand/raw/atmel/nand-controller.c index e06523f329..ee4ec6da58 100644 --- a/drivers/mtd/nand/raw/atmel/nand-controller.c +++ b/drivers/mtd/nand/raw/atmel/nand-controller.c @@ -1267,7 +1267,7 @@ static int atmel_smc_nand_prepare_smcconf(struct atmel_nand *nand, return ret; /* - * The write cycle timing is directly matching tWC, but is also + * The read cycle timing is directly matching tRC, but is also * dependent on the setup and hold timings we calculated earlier, * which gives: * |