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| author | Chris Packham <chris.packham@alliedtelesis.co.nz> | 2020-05-27 13:31:29 +1200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2020-07-09 06:49:44 +0200 |
| commit | 40ed88529c6ad73c20908c2c5cdbdcc01da3d476 (patch) | |
| tree | 8c3cfdce8c069357072b8beb55dbb9650cb5b8f8 /drivers | |
| parent | 61608f395e7dcb2be6060407a72a1149b046430a (diff) | |
| download | u-boot-40ed88529c6ad73c20908c2c5cdbdcc01da3d476.tar.gz u-boot-40ed88529c6ad73c20908c2c5cdbdcc01da3d476.tar.bz2 u-boot-40ed88529c6ad73c20908c2c5cdbdcc01da3d476.zip | |
mv_ddr: ddr3: Use correct bitmask for read sample delay
In the Armada 385 functional spec (MV-S109094-00 Rev. C) the read sample
delay fields are 5 bits wide. Use the correct bitmask of 0x1f when
extracting the value.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
[upstream https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/22]
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c b/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c index df832ac6dc..ce9a47fc2c 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c +++ b/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c @@ -11,7 +11,7 @@ #define VREF_MAX_INDEX 7 #define MAX_VALUE (1024 - 1) #define MIN_VALUE (-MAX_VALUE) -#define GET_RD_SAMPLE_DELAY(data, cs) ((data >> rd_sample_mask[cs]) & 0xf) +#define GET_RD_SAMPLE_DELAY(data, cs) ((data >> rd_sample_mask[cs]) & 0x1f) u32 ca_delay; int ddr3_tip_centr_skip_min_win_check = 0; |