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| author | Roy Zang <tie-fei.zang@freescale.com> | 2013-03-25 07:39:33 +0000 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2013-05-14 16:13:25 -0500 |
| commit | 3fa75c875c960b0b978c63d6ae27fad8d8a0e692 (patch) | |
| tree | a9a962db913027469002731053463af8c575c972 /drivers | |
| parent | 04bccc3ab043601554ca0d85a57565d8452a8030 (diff) | |
| download | u-boot-3fa75c875c960b0b978c63d6ae27fad8d8a0e692.tar.gz u-boot-3fa75c875c960b0b978c63d6ae27fad8d8a0e692.tar.bz2 u-boot-3fa75c875c960b0b978c63d6ae27fad8d8a0e692.zip | |
T4/usb: move usb 2.0 utmi dual phy init code to cpu_init.c
This is what we have done for the UTMI PHY on P3041/P5020. Then the PHY
initialization can be reused in kernel without “usb start” command.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/usb/host/ehci-fsl.c | 21 |
1 files changed, 0 insertions, 21 deletions
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index 77c41f3c3e..f54b408966 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -89,27 +89,6 @@ int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) if (!strcmp(phy_type, "utmi")) { #if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY) -#if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE) - ccsr_usb_phy_t *usb_phy = - (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; - setbits_be32(&usb_phy->pllprg[1], - CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN | - CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN | - CONFIG_SYS_FSL_USB_PLLPRG2_MFI | - CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN); - setbits_be32(&usb_phy->port1.ctrl, - CONFIG_SYS_FSL_USB_CTRL_PHY_EN); - setbits_be32(&usb_phy->port1.drvvbuscfg, - CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN); - setbits_be32(&usb_phy->port1.pwrfltcfg, - CONFIG_SYS_FSL_USB_PWRFLT_CR_EN); - setbits_be32(&usb_phy->port2.ctrl, - CONFIG_SYS_FSL_USB_CTRL_PHY_EN); - setbits_be32(&usb_phy->port2.drvvbuscfg, - CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN); - setbits_be32(&usb_phy->port2.pwrfltcfg, - CONFIG_SYS_FSL_USB_PWRFLT_CR_EN); -#endif setbits_be32(&ehci->control, PHY_CLK_SEL_UTMI); setbits_be32(&ehci->control, UTMI_PHY_EN); udelay(1000); /* delay required for PHY Clk to appear */ |