diff options
| author | Hai Pham <hai.pham.ud@renesas.com> | 2023-01-26 21:02:04 +0100 |
|---|---|---|
| committer | Marek Vasut <marek.vasut+renesas@gmail.com> | 2023-02-02 01:49:20 +0100 |
| commit | 21a8dbc3691f2f4a7089e8fcf9808bf3ac59f868 (patch) | |
| tree | c26e1c8a9401efe4dcbf4f7689d8d4fb401d6d5d /drivers | |
| parent | 326e05c5e21752f23f1f6090d4c546867211b823 (diff) | |
| download | u-boot-21a8dbc3691f2f4a7089e8fcf9808bf3ac59f868.tar.gz u-boot-21a8dbc3691f2f4a7089e8fcf9808bf3ac59f868.tar.bz2 u-boot-21a8dbc3691f2f4a7089e8fcf9808bf3ac59f868.zip | |
clk: renesas: Use pre-defined offset for RPC clocks
Since commit f7b4e4c0949f ("clk: renesas: Synchronize R-Car Gen3 tables
with Linux 5.12"), the custom macros for RPC clocks were dropped.
Use pre-defined offset for RPC clocks, same as what Linux does, instead
of retrieving it from the macros
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/clk/renesas/clk-rcar-gen3.c | 2 | ||||
| -rw-r--r-- | drivers/clk/renesas/rcar-gen3-cpg.h | 3 |
2 files changed, 1 insertions, 4 deletions
diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c index 3611bdb06f..812580475c 100644 --- a/drivers/clk/renesas/clk-rcar-gen3.c +++ b/drivers/clk/renesas/clk-rcar-gen3.c @@ -324,7 +324,7 @@ static u64 gen3_clk_get_rate64(struct clk *clk) case CLK_TYPE_GEN4_RPCD2: rate = gen3_clk_get_rate64(&parent); - value = readl(priv->base + core->offset); + value = readl(priv->base + CPG_RPCCKCR); prediv = (value >> CPG_RPC_PREDIV_OFFSET) & CPG_RPC_PREDIV_MASK; diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h index a7074e2bcd..007610bb4d 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.h +++ b/drivers/clk/renesas/rcar-gen3-cpg.h @@ -53,9 +53,6 @@ enum rcar_gen3_clk_types { #define DEF_GEN3_SD(_name, _id, _parent, _offset) \ DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset) -#define DEF_GEN3_RPCD2(_name, _id, _parent, _offset) \ - DEF_BASE(_name, _id, CLK_TYPE_GEN3_RPCD2, _parent, .offset = _offset) - #define DEF_GEN3_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \ DEF_BASE(_name, _id, CLK_TYPE_GEN3_MDSEL, \ (_parent0) << 16 | (_parent1), \ |