diff options
| author | Simon Glass <sjg@chromium.org> | 2019-12-06 21:41:49 -0700 |
|---|---|---|
| committer | Bin Meng <bmeng.cn@gmail.com> | 2019-12-15 11:44:09 +0800 |
| commit | 77dd7c6854f3bd8ddc422f0cb1953071fe00dc6c (patch) | |
| tree | 9f20790502407316911d7bab7b2f5b69057e0a05 /drivers/timer/tsc_timer.c | |
| parent | dd0edcb2508b9abcf828baede32e6b3da5fc0c8a (diff) | |
| download | u-boot-77dd7c6854f3bd8ddc422f0cb1953071fe00dc6c.tar.gz u-boot-77dd7c6854f3bd8ddc422f0cb1953071fe00dc6c.tar.bz2 u-boot-77dd7c6854f3bd8ddc422f0cb1953071fe00dc6c.zip | |
x86: timer: use a timer base of 0
On x86 platforms the timer is reset to 0 when the SoC is reset. Having
this as the timer base is useful since it provides an indication of how
long it takes before U-Boot is running.
When U-Boot sets the timer base to something else, time is lost and we
no-longer have an accurate account of the time since reset. This
particularly affects bootstage.
Change the default to not read the timer base, leaving it at 0. Add an
option for when U-Boot is the secondary bootloader.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'drivers/timer/tsc_timer.c')
| -rw-r--r-- | drivers/timer/tsc_timer.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c index 0df551f94c..813817f467 100644 --- a/drivers/timer/tsc_timer.c +++ b/drivers/timer/tsc_timer.c @@ -397,7 +397,8 @@ static void tsc_timer_ensure_setup(bool early) { if (gd->arch.tsc_inited) return; - gd->arch.tsc_base = rdtsc(); + if (IS_ENABLED(CONFIG_X86_TSC_READ_BASE)) + gd->arch.tsc_base = rdtsc(); if (!gd->arch.clock_rate) { unsigned long fast_calibrate; |