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authorSergiu Moga <sergiu.moga@microchip.com>2022-04-01 12:27:24 +0300
committerEugen Hristev <eugen.hristev@microchip.com>2022-04-26 09:51:46 +0300
commit71d4393f846f5ae86ac35c0fd0987719b660c9ba (patch)
treeaaa759e6548e84575b49ee58143144a6d92a35b1 /drivers/sysreset
parent2016585c3a9486ea438145f47a28ee7fa8f7060c (diff)
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sysreset: Add Atmel/Microchip sysreset driver
This patch adds a sysreset driver for Atmel/Microchip platforms. Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Diffstat (limited to 'drivers/sysreset')
-rw-r--r--drivers/sysreset/Kconfig15
-rw-r--r--drivers/sysreset/Makefile1
-rw-r--r--drivers/sysreset/sysreset_at91.c71
3 files changed, 87 insertions, 0 deletions
diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
index f6d60038b8..25dd02c704 100644
--- a/drivers/sysreset/Kconfig
+++ b/drivers/sysreset/Kconfig
@@ -77,6 +77,21 @@ config SYSRESET_OCTEON
This enables the system reset driver support for Marvell Octeon
SoCs.
+config SYSRESET_AT91
+ bool "Enable support for Microchip/Atmel reset driver"
+ depends on ARCH_AT91
+ select SYSRESET_SPL_AT91 if SPL && SPL_SYSRESET
+ help
+ This enables the system reset driver support for Microchip/Atmel
+ SoCs.
+
+config SYSRESET_SPL_AT91
+ bool "Enable support for Microchip/Atmel reset driver in SPL"
+ depends on ARCH_AT91
+ help
+ This enables the system reset driver support for Microchip/Atmel
+ SoCs in SPL.
+
config SYSRESET_PSCI
bool "Enable support for PSCI System Reset"
depends on ARM_PSCI_FW
diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index 8e00be0779..0ed3bbf356 100644
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -20,5 +20,6 @@ obj-$(CONFIG_SYSRESET_TI_SCI) += sysreset-ti-sci.o
obj-$(CONFIG_SYSRESET_SYSCON) += sysreset_syscon.o
obj-$(CONFIG_SYSRESET_WATCHDOG) += sysreset_watchdog.o
obj-$(CONFIG_SYSRESET_RESETCTL) += sysreset_resetctl.o
+obj-$(CONFIG_SYSRESET_$(SPL_TPL_)AT91) += sysreset_at91.o
obj-$(CONFIG_$(SPL_TPL_)SYSRESET_X86) += sysreset_x86.o
obj-$(CONFIG_TARGET_XTFPGA) += sysreset_xtfpga.o
diff --git a/drivers/sysreset/sysreset_at91.c b/drivers/sysreset/sysreset_at91.c
new file mode 100644
index 0000000000..24b87ee987
--- /dev/null
+++ b/drivers/sysreset/sysreset_at91.c
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries
+ */
+
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+#include <asm/arch/at91_rstc.h>
+#include <clk.h>
+#include <common.h>
+#include <cpu_func.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <dm/device-internal.h>
+#include <sysreset.h>
+
+static int at91_sysreset_request(struct udevice *dev, enum sysreset_t type)
+{
+ at91_rstc_t *rstc = (at91_rstc_t *)dev_get_priv(dev);
+
+ writel(AT91_RSTC_KEY
+ | AT91_RSTC_CR_PROCRST /* Processor Reset */
+ | AT91_RSTC_CR_PERRST /* Peripheral Reset */
+#ifdef CONFIG_AT91RESET_EXTRST
+ | AT91_RSTC_CR_EXTRST /* External Reset (assert nRST pin) */
+#endif
+ , &rstc->cr);
+
+ return -EINPROGRESS;
+}
+
+static int at91_sysreset_probe(struct udevice *dev)
+{
+ struct clk slck;
+ void *priv;
+ int ret;
+
+ priv = dev_remap_addr(dev);
+ if (!priv)
+ return -EINVAL;
+
+ dev_set_priv(dev, priv);
+
+ ret = clk_get_by_index(dev, 0, &slck);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(&slck);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static struct sysreset_ops at91_sysreset = {
+ .request = at91_sysreset_request,
+};
+
+static const struct udevice_id a91_sysreset_ids[] = {
+ { .compatible = "atmel,sama5d3-rstc" },
+ { .compatible = "microchip,sam9x60-rstc" },
+ { }
+};
+
+U_BOOT_DRIVER(sysreset_at91) = {
+ .id = UCLASS_SYSRESET,
+ .name = "at91_reset",
+ .ops = &at91_sysreset,
+ .probe = at91_sysreset_probe,
+ .of_match = a91_sysreset_ids,
+};