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| author | Dhruva Gole <d-gole@ti.com> | 2023-04-12 16:28:56 +0530 |
|---|---|---|
| committer | Jagan Teki <jagan@amarulasolutions.com> | 2023-04-26 13:37:39 +0530 |
| commit | 08b3098eadc7f826c3e6fb9d184cf6d82f5028fe (patch) | |
| tree | 01a7fa4fac8722ef15671043bc45c992c16c604e /drivers/spi | |
| parent | 8077d296adff235e13c1478f92ef42c08e17ec33 (diff) | |
| download | u-boot-08b3098eadc7f826c3e6fb9d184cf6d82f5028fe.tar.gz u-boot-08b3098eadc7f826c3e6fb9d184cf6d82f5028fe.tar.bz2 u-boot-08b3098eadc7f826c3e6fb9d184cf6d82f5028fe.zip | |
spi: cadence-quadspi: Reset CMD_CTRL Reg on cmd r/w completion
If one leaves the CQSPI_REG_CMDCTRL in an unclean state this may cause
issues in future command reads. This issue came to light when some flash
reads in STIG mode were coming back dirty.
Co-developed-by: Apurva Nandan <a-nandan@ti.com>
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Signed-off-by: Dhruva Gole <d-gole@ti.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Diffstat (limited to 'drivers/spi')
| -rw-r--r-- | drivers/spi/cadence_qspi_apb.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index 4c055a0580..9ce2c0f254 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -376,6 +376,9 @@ int cadence_qspi_apb_exec_flash_cmd(void *reg_base, unsigned int reg) if (!cadence_qspi_wait_idle(reg_base)) return -EIO; + /* Flush the CMDCTRL reg after the execution */ + writel(0, reg_base + CQSPI_REG_CMDCTRL); + return 0; } |