Merge branch 'next'

1 files changed, 30 insertions, 29 deletions

diff --git a/drivers/spi/cadence_ospi_versal.c b/drivers/spi/cadence_ospi_versal.c
index 52bcad053f..a9547a8200 100644
--- a/drivers/spi/cadence_ospi_versal.c
+++ b/drivers/spi/cadence_ospi_versal.c
@@ -21,7 +21,7 @@
 #define CMD_4BYTE_READ  0x13
 #define CMD_4BYTE_FAST_READ  0x0C
 
-int cadence_qspi_apb_dma_read(struct cadence_spi_plat *plat,
+int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv,
 			      const struct spi_mem_op *op)
 {
 	u32 reg, ret, rx_rem, n_rx, bytes_to_dma, data;
@@ -34,86 +34,86 @@ int cadence_qspi_apb_dma_read(struct cadence_spi_plat *plat,
 
 	if (bytes_to_dma) {
 		cadence_qspi_apb_enable_linear_mode(false);
-		reg = readl(plat->regbase + CQSPI_REG_CONFIG);
+		reg = readl(priv->regbase + CQSPI_REG_CONFIG);
 		reg |= CQSPI_REG_CONFIG_ENBL_DMA;
-		writel(reg, plat->regbase + CQSPI_REG_CONFIG);
+		writel(reg, priv->regbase + CQSPI_REG_CONFIG);
 
-		writel(bytes_to_dma, plat->regbase + CQSPI_REG_INDIRECTRDBYTES);
+		writel(bytes_to_dma, priv->regbase + CQSPI_REG_INDIRECTRDBYTES);
 
 		writel(CQSPI_DFLT_INDIR_TRIG_ADDR_RANGE,
-		       plat->regbase + CQSPI_REG_INDIR_TRIG_ADDR_RANGE);
+		       priv->regbase + CQSPI_REG_INDIR_TRIG_ADDR_RANGE);
 		writel(CQSPI_DFLT_DMA_PERIPH_CFG,
-		       plat->regbase + CQSPI_REG_DMA_PERIPH_CFG);
-		writel((unsigned long)rxbuf, plat->regbase +
+		       priv->regbase + CQSPI_REG_DMA_PERIPH_CFG);
+		writel((unsigned long)rxbuf, priv->regbase +
 		       CQSPI_DMA_DST_ADDR_REG);
-		writel(plat->trigger_address, plat->regbase +
+		writel(priv->trigger_address, priv->regbase +
 		       CQSPI_DMA_SRC_RD_ADDR_REG);
-		writel(bytes_to_dma, plat->regbase +
+		writel(bytes_to_dma, priv->regbase +
 		       CQSPI_DMA_DST_SIZE_REG);
 		flush_dcache_range((unsigned long)rxbuf,
 				   (unsigned long)rxbuf + bytes_to_dma);
 		writel(CQSPI_DFLT_DST_CTRL_REG_VAL,
-		       plat->regbase + CQSPI_DMA_DST_CTRL_REG);
+		       priv->regbase + CQSPI_DMA_DST_CTRL_REG);
 
 		/* Start the indirect read transfer */
-		writel(CQSPI_REG_INDIRECTRD_START, plat->regbase +
+		writel(CQSPI_REG_INDIRECTRD_START, priv->regbase +
 		       CQSPI_REG_INDIRECTRD);
 		/* Wait for dma to complete transfer */
-		ret = cadence_qspi_apb_wait_for_dma_cmplt(plat);
+		ret = cadence_qspi_apb_wait_for_dma_cmplt(priv);
 		if (ret)
 			return ret;
 
 		/* Clear indirect completion status */
-		writel(CQSPI_REG_INDIRECTRD_DONE, plat->regbase +
+		writel(CQSPI_REG_INDIRECTRD_DONE, priv->regbase +
 		       CQSPI_REG_INDIRECTRD);
 		rxbuf += bytes_to_dma;
 	}
 
 	if (rx_rem) {
-		reg = readl(plat->regbase + CQSPI_REG_CONFIG);
+		reg = readl(priv->regbase + CQSPI_REG_CONFIG);
 		reg &= ~CQSPI_REG_CONFIG_ENBL_DMA;
-		writel(reg, plat->regbase + CQSPI_REG_CONFIG);
+		writel(reg, priv->regbase + CQSPI_REG_CONFIG);
 
-		reg = readl(plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);
+		reg = readl(priv->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);
 		reg += bytes_to_dma;
-		writel(reg, plat->regbase + CQSPI_REG_CMDADDRESS);
+		writel(reg, priv->regbase + CQSPI_REG_CMDADDRESS);
 
-		addr_bytes = readl(plat->regbase + CQSPI_REG_SIZE) &
+		addr_bytes = readl(priv->regbase + CQSPI_REG_SIZE) &
 				   CQSPI_REG_SIZE_ADDRESS_MASK;
 
 		opcode = CMD_4BYTE_FAST_READ;
 		dummy_cycles = 8;
 		writel((dummy_cycles << CQSPI_REG_RD_INSTR_DUMMY_LSB) | opcode,
-		       plat->regbase + CQSPI_REG_RD_INSTR);
+		       priv->regbase + CQSPI_REG_RD_INSTR);
 
 		reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 		reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
 		reg |= (addr_bytes & CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) <<
 			CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
 		reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
-		dummy_cycles = (readl(plat->regbase + CQSPI_REG_RD_INSTR) >>
+		dummy_cycles = (readl(priv->regbase + CQSPI_REG_RD_INSTR) >>
 				CQSPI_REG_RD_INSTR_DUMMY_LSB) &
 				CQSPI_REG_RD_INSTR_DUMMY_MASK;
 		reg |= (dummy_cycles & CQSPI_REG_CMDCTRL_DUMMY_MASK) <<
 			CQSPI_REG_CMDCTRL_DUMMY_LSB;
 		reg |= (((rx_rem - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK) <<
 			CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
-		ret = cadence_qspi_apb_exec_flash_cmd(plat->regbase, reg);
+		ret = cadence_qspi_apb_exec_flash_cmd(priv->regbase, reg);
 		if (ret)
 			return ret;
 
-		data = readl(plat->regbase + CQSPI_REG_CMDREADDATALOWER);
+		data = readl(priv->regbase + CQSPI_REG_CMDREADDATALOWER);
 		memcpy(rxbuf, &data, rx_rem);
 	}
 
 	return 0;
 }
 
-int cadence_qspi_apb_wait_for_dma_cmplt(struct cadence_spi_plat *plat)
+int cadence_qspi_apb_wait_for_dma_cmplt(struct cadence_spi_priv *priv)
 {
 	u32 timeout = CQSPI_DMA_TIMEOUT;
 
-	while (!(readl(plat->regbase + CQSPI_DMA_DST_I_STS_REG) &
+	while (!(readl(priv->regbase + CQSPI_DMA_DST_I_STS_REG) &
 		 CQSPI_DMA_DST_I_STS_DONE) && timeout--)
 		udelay(1);
 
@@ -122,14 +122,15 @@ int cadence_qspi_apb_wait_for_dma_cmplt(struct cadence_spi_plat *plat)
 		return -ETIMEDOUT;
 	}
 
-	writel(readl(plat->regbase + CQSPI_DMA_DST_I_STS_REG),
-	       plat->regbase + CQSPI_DMA_DST_I_STS_REG);
+	writel(readl(priv->regbase + CQSPI_DMA_DST_I_STS_REG),
+	       priv->regbase + CQSPI_DMA_DST_I_STS_REG);
 	return 0;
 }
 
 #if defined(CONFIG_DM_GPIO)
-int cadence_spi_versal_flash_reset(struct udevice *dev)
+int cadence_qspi_versal_flash_reset(struct udevice *dev)
 {
+#ifndef CONFIG_ARCH_VERSAL_NET
 	struct gpio_desc gpio;
 	u32 reset_gpio;
 	int ret;
@@ -165,11 +166,11 @@ int cadence_spi_versal_flash_reset(struct udevice *dev)
 	/* Set value 1 to pin */
 	dm_gpio_set_value(&gpio, 1);
 	udelay(1);
-
+#endif
 	return 0;
 }
 #else
-int cadence_spi_versal_flash_reset(struct udevice *dev)
+int cadence_qspi_versal_flash_reset(struct udevice *dev)
 {
 	/* CRP WPROT */
 	writel(0, WPROT_CRP);