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authorAshok Reddy Soma <ashok.reddy.soma@xilinx.com>2020-12-01 00:34:47 -0700
committerMichal Simek <michal.simek@xilinx.com>2021-01-04 10:51:26 +0100
commite5e8bbd25a499e65e7403b0b054fe35abe5187b3 (patch)
tree409b92d16db048cbd3dd2d7fb24eac4891014770 /drivers/serial
parentd91a652cfd96e2c4217946a1839cf3c8c0523e85 (diff)
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serial: uartlite: Fix uninitialized ret in debug uartlite
Endianness detection is checked against uninitialized ret variable. Assign ret with read value from status register to fix this. Fixes: 31a359f87eaa ("serial: uartlite: Add support to work with any endianness") Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'drivers/serial')
-rw-r--r--drivers/serial/serial_xuartlite.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/serial/serial_xuartlite.c b/drivers/serial/serial_xuartlite.c
index 236ab860ad..1453fb4257 100644
--- a/drivers/serial/serial_xuartlite.c
+++ b/drivers/serial/serial_xuartlite.c
@@ -148,7 +148,7 @@ static inline void _debug_uart_init(void)
uart_out32(&regs->control, 0);
uart_out32(&regs->control, ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX);
- uart_in32(&regs->status);
+ ret = uart_in32(&regs->status);
/* Endianness detection */
if ((ret & SR_TX_FIFO_EMPTY) != SR_TX_FIFO_EMPTY) {
little_endian = true;