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| author | Ben Dooks <ben.dooks@sifive.com> | 2022-10-20 16:51:09 +0100 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-12-12 14:03:11 -0500 |
| commit | 4c56d75117341103388f001818a0a1f8f6c449f1 (patch) | |
| tree | 907f482d89dd275c1a5f7d20be10b2401a02bed9 /drivers/pci | |
| parent | 1eaffe39583a784390d579c3ca9e06b58164f4d0 (diff) | |
| download | u-boot-4c56d75117341103388f001818a0a1f8f6c449f1.tar.gz u-boot-4c56d75117341103388f001818a0a1f8f6c449f1.tar.bz2 u-boot-4c56d75117341103388f001818a0a1f8f6c449f1.zip | |
drivers: pci: pcie_dw_common: add upper-limit to iATU
The 4.6 spec added an upper 32bits to the ATU limit, and since this
driver is already assuming the unrolled feature added in the 4.8
specification this really should be set.
This is causing a bug with testing against the QEMU model as it
defaults the viewports to fully open and not setting this causes
the config viewport to become most of memory (obviously stopping
the emulated system working correctly)
Signed-off-by: Ben Dooks <ben.dooks@sifive.com>
Diffstat (limited to 'drivers/pci')
| -rw-r--r-- | drivers/pci/pcie_dw_common.c | 2 | ||||
| -rw-r--r-- | drivers/pci/pcie_dw_common.h | 1 |
2 files changed, 3 insertions, 0 deletions
diff --git a/drivers/pci/pcie_dw_common.c b/drivers/pci/pcie_dw_common.c index e66fb1490a..9f8b016d11 100644 --- a/drivers/pci/pcie_dw_common.c +++ b/drivers/pci/pcie_dw_common.c @@ -73,6 +73,8 @@ int pcie_dw_prog_outbound_atu_unroll(struct pcie_dw *pci, int index, upper_32_bits(cpu_addr)); dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LIMIT, lower_32_bits(cpu_addr + size - 1)); + dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_LIMIT, + upper_32_bits(cpu_addr + size - 1)); dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET, lower_32_bits(pci_addr)); dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET, diff --git a/drivers/pci/pcie_dw_common.h b/drivers/pci/pcie_dw_common.h index 6b701645af..e0f7796f2a 100644 --- a/drivers/pci/pcie_dw_common.h +++ b/drivers/pci/pcie_dw_common.h @@ -32,6 +32,7 @@ #define PCIE_ATU_UNR_LIMIT 0x10 #define PCIE_ATU_UNR_LOWER_TARGET 0x14 #define PCIE_ATU_UNR_UPPER_TARGET 0x18 +#define PCIE_ATU_UNR_UPPER_LIMIT 0x20 #define PCIE_ATU_REGION_INDEX1 (0x1 << 0) #define PCIE_ATU_REGION_INDEX0 (0x0 << 0) |