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authorMarek Vasut <marek.vasut+renesas@gmail.com>2021-01-16 00:33:17 +0100
committerMarek Vasut <marek.vasut+renesas@gmail.com>2021-02-20 22:38:28 +0100
commit06183ac5f583d6a6279dd5479cd9b44b7edd9d4c (patch)
treecc0d2e5e1414a6237f246ab788c7f1e568b4da64 /drivers/pci
parentb169ef17984ff73bee3b4e94844699893971bb8a (diff)
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pci: renesas: Fix BAR mapping on Gen3
Because the first PCIExAR(n) register is configured with the mapping, It is the second PCIExAR(n) register that must be written with 0, not the last one. Update the n from 4 to 1 to select the correct register. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Diffstat (limited to 'drivers/pci')
-rw-r--r--drivers/pci/pci-rcar-gen3.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/pci/pci-rcar-gen3.c b/drivers/pci/pci-rcar-gen3.c
index 6b08409b85..34a561ef8b 100644
--- a/drivers/pci/pci-rcar-gen3.c
+++ b/drivers/pci/pci-rcar-gen3.c
@@ -358,9 +358,9 @@ static int rcar_gen3_pcie_probe(struct udevice *dev)
break;
}
- writel(0, priv->regs + PCIEPRAR(4));
- writel(0, priv->regs + PCIELAR(4));
- writel(0, priv->regs + PCIELAMR(4));
+ writel(0, priv->regs + PCIEPRAR(1));
+ writel(0, priv->regs + PCIELAR(1));
+ writel(0, priv->regs + PCIELAMR(1));
ret = rcar_gen3_pcie_hw_init(dev);
if (ret)