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| author | Pratyush Yadav <p.yadav@ti.com> | 2021-06-26 00:47:21 +0530 |
|---|---|---|
| committer | Jagan Teki <jagan@amarulasolutions.com> | 2021-06-28 12:03:57 +0530 |
| commit | 6b808e0864dbd492d33e7149fb1666bef7e56049 (patch) | |
| tree | 70fd5cda84efb3648a8cb42de05e235f874b6ff5 /drivers/mtd/spi | |
| parent | b862765c7c9a64640ce557bc10a10b4f20e8584b (diff) | |
| download | u-boot-6b808e0864dbd492d33e7149fb1666bef7e56049.tar.gz u-boot-6b808e0864dbd492d33e7149fb1666bef7e56049.tar.bz2 u-boot-6b808e0864dbd492d33e7149fb1666bef7e56049.zip | |
mtd: spi-nor-core: Enable octal DTR mode when possible
Allow flashes to specify a hook to enable octal DTR mode. Use this hook
whenever possible to get optimal transfer speeds.
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Diffstat (limited to 'drivers/mtd/spi')
| -rw-r--r-- | drivers/mtd/spi/spi-nor-core.c | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index b9d3101d57..cdb464813b 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -2888,10 +2888,41 @@ static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info, return nor->setup(nor, info, params); } +/** spi_nor_octal_dtr_enable() - enable Octal DTR I/O if needed + * @nor: pointer to a 'struct spi_nor' + * + * Return: 0 on success, -errno otherwise. + */ +static int spi_nor_octal_dtr_enable(struct spi_nor *nor) +{ + int ret; + + if (!nor->octal_dtr_enable) + return 0; + + if (!(nor->read_proto == SNOR_PROTO_8_8_8_DTR && + nor->write_proto == SNOR_PROTO_8_8_8_DTR)) + return 0; + + ret = nor->octal_dtr_enable(nor); + if (ret) + return ret; + + nor->reg_proto = SNOR_PROTO_8_8_8_DTR; + + return 0; +} + static int spi_nor_init(struct spi_nor *nor) { int err; + err = spi_nor_octal_dtr_enable(nor); + if (err) { + dev_dbg(nor->dev, "Octal DTR mode not supported\n"); + return err; + } + /* * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up * with the software protection bits set |