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| author | Peng Fan <peng.fan@nxp.com> | 2018-08-10 14:07:55 +0800 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2018-09-10 20:48:19 -0400 |
| commit | c76382ff7f213d7d182fa8a1dfb2df114deb075f (patch) | |
| tree | 2850dc163462e2c18b5c38d695b4f4e9f09d8fb1 /drivers/mmc/fsl_esdhc.c | |
| parent | 3dd2626f48af6f459b8bfb9ce7c6832b0606e813 (diff) | |
| download | u-boot-c76382ff7f213d7d182fa8a1dfb2df114deb075f.tar.gz u-boot-c76382ff7f213d7d182fa8a1dfb2df114deb075f.tar.bz2 u-boot-c76382ff7f213d7d182fa8a1dfb2df114deb075f.zip | |
mmc: fsl_esdhc: enable HS400 feature
The strobe dll code is ported from Linux Kernel:
drivers/mmc/host/sdhci-esdhc-imx.c
The comments are from the above file,
"For HS400 eMMC, there is a data_strobe line. This signal is generated
by the device and used for data output and CRC status response output
in HS400 mode. The frequency of this signal follows the frequency of
CLK generated by host. The host receives the data which is aligned to the
edge of data_strobe line. Due to the time delay between CLK line and
data_strobe line, if the delay time is larger than one clock cycle,
then CLK and data_strobe line will be misaligned, read error shows up.
So when the CLK is higher than 100MHz, each clock cycle is short enough,
host should configure the delay target. "
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'drivers/mmc/fsl_esdhc.c')
| -rw-r--r-- | drivers/mmc/fsl_esdhc.c | 36 |
1 files changed, 35 insertions, 1 deletions
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 4528345c67..03c6743ae8 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -662,6 +662,7 @@ static int esdhc_change_pinstate(struct udevice *dev) break; case UHS_SDR104: case MMC_HS_200: + case MMC_HS_400: ret = pinctrl_select_state(dev, "state_200mhz"); break; default: @@ -689,6 +690,33 @@ static void esdhc_reset_tuning(struct mmc *mmc) } } +static void esdhc_set_strobe_dll(struct mmc *mmc) +{ + struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev); + struct fsl_esdhc *regs = priv->esdhc_regs; + u32 val; + + if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) { + writel(ESDHC_STROBE_DLL_CTRL_RESET, ®s->strobe_dllctrl); + + /* + * enable strobe dll ctrl and adjust the delay target + * for the uSDHC loopback read clock + */ + val = ESDHC_STROBE_DLL_CTRL_ENABLE | + (priv->strobe_dll_delay_target << + ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT); + writel(val, ®s->strobe_dllctrl); + /* wait 1us to make sure strobe dll status register stable */ + mdelay(1); + val = readl(®s->strobe_dllstat); + if (!(val & ESDHC_STROBE_DLL_STS_REF_LOCK)) + pr_warn("HS400 strobe DLL status REF not lock!\n"); + if (!(val & ESDHC_STROBE_DLL_STS_SLV_LOCK)) + pr_warn("HS400 strobe DLL status SLV not lock!\n"); + } +} + static int esdhc_set_timing(struct mmc *mmc) { struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev); @@ -702,6 +730,12 @@ static int esdhc_set_timing(struct mmc *mmc) case MMC_LEGACY: case SD_LEGACY: esdhc_reset_tuning(mmc); + writel(mixctrl, ®s->mixctrl); + break; + case MMC_HS_400: + mixctrl |= MIX_CTRL_DDREN | MIX_CTRL_HS400_EN; + writel(mixctrl, ®s->mixctrl); + esdhc_set_strobe_dll(mmc); break; case MMC_HS: case MMC_HS_52: @@ -1438,7 +1472,7 @@ static int fsl_esdhc_probe(struct udevice *dev) #endif if (fdt_get_property(fdt, node, "no-1-8-v", NULL)) - priv->caps &= ~(UHS_CAPS | MMC_MODE_HS200); + priv->caps &= ~(UHS_CAPS | MMC_MODE_HS200 | MMC_MODE_HS400); /* * TODO: |