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| author | Dinh Nguyen <dinguyen@kernel.org> | 2016-01-19 09:16:21 -0600 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2016-02-04 12:43:21 +0100 |
| commit | a409a8b85ee337250043aa0c031a31b3a6639e74 (patch) | |
| tree | 4c348beedae2da790c058f122db09a6b5250f135 /drivers/fpga | |
| parent | 44189a032804c4a16632f4e80abf77f2820e9a48 (diff) | |
| download | u-boot-a409a8b85ee337250043aa0c031a31b3a6639e74.tar.gz u-boot-a409a8b85ee337250043aa0c031a31b3a6639e74.tar.bz2 u-boot-a409a8b85ee337250043aa0c031a31b3a6639e74.zip | |
Revert "arm: socfpga: set the fpga global bit to disable HPS to FPGA signals"
Apparently, the logic for the FPGA global bit is not universal between Gen5
and Gen10 devices is not the same. Disabling this bit, while applicable to
Gen10 devices, will break FPGA programming on Gen5 devices.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Diffstat (limited to 'drivers/fpga')
| -rw-r--r-- | drivers/fpga/socfpga.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c index 431e159e48..4448250f5c 100644 --- a/drivers/fpga/socfpga.c +++ b/drivers/fpga/socfpga.c @@ -269,7 +269,7 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size) /* Prior programming the FPGA, all bridges need to be shut off */ /* Disable all signals from hps peripheral controller to fpga */ - writel(0, &sysmgr_regs->fpgaintfgrp_gbl); + writel(0, &sysmgr_regs->fpgaintfgrp_module); /* Disable all signals from FPGA to HPS SDRAM */ #define SDR_CTRLGRP_FPGAPORTRST_ADDRESS 0x5080 |