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| author | Andre Przywara <andre.przywara@arm.com> | 2019-01-29 15:54:09 +0000 |
|---|---|---|
| committer | Jagan Teki <jagan@amarulasolutions.com> | 2019-01-29 23:30:11 +0530 |
| commit | bb3e5aa2896d69a6fe86861004d7d4e33824efbe (patch) | |
| tree | 8f38de7357c03681bc0309bd76ab52fe00e02e06 /drivers/clk/sunxi/clk_v3s.c | |
| parent | 1659156c74fb575d851fc1f43818d232712e776b (diff) | |
| download | u-boot-bb3e5aa2896d69a6fe86861004d7d4e33824efbe.tar.gz u-boot-bb3e5aa2896d69a6fe86861004d7d4e33824efbe.tar.bz2 u-boot-bb3e5aa2896d69a6fe86861004d7d4e33824efbe.zip | |
sunxi: clk: add MMC gates/resets
Add the MMC clock gates and reset bits for all the Allwinner SoCs.
This allows them to be used by the MMC driver.
We don't advertise the mod clock yet, as this is still handled by the
MMC driver.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[jagan: add V3S, A80 gates/resets]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Diffstat (limited to 'drivers/clk/sunxi/clk_v3s.c')
| -rw-r--r-- | drivers/clk/sunxi/clk_v3s.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c index 25ad87500e..c8a9027889 100644 --- a/drivers/clk/sunxi/clk_v3s.c +++ b/drivers/clk/sunxi/clk_v3s.c @@ -13,6 +13,9 @@ #include <dt-bindings/reset/sun8i-v3s-ccu.h> static struct ccu_clk_gate v3s_gates[] = { + [CLK_BUS_MMC0] = GATE(0x060, BIT(8)), + [CLK_BUS_MMC1] = GATE(0x060, BIT(9)), + [CLK_BUS_MMC2] = GATE(0x060, BIT(10)), [CLK_BUS_OTG] = GATE(0x060, BIT(24)), [CLK_BUS_UART0] = GATE(0x06c, BIT(16)), @@ -25,6 +28,9 @@ static struct ccu_clk_gate v3s_gates[] = { static struct ccu_reset v3s_resets[] = { [RST_USB_PHY0] = RESET(0x0cc, BIT(0)), + [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)), + [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)), + [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)), [RST_BUS_OTG] = RESET(0x2c0, BIT(24)), [RST_BUS_UART0] = RESET(0x2d8, BIT(16)), |