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| author | Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> | 2018-01-16 20:44:27 +0300 |
|---|---|---|
| committer | Alexey Brodkin <abrodkin@synopsys.com> | 2018-01-19 17:59:35 +0300 |
| commit | 320c8a1a860e91983955b9d69014324a1c1c0ad8 (patch) | |
| tree | c35440ed9cfce09503ed7ea1d6bb495296a2c57b /drivers/clk/clk-hsdk-cgu.c | |
| parent | f6d7812d8d9ca2b0b04d2825b820160e8bdd79c8 (diff) | |
| download | u-boot-320c8a1a860e91983955b9d69014324a1c1c0ad8.tar.gz u-boot-320c8a1a860e91983955b9d69014324a1c1c0ad8.tar.bz2 u-boot-320c8a1a860e91983955b9d69014324a1c1c0ad8.zip | |
ARC: HSDK: CGU: Add 'Hz' when printing clock frequency
Add 'Hz' when printing clock frequency in error messages.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Diffstat (limited to 'drivers/clk/clk-hsdk-cgu.c')
| -rw-r--r-- | drivers/clk/clk-hsdk-cgu.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/clk/clk-hsdk-cgu.c b/drivers/clk/clk-hsdk-cgu.c index 64bb1db821..4362d583cb 100644 --- a/drivers/clk/clk-hsdk-cgu.c +++ b/drivers/clk/clk-hsdk-cgu.c @@ -492,7 +492,7 @@ static ulong pll_set(struct clk *sclk, ulong rate) } } - pr_err("invalid rate=%ld, parent_rate=%d\n", best_rate, PARENT_RATE); + pr_err("invalid rate=%ld Hz, parent_rate=%d Hz\n", best_rate, PARENT_RATE); return -EINVAL; } @@ -623,14 +623,14 @@ static ulong idiv_set(struct clk *sclk, ulong rate) } if (div_factor & ~CGU_IDIV_MASK) { - pr_err("invalid rate=%ld, parent_rate=%ld, div=%d: max divider valie is%d\n", + pr_err("invalid rate=%ld Hz, parent_rate=%ld Hz, div=%d: max divider valie is%d\n", rate, parent_rate, div_factor, CGU_IDIV_MASK); div_factor = CGU_IDIV_MASK; } if (div_factor == 0) { - pr_err("invalid rate=%ld, parent_rate=%ld, div=%d: min divider valie is 1\n", + pr_err("invalid rate=%ld Hz, parent_rate=%ld Hz, div=%d: min divider valie is 1\n", rate, parent_rate, div_factor); div_factor = 1; |