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author | Ryder Lee <ryder.lee@mediatek.com> | 2018-11-15 10:07:54 +0800 |
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committer | Tom Rini <trini@konsulko.com> | 2018-11-28 23:04:51 -0500 |
commit | 0bd7dc74d2ffee99b931606b94469f9c9ab9bbf1 (patch) | |
tree | 9968817f4c0d3b1af72595059403e78302e41e02 /drivers/clk/Makefile | |
parent | 361e13f1d5c893caf40a6026405c0e1b615e90ea (diff) | |
download | u-boot-0bd7dc74d2ffee99b931606b94469f9c9ab9bbf1.tar.gz u-boot-0bd7dc74d2ffee99b931606b94469f9c9ab9bbf1.tar.bz2 u-boot-0bd7dc74d2ffee99b931606b94469f9c9ab9bbf1.zip |
clk: MediaTek: add clock driver for MT7629 SoC.
This patch adds clock modules for MediaTek SoCs:
- Shared part: a common driver which contains the general operations
for plls, muxes, dividers and gates so that we can reuse it in future.
- Specific SoC part: the group of structures used to hold the hardware
configuration for each SoC.
We take MT7629 as an example to demonstrate how to implement driver if
any other MediaTek chips would like to use it.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'drivers/clk/Makefile')
-rw-r--r-- | drivers/clk/Makefile | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 821b5867e8..c128538303 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -10,6 +10,7 @@ obj-y += imx/ obj-y += tegra/ obj-$(CONFIG_ARCH_ASPEED) += aspeed/ obj-$(CONFIG_ARCH_MESON) += clk_meson.o +obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ obj-$(CONFIG_ARCH_SOCFPGA) += altera/ obj-$(CONFIG_CLK_AT91) += at91/ |