diff options
| author | Patrice Chotard <patrice.chotard@st.com> | 2017-07-18 17:37:27 +0200 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2017-07-26 11:29:15 -0400 |
| commit | f303aaf21b968ab959edcc354892f9eca8907e0b (patch) | |
| tree | 9116053595de57030e108158f5ceba95ac76bfb6 /doc | |
| parent | f39b90dc8c2b6da6665fa4c7dcd47d32cbe07a29 (diff) | |
| download | u-boot-f303aaf21b968ab959edcc354892f9eca8907e0b.tar.gz u-boot-f303aaf21b968ab959edcc354892f9eca8907e0b.tar.bz2 u-boot-f303aaf21b968ab959edcc354892f9eca8907e0b.zip | |
ram: stm32: add second SDRAM bank management
FMC is able to manage 2 SDRAM banks, but the current driver
implementation is only able to manage the first SDRAM bank.
Even if only bank2 is used, some bank1 registers must be
configured.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'doc')
| -rw-r--r-- | doc/device-tree-bindings/ram/st,stm32-fmc.txt | 19 |
1 files changed, 13 insertions, 6 deletions
diff --git a/doc/device-tree-bindings/ram/st,stm32-fmc.txt b/doc/device-tree-bindings/ram/st,stm32-fmc.txt index 3d1392c764..99f76d515f 100644 --- a/doc/device-tree-bindings/ram/st,stm32-fmc.txt +++ b/doc/device-tree-bindings/ram/st,stm32-fmc.txt @@ -40,12 +40,19 @@ Example: pinctrl-names = "default"; status = "okay"; - mr-nbanks = <1>; /* sdram memory configuration from sdram datasheet */ - bank1: bank@0 { - st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_2 + bank1: bank@0 { + st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_2 CAS_3 RD_BURST_EN RD_PIPE_DL_0>; - st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18 + st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18 TRCD_18>; - }; -} + }; + + /* sdram memory configuration from sdram datasheet */ + bank2: bank@1 { + st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_2 + CAS_3 RD_BURST_EN RD_PIPE_DL_0>; + st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18 + TRCD_18>; + }; + } |