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| author | york <yorksun@freescale.com> | 2010-07-02 22:25:52 +0000 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2010-07-26 13:16:09 -0500 |
| commit | 076bff8f4746baf7c83b96049d97e9dd4454dace (patch) | |
| tree | 8a55f11be0a24163a7c6e59686b72b91ae4ea3d8 /doc | |
| parent | 79e4e6480b359cb28129cecfa2cae0ef9cccf803 (diff) | |
| download | u-boot-076bff8f4746baf7c83b96049d97e9dd4454dace.tar.gz u-boot-076bff8f4746baf7c83b96049d97e9dd4454dace.tar.bz2 u-boot-076bff8f4746baf7c83b96049d97e9dd4454dace.zip | |
powerpc/8xxx: Fix bug in memctrl interleaving & bank interleaving on cs0~cs4
Verified on MPC8641HPCN with four DDR2 dimms. Each dimm has dual
rank with 512MB each rank.
Also check dimm size and rank size for memory controller interleaving
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'doc')
| -rw-r--r-- | doc/README.fsl-ddr | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/doc/README.fsl-ddr b/doc/README.fsl-ddr index 6e4f6e9244..8c37bbead1 100644 --- a/doc/README.fsl-ddr +++ b/doc/README.fsl-ddr @@ -27,6 +27,9 @@ Table of interleaving modes supported in cpu/8xxx/ddr/ from each controller. {CS2+CS3} on each controller are only rank interleaved on that controller. + For memory controller interleaving, identical DIMMs are suggested. Software + doesn't check the size or organization of interleaved DIMMs. + The ways to configure the ddr interleaving mode ============================================== 1. In board header file(e.g.MPC8572DS.h), add default interleaving setting |