diff options
author | Michael Walle <michael@walle.cc> | 2021-11-15 23:45:43 +0100 |
---|---|---|
committer | Priyanka Jain <priyanka.jain@nxp.com> | 2022-02-28 11:59:35 +0530 |
commit | f606c9a8959728f7df539e182fb799d3ccc92cc6 (patch) | |
tree | 08011f8cb6f63185e27342f8393e287f4a77e31d /doc/board | |
parent | 42595eb7067c6c076e1c98213438be727f883fe2 (diff) | |
download | u-boot-f606c9a8959728f7df539e182fb799d3ccc92cc6.tar.gz u-boot-f606c9a8959728f7df539e182fb799d3ccc92cc6.tar.bz2 u-boot-f606c9a8959728f7df539e182fb799d3ccc92cc6.zip |
watchdog: add sl28cpld watchdog driver
The watchdog timer is part of the sl28cpld management controller. The
watchdog timer usually supervises the bootloader boot-up and if it bites
the failsafe bootloader will be activated. Apart from that it supports
the usual board level reset and one SMARC speciality: driving the
WDT_TIMEOUT# signal.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Diffstat (limited to 'doc/board')
-rw-r--r-- | doc/board/kontron/sl28.rst | 53 |
1 files changed, 36 insertions, 17 deletions
diff --git a/doc/board/kontron/sl28.rst b/doc/board/kontron/sl28.rst index c7b18bed10..c2cdc5e424 100644 --- a/doc/board/kontron/sl28.rst +++ b/doc/board/kontron/sl28.rst @@ -35,23 +35,6 @@ The board is fully failsafe, you can't break anything. But because you've disabled the builtin watchdog you might have to manually enter failsafe mode by asserting the ``FORCE_RECOV#`` line during board reset. -Disable the builtin watchdog -^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -- boot into the failsafe bootloader, either by asserting the - ``FORCE_RECOV#`` line or if you still have the original bootloader - installed you can use the command:: - - > wdt dev cpld_watchdog@4a; wdt expire 1 - -- in the failsafe bootloader use the "sl28 nvm" command to disable - the automatic start of the builtin watchdog:: - - > sl28 nvm 0008 - -- power-cycle the board - - Update image ------------ @@ -82,6 +65,42 @@ u-boot (yet). But you can use the i2c command to access it. > i2c md 4a 3.1 1 +Builtin watchdog +---------------- + +The builtin watchdog will supervise the bootloader startup. If anything +goes wrong it will reset the board and boot into the failsafe bootloader. + +Once the bootloader is started successfully, it will disable the watchdog +timer. + +wdt command flags +^^^^^^^^^^^^^^^^^ + +The `wdt start` as well as the `wdt expire` command take a flags argument. +The supported bitmask is as follows. + +| Bit | Description | +| --- | ----------------------------- | +| 0 | Enable failsafe mode | +| 1 | Lock the control register | +| 2 | Disable board reset | +| 3 | Enable WDT_TIME_OUT# line | + +For example, you can use `wdt expire 1` to issue a reset and boot into the +failsafe bootloader. + +Disable the builtin watchdog +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +If for some reason, this isn't a desired behavior, the watchdog can also +be configured to not be enabled on board reset. It's configuration is saved +in the non-volatile board configuration bits. To change these you can use +the `sl28 nvm` command. + +For more information on the non-volatile board configuration bits, see the +following section. + Non-volatile Board Configuration Bits ------------------------------------- |