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| author | Haiying Wang <Haiying.Wang@freescale.com> | 2009-01-13 16:29:22 -0500 |
|---|---|---|
| committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | 2009-01-13 16:47:07 -0600 |
| commit | 950264317eb9594b2b5ee2fb65206200a1c6007a (patch) | |
| tree | 255119caa0618014d075f5ea680522c2326ad5b1 /cpu | |
| parent | 6d3a10f73ece7ffb736890c10e023222612a4aa0 (diff) | |
| download | u-boot-950264317eb9594b2b5ee2fb65206200a1c6007a.tar.gz u-boot-950264317eb9594b2b5ee2fb65206200a1c6007a.tar.bz2 u-boot-950264317eb9594b2b5ee2fb65206200a1c6007a.zip | |
Change DDR tlb start entry to CONFIG param for 85xx
So that we can locate the DDR tlb start entry to the value other than 8. By
default, it is still 8.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Diffstat (limited to 'cpu')
| -rw-r--r-- | cpu/mpc85xx/tlb.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/cpu/mpc85xx/tlb.c b/cpu/mpc85xx/tlb.c index 5b5f7914f2..25fa9ee8f8 100644 --- a/cpu/mpc85xx/tlb.c +++ b/cpu/mpc85xx/tlb.c @@ -125,6 +125,10 @@ void init_addr_map(void) } #endif +#ifndef CONFIG_SYS_DDR_TLB_START +#define CONFIG_SYS_DDR_TLB_START 8 +#endif + unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg) { unsigned int tlb_size; @@ -171,7 +175,7 @@ unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg) * Configure DDR TLB1 entries. * Starting at TLB1 8, use no more than 8 TLB1 entries. */ - ram_tlb_index = 8; + ram_tlb_index = CONFIG_SYS_DDR_TLB_START; ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE; while (ram_tlb_address < (memsize_in_meg * 1024 * 1024) && ram_tlb_index < 16) { |