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| author | Andre Przywara <andre.przywara@arm.com> | 2019-07-15 02:27:06 +0100 |
|---|---|---|
| committer | Jagan Teki <jagan@amarulasolutions.com> | 2019-07-16 17:09:31 +0530 |
| commit | 770b85a4180e5173c57c3297a4e28647e041f63a (patch) | |
| tree | 36288a5cd66bae0123a31c85311a3414061cd83a /configs | |
| parent | 65f80f58049a820e7d1ed7b0b0d233885ce6ebb2 (diff) | |
| download | u-boot-770b85a4180e5173c57c3297a4e28647e041f63a.tar.gz u-boot-770b85a4180e5173c57c3297a4e28647e041f63a.tar.bz2 u-boot-770b85a4180e5173c57c3297a4e28647e041f63a.zip | |
sunxi: H6: move LPDDR3 timing definition into separate file
Currently the H6 DRAM driver only supports one kind of LPDDR3 DRAM.
Split the timing parameters for this LPDDR3 configuration into a
separate file, to allow selecting an alternative later at compile time
(as the sunxi-dw driver does).
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Diffstat (limited to 'configs')
| -rw-r--r-- | configs/beelink_gs1_defconfig | 1 | ||||
| -rw-r--r-- | configs/orangepi_lite2_defconfig | 1 | ||||
| -rw-r--r-- | configs/orangepi_one_plus_defconfig | 1 | ||||
| -rw-r--r-- | configs/pine_h64_defconfig | 1 |
4 files changed, 4 insertions, 0 deletions
diff --git a/configs/beelink_gs1_defconfig b/configs/beelink_gs1_defconfig index f5de850d08..eec4edd4c2 100644 --- a/configs/beelink_gs1_defconfig +++ b/configs/beelink_gs1_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_SUNXI=y CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN50I_H6=y +CONFIG_SUNXI_DRAM_H6_LPDDR3=y CONFIG_MMC0_CD_PIN="PF6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_PSCI_RESET is not set diff --git a/configs/orangepi_lite2_defconfig b/configs/orangepi_lite2_defconfig index f6d023eea7..2d74fc4053 100644 --- a/configs/orangepi_lite2_defconfig +++ b/configs/orangepi_lite2_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_SUNXI=y CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN50I_H6=y +CONFIG_SUNXI_DRAM_H6_LPDDR3=y CONFIG_MMC0_CD_PIN="PF6" # CONFIG_PSCI_RESET is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set diff --git a/configs/orangepi_one_plus_defconfig b/configs/orangepi_one_plus_defconfig index a9d560a917..3737ecd378 100644 --- a/configs/orangepi_one_plus_defconfig +++ b/configs/orangepi_one_plus_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_SUNXI=y CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN50I_H6=y +CONFIG_SUNXI_DRAM_H6_LPDDR3=y CONFIG_MMC0_CD_PIN="PF6" # CONFIG_PSCI_RESET is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set diff --git a/configs/pine_h64_defconfig b/configs/pine_h64_defconfig index 5fa279f2e7..a49bd6618f 100644 --- a/configs/pine_h64_defconfig +++ b/configs/pine_h64_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_SUNXI=y CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN50I_H6=y +CONFIG_SUNXI_DRAM_H6_LPDDR3=y CONFIG_MMC0_CD_PIN="PF6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_PSCI_RESET is not set |