diff options
| author | Hans de Goede <hdegoede@redhat.com> | 2014-11-21 17:19:45 +0100 |
|---|---|---|
| committer | Hans de Goede <hdegoede@redhat.com> | 2014-11-25 13:38:46 +0100 |
| commit | eafec32000499c8f20589e44801c9febff9ce101 (patch) | |
| tree | f1604ccbd2902e1b082fde18377efeae09fa36fc /board | |
| parent | b871f636c70a2371a8e50190177e4f86d31094fb (diff) | |
| download | u-boot-eafec32000499c8f20589e44801c9febff9ce101.tar.gz u-boot-eafec32000499c8f20589e44801c9febff9ce101.tar.bz2 u-boot-eafec32000499c8f20589e44801c9febff9ce101.zip | |
sun6i: Add gmac support for sun6i boards
Hookup the gmac found on the sun6i / A31 SoCs.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Diffstat (limited to 'board')
| -rw-r--r-- | board/sunxi/gmac.c | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/board/sunxi/gmac.c b/board/sunxi/gmac.c index 051aca01a8..571bc9e0ab 100644 --- a/board/sunxi/gmac.c +++ b/board/sunxi/gmac.c @@ -13,7 +13,12 @@ int sunxi_gmac_initialize(bd_t *bis) (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; /* Set up clock gating */ +#ifndef CONFIG_MACH_SUN6I setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC); +#else + setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_RESET_OFFSET_GMAC); + setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_GMAC); +#endif /* Set MII clock */ #ifdef CONFIG_RGMII @@ -33,6 +38,7 @@ int sunxi_gmac_initialize(bd_t *bis) setbits_le32(&ccm->gmac_clk_cfg, 0x3 << 10); #endif +#ifndef CONFIG_MACH_SUN6I /* Configure pin mux settings for GMAC */ for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) { #ifdef CONFIG_RGMII @@ -43,9 +49,48 @@ int sunxi_gmac_initialize(bd_t *bis) sunxi_gpio_set_cfgpin(pin, SUN7I_GPA0_GMAC); sunxi_gpio_set_drv(pin, 3); } +#elif defined CONFIG_RGMII + /* Configure sun6i RGMII mode pin mux settings */ + for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++) { + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC); + sunxi_gpio_set_drv(pin, 3); + } + for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) { + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC); + sunxi_gpio_set_drv(pin, 3); + } + for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(20); pin++) { + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC); + sunxi_gpio_set_drv(pin, 3); + } + for (pin = SUNXI_GPA(25); pin <= SUNXI_GPA(27); pin++) { + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC); + sunxi_gpio_set_drv(pin, 3); + } +#elif defined CONFIG_GMII + /* Configure sun6i GMII mode pin mux settings */ + for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(27); pin++) { + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC); + sunxi_gpio_set_drv(pin, 2); + } +#else + /* Configure sun6i MII mode pin mux settings */ + for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++) + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC); + for (pin = SUNXI_GPA(8); pin <= SUNXI_GPA(9); pin++) + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC); + for (pin = SUNXI_GPA(11); pin <= SUNXI_GPA(14); pin++) + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC); + for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(24); pin++) + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC); + for (pin = SUNXI_GPA(26); pin <= SUNXI_GPA(27); pin++) + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC); +#endif #ifdef CONFIG_RGMII return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_RGMII); +#elif defined CONFIG_GMII + return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_GMII); #else return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_MII); #endif |